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QMP: Fix asynchronous events delivery
[qemu.git] / hw / omap_dma.c
CommitLineData
b4e3104b
AZ		 1/*
2 * TI OMAP DMA gigacell.
3 *
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <[email protected]>
5 * Copyright (C) 2007-2008 Lauro Ramos Venancio <[email protected]>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
fad6cb1a 17 * You should have received a copy of the GNU General Public License along
8167ee88 18 * with this program; if not, see <http://www.gnu.org/licenses/>.
b4e3104b
AZ		 19 */
20#include "qemu-common.h"
21#include "qemu-timer.h"
22#include "omap.h"
23#include "irq.h"
afbb5194 24#include "soc_dma.h"
b4e3104b
AZ		 25
26struct omap_dma_channel_s {
27 /* transfer data */
28 int burst[2];
29 int pack[2];
827df9f3
AZ		 30 int endian[2];
31 int endian_lock[2];
32 int translate[2];
b4e3104b 33 enum omap_dma_port port[2];
c227f099
AL		 34 target_phys_addr_t addr[2];
35 omap_dma_addressing_t mode[2];
827df9f3 36 uint32_t elements;
b4e3104b 37 uint16_t frames;
827df9f3 38 int32_t frame_index[2];
b4e3104b
AZ		 39 int16_t element_index[2];
40 int data_type;
41
42 /* transfer type */
43 int transparent_copy;
44 int constant_fill;
45 uint32_t color;
827df9f3 46 int prefetch;
b4e3104b
AZ		 47
48 /* auto init and linked channel data */
49 int end_prog;
50 int repeat;
51 int auto_init;
52 int link_enabled;
53 int link_next_ch;
54
55 /* interruption data */
56 int interrupts;
57 int status;
827df9f3 58 int cstatus;
b4e3104b
AZ		 59
60 /* state data */
61 int active;
62 int enable;
63 int sync;
827df9f3 64 int src_sync;
b4e3104b
AZ		 65 int pending_request;
66 int waiting_end_prog;
67 uint16_t cpc;
afbb5194 68 int set_update;
b4e3104b
AZ		 69
70 /* sync type */
71 int fs;
72 int bs;
73
74 /* compatibility */
75 int omap_3_1_compatible_disable;
76
77 qemu_irq irq;
78 struct omap_dma_channel_s *sibling;
79
80 struct omap_dma_reg_set_s {
c227f099 81 target_phys_addr_t src, dest;
b4e3104b
AZ		 82 int frame;
83 int element;
827df9f3 84 int pck_element;
b4e3104b
AZ		 85 int frame_delta[2];
86 int elem_delta[2];
87 int frames;
88 int elements;
827df9f3 89 int pck_elements;
b4e3104b
AZ		 90 } active_set;
91
afbb5194
AZ		 92 struct soc_dma_ch_s *dma;
93
b4e3104b 94 /* unused parameters */
827df9f3 95 int write_mode;
b4e3104b
AZ		 96 int priority;
97 int interleave_disabled;
98 int type;
827df9f3
AZ		 99 int suspend;
100 int buf_disable;
b4e3104b
AZ		 101};
102
103struct omap_dma_s {
afbb5194
AZ		 104 struct soc_dma_s *dma;
105
b4e3104b 106 struct omap_mpu_state_s *mpu;
b4e3104b 107 omap_clk clk;
827df9f3
AZ		 108 qemu_irq irq[4];
109 void (*intr_update)(struct omap_dma_s *s);
b4e3104b
AZ		 110 enum omap_dma_model model;
111 int omap_3_1_mapping_disabled;
112
827df9f3
AZ		 113 uint32_t gcr;
114 uint32_t ocp;
115 uint32_t caps[5];
116 uint32_t irqen[4];
117 uint32_t irqstat[4];
b4e3104b
AZ		 118
119 int chans;
827df9f3 120 struct omap_dma_channel_s ch[32];
b4e3104b
AZ		 121 struct omap_dma_lcd_channel_s lcd_ch;
122};
123
124/* Interrupts */
125#define TIMEOUT_INTR (1 << 0)
126#define EVENT_DROP_INTR (1 << 1)
127#define HALF_FRAME_INTR (1 << 2)
128#define END_FRAME_INTR (1 << 3)
129#define LAST_FRAME_INTR (1 << 4)
130#define END_BLOCK_INTR (1 << 5)
131#define SYNC (1 << 6)
827df9f3
AZ		 132#define END_PKT_INTR (1 << 7)
133#define TRANS_ERR_INTR (1 << 8)
134#define MISALIGN_INTR (1 << 11)
b4e3104b 135
827df9f3 136static inline void omap_dma_interrupts_update(struct omap_dma_s *s)
b4e3104b 137{
827df9f3 138 return s->intr_update(s);
b4e3104b
AZ		 139}
140
afbb5194 141static void omap_dma_channel_load(struct omap_dma_channel_s *ch)
b4e3104b
AZ		 142{
143 struct omap_dma_reg_set_s *a = &ch->active_set;
afbb5194 144 int i, normal;
b4e3104b
AZ		 145 int omap_3_1 = !ch->omap_3_1_compatible_disable;
146
147 /*
148 * TODO: verify address ranges and alignment
149 * TODO: port endianness
150 */
151
152 a->src = ch->addr[0];
153 a->dest = ch->addr[1];
154 a->frames = ch->frames;
155 a->elements = ch->elements;
827df9f3 156 a->pck_elements = ch->frame_index[!ch->src_sync];
b4e3104b
AZ		 157 a->frame = 0;
158 a->element = 0;
827df9f3 159 a->pck_element = 0;
b4e3104b
AZ		 160
161 if (unlikely(!ch->elements || !ch->frames)) {
162 printf("%s: bad DMA request\n", __FUNCTION__);
163 return;
164 }
165
166 for (i = 0; i < 2; i ++)
167 switch (ch->mode[i]) {
168 case constant:
169 a->elem_delta[i] = 0;
170 a->frame_delta[i] = 0;
171 break;
172 case post_incremented:
173 a->elem_delta[i] = ch->data_type;
174 a->frame_delta[i] = 0;
175 break;
176 case single_index:
177 a->elem_delta[i] = ch->data_type +
178 ch->element_index[omap_3_1 ? 0 : i] - 1;
179 a->frame_delta[i] = 0;
180 break;
181 case double_index:
182 a->elem_delta[i] = ch->data_type +
183 ch->element_index[omap_3_1 ? 0 : i] - 1;
184 a->frame_delta[i] = ch->frame_index[omap_3_1 ? 0 : i] -
185 ch->element_index[omap_3_1 ? 0 : i];
186 break;
187 default:
188 break;
189 }
afbb5194
AZ		 190
191 normal = !ch->transparent_copy && !ch->constant_fill &&
192 /* FIFO is big-endian so either (ch->endian[n] == 1) OR
193 * (ch->endian_lock[n] == 1) mean no endianism conversion. */
194 (ch->endian[0] | ch->endian_lock[0]) ==
195 (ch->endian[1] | ch->endian_lock[1]);
196 for (i = 0; i < 2; i ++) {
197 /* TODO: for a->frame_delta[i] > 0 still use the fast path, just
198 * limit min_elems in omap_dma_transfer_setup to the nearest frame
199 * end. */
200 if (!a->elem_delta[i] && normal &&
201 (a->frames == 1 || !a->frame_delta[i]))
202 ch->dma->type[i] = soc_dma_access_const;
203 else if (a->elem_delta[i] == ch->data_type && normal &&
204 (a->frames == 1 || !a->frame_delta[i]))
205 ch->dma->type[i] = soc_dma_access_linear;
206 else
207 ch->dma->type[i] = soc_dma_access_other;
208
209 ch->dma->vaddr[i] = ch->addr[i];
210 }
211 soc_dma_ch_update(ch->dma);
b4e3104b
AZ		 212}
213
214static void omap_dma_activate_channel(struct omap_dma_s *s,
215 struct omap_dma_channel_s *ch)
216{
217 if (!ch->active) {
afbb5194
AZ		 218 if (ch->set_update) {
219 /* It's not clear when the active set is supposed to be
220 * loaded from registers. We're already loading it when the
221 * channel is enabled, and for some guests this is not enough
222 * but that may be also because of a race condition (no
223 * delays in qemu) in the guest code, which we're just
224 * working around here. */
225 omap_dma_channel_load(ch);
226 ch->set_update = 0;
227 }
228
b4e3104b 229 ch->active = 1;
afbb5194 230 soc_dma_set_request(ch->dma, 1);
b4e3104b
AZ		 231 if (ch->sync)
232 ch->status |= SYNC;
b4e3104b 233 }
b4e3104b
AZ		 234}
235
236static void omap_dma_deactivate_channel(struct omap_dma_s *s,
237 struct omap_dma_channel_s *ch)
238{
239 /* Update cpc */
240 ch->cpc = ch->active_set.dest & 0xffff;
241
827df9f3 242 if (ch->pending_request && !ch->waiting_end_prog && ch->enable) {
b4e3104b
AZ		 243 /* Don't deactivate the channel */
244 ch->pending_request = 0;
827df9f3 245 return;
b4e3104b
AZ		 246 }
247
248 /* Don't deactive the channel if it is synchronized and the DMA request is
249 active */
afbb5194 250 if (ch->sync && ch->enable && (s->dma->drqbmp & (1 << ch->sync)))
b4e3104b
AZ		 251 return;
252
253 if (ch->active) {
254 ch->active = 0;
255 ch->status &= ~SYNC;
afbb5194 256 soc_dma_set_request(ch->dma, 0);
b4e3104b 257 }
b4e3104b
AZ		 258}
259
260static void omap_dma_enable_channel(struct omap_dma_s *s,
261 struct omap_dma_channel_s *ch)
262{
263 if (!ch->enable) {
264 ch->enable = 1;
265 ch->waiting_end_prog = 0;
afbb5194 266 omap_dma_channel_load(ch);
827df9f3 267 /* TODO: theoretically if ch->sync && ch->prefetch &&
afbb5194
AZ		 268 * !s->dma->drqbmp[ch->sync], we should also activate and fetch
269 * from source and then stall until signalled. */
270 if ((!ch->sync) || (s->dma->drqbmp & (1 << ch->sync)))
b4e3104b
AZ		 271 omap_dma_activate_channel(s, ch);
272 }
273}
274
275static void omap_dma_disable_channel(struct omap_dma_s *s,
276 struct omap_dma_channel_s *ch)
277{
278 if (ch->enable) {
279 ch->enable = 0;
280 /* Discard any pending request */
281 ch->pending_request = 0;
282 omap_dma_deactivate_channel(s, ch);
283 }
284}
285
286static void omap_dma_channel_end_prog(struct omap_dma_s *s,
287 struct omap_dma_channel_s *ch)
288{
289 if (ch->waiting_end_prog) {
290 ch->waiting_end_prog = 0;
291 if (!ch->sync || ch->pending_request) {
292 ch->pending_request = 0;
293 omap_dma_activate_channel(s, ch);
294 }
295 }
296}
297
827df9f3
AZ		 298static void omap_dma_interrupts_3_1_update(struct omap_dma_s *s)
299{
300 struct omap_dma_channel_s *ch = s->ch;
301
302 /* First three interrupts are shared between two channels each. */
303 if (ch[0].status | ch[6].status)
304 qemu_irq_raise(ch[0].irq);
305 if (ch[1].status | ch[7].status)
306 qemu_irq_raise(ch[1].irq);
307 if (ch[2].status | ch[8].status)
308 qemu_irq_raise(ch[2].irq);
309 if (ch[3].status)
310 qemu_irq_raise(ch[3].irq);
311 if (ch[4].status)
312 qemu_irq_raise(ch[4].irq);
313 if (ch[5].status)
314 qemu_irq_raise(ch[5].irq);
315}
316
317static void omap_dma_interrupts_3_2_update(struct omap_dma_s *s)
318{
319 struct omap_dma_channel_s *ch = s->ch;
320 int i;
321
322 for (i = s->chans; i; ch ++, i --)
323 if (ch->status)
324 qemu_irq_raise(ch->irq);
325}
326
b4e3104b
AZ		 327static void omap_dma_enable_3_1_mapping(struct omap_dma_s *s)
328{
329 s->omap_3_1_mapping_disabled = 0;
330 s->chans = 9;
827df9f3 331 s->intr_update = omap_dma_interrupts_3_1_update;
b4e3104b
AZ		 332}
333
334static void omap_dma_disable_3_1_mapping(struct omap_dma_s *s)
335{
336 s->omap_3_1_mapping_disabled = 1;
337 s->chans = 16;
827df9f3 338 s->intr_update = omap_dma_interrupts_3_2_update;
b4e3104b
AZ		 339}
340
341static void omap_dma_process_request(struct omap_dma_s *s, int request)
342{
343 int channel;
344 int drop_event = 0;
345 struct omap_dma_channel_s *ch = s->ch;
346
347 for (channel = 0; channel < s->chans; channel ++, ch ++) {
348 if (ch->enable && ch->sync == request) {
349 if (!ch->active)
350 omap_dma_activate_channel(s, ch);
351 else if (!ch->pending_request)
352 ch->pending_request = 1;
353 else {
354 /* Request collision */
355 /* Second request received while processing other request */
356 ch->status |= EVENT_DROP_INTR;
357 drop_event = 1;
358 }
359 }
360 }
361
362 if (drop_event)
363 omap_dma_interrupts_update(s);
364}
365
afbb5194 366static void omap_dma_transfer_generic(struct soc_dma_ch_s *dma)
b4e3104b 367{
b4e3104b 368 uint8_t value[4];
afbb5194
AZ		 369 struct omap_dma_channel_s *ch = dma->opaque;
370 struct omap_dma_reg_set_s *a = &ch->active_set;
371 int bytes = dma->bytes;
372#ifdef MULTI_REQ
373 uint16_t status = ch->status;
374#endif
b4e3104b 375
afbb5194
AZ		 376 do {
377 /* Transfer a single element */
378 /* FIXME: check the endianness */
379 if (!ch->constant_fill)
380 cpu_physical_memory_read(a->src, value, ch->data_type);
381 else
382 *(uint32_t *) value = ch->color;
383
384 if (!ch->transparent_copy || *(uint32_t *) value != ch->color)
385 cpu_physical_memory_write(a->dest, value, ch->data_type);
386
387 a->src += a->elem_delta[0];
388 a->dest += a->elem_delta[1];
389 a->element ++;
390
391#ifndef MULTI_REQ
392 if (a->element == a->elements) {
393 /* End of Frame */
394 a->element = 0;
395 a->src += a->frame_delta[0];
396 a->dest += a->frame_delta[1];
397 a->frame ++;
398
399 /* If the channel is async, update cpc */
400 if (!ch->sync)
401 ch->cpc = a->dest & 0xffff;
402 }
403 } while ((bytes -= ch->data_type));
404#else
405 /* If the channel is element synchronized, deactivate it */
406 if (ch->sync && !ch->fs && !ch->bs)
b4e3104b 407 omap_dma_deactivate_channel(s, ch);
afbb5194
AZ		 408
409 /* If it is the last frame, set the LAST_FRAME interrupt */
410 if (a->element == 1 && a->frame == a->frames - 1)
411 if (ch->interrupts & LAST_FRAME_INTR)
412 ch->status |= LAST_FRAME_INTR;
413
414 /* If the half of the frame was reached, set the HALF_FRAME
415 interrupt */
416 if (a->element == (a->elements >> 1))
417 if (ch->interrupts & HALF_FRAME_INTR)
418 ch->status |= HALF_FRAME_INTR;
419
420 if (ch->fs && ch->bs) {
421 a->pck_element ++;
422 /* Check if a full packet has beed transferred. */
423 if (a->pck_element == a->pck_elements) {
424 a->pck_element = 0;
425
426 /* Set the END_PKT interrupt */
427 if ((ch->interrupts & END_PKT_INTR) && !ch->src_sync)
428 ch->status |= END_PKT_INTR;
429
430 /* If the channel is packet-synchronized, deactivate it */
431 if (ch->sync)
432 omap_dma_deactivate_channel(s, ch);
433 }
b4e3104b
AZ		 434 }
435
afbb5194
AZ		 436 if (a->element == a->elements) {
437 /* End of Frame */
438 a->element = 0;
439 a->src += a->frame_delta[0];
440 a->dest += a->frame_delta[1];
441 a->frame ++;
442
443 /* If the channel is frame synchronized, deactivate it */
444 if (ch->sync && ch->fs && !ch->bs)
b4e3104b
AZ		 445 omap_dma_deactivate_channel(s, ch);
446
afbb5194
AZ		 447 /* If the channel is async, update cpc */
448 if (!ch->sync)
449 ch->cpc = a->dest & 0xffff;
450
451 /* Set the END_FRAME interrupt */
452 if (ch->interrupts & END_FRAME_INTR)
453 ch->status |= END_FRAME_INTR;
454
455 if (a->frame == a->frames) {
456 /* End of Block */
457 /* Disable the channel */
458
459 if (ch->omap_3_1_compatible_disable) {
460 omap_dma_disable_channel(s, ch);
461 if (ch->link_enabled)
462 omap_dma_enable_channel(s,
463 &s->ch[ch->link_next_ch]);
464 } else {
465 if (!ch->auto_init)
466 omap_dma_disable_channel(s, ch);
467 else if (ch->repeat || ch->end_prog)
468 omap_dma_channel_load(ch);
469 else {
470 ch->waiting_end_prog = 1;
827df9f3 471 omap_dma_deactivate_channel(s, ch);
afbb5194 472 }
827df9f3 473 }
afbb5194
AZ		 474
475 if (ch->interrupts & END_BLOCK_INTR)
476 ch->status |= END_BLOCK_INTR;
827df9f3 477 }
afbb5194
AZ		 478 }
479 } while (status == ch->status && ch->active);
827df9f3 480
afbb5194
AZ		 481 omap_dma_interrupts_update(s);
482#endif
483}
b4e3104b 484
afbb5194
AZ		 485enum {
486 omap_dma_intr_element_sync,
487 omap_dma_intr_last_frame,
488 omap_dma_intr_half_frame,
489 omap_dma_intr_frame,
490 omap_dma_intr_frame_sync,
491 omap_dma_intr_packet,
492 omap_dma_intr_packet_sync,
493 omap_dma_intr_block,
494 __omap_dma_intr_last,
495};
b4e3104b 496
afbb5194
AZ		 497static void omap_dma_transfer_setup(struct soc_dma_ch_s *dma)
498{
499 struct omap_dma_port_if_s *src_p, *dest_p;
500 struct omap_dma_reg_set_s *a;
501 struct omap_dma_channel_s *ch = dma->opaque;
502 struct omap_dma_s *s = dma->dma->opaque;
503 int frames, min_elems, elements[__omap_dma_intr_last];
b4e3104b 504
afbb5194 505 a = &ch->active_set;
b4e3104b 506
afbb5194
AZ		 507 src_p = &s->mpu->port[ch->port[0]];
508 dest_p = &s->mpu->port[ch->port[1]];
509 if ((!ch->constant_fill && !src_p->addr_valid(s->mpu, a->src)) ||
510 (!dest_p->addr_valid(s->mpu, a->dest))) {
511#if 0
512 /* Bus time-out */
513 if (ch->interrupts & TIMEOUT_INTR)
514 ch->status |= TIMEOUT_INTR;
515 omap_dma_deactivate_channel(s, ch);
516 continue;
517#endif
518 printf("%s: Bus time-out in DMA%i operation\n",
519 __FUNCTION__, dma->num);
520 }
b4e3104b 521
afbb5194
AZ		 522 min_elems = INT_MAX;
523
524 /* Check all the conditions that terminate the transfer starting
525 * with those that can occur the soonest. */
526#define INTR_CHECK(cond, id, nelements) \
527 if (cond) { \
528 elements[id] = nelements; \
529 if (elements[id] < min_elems) \
530 min_elems = elements[id]; \
531 } else \
532 elements[id] = INT_MAX;
533
534 /* Elements */
535 INTR_CHECK(
536 ch->sync && !ch->fs && !ch->bs,
537 omap_dma_intr_element_sync,
538 1)
539
540 /* Frames */
541 /* TODO: for transfers where entire frames can be read and written
542 * using memcpy() but a->frame_delta is non-zero, try to still do
543 * transfers using soc_dma but limit min_elems to a->elements - ...
544 * See also the TODO in omap_dma_channel_load. */
545 INTR_CHECK(
546 (ch->interrupts & LAST_FRAME_INTR) &&
547 ((a->frame < a->frames - 1) || !a->element),
548 omap_dma_intr_last_frame,
549 (a->frames - a->frame - 2) * a->elements +
550 (a->elements - a->element + 1))
551 INTR_CHECK(
552 ch->interrupts & HALF_FRAME_INTR,
553 omap_dma_intr_half_frame,
554 (a->elements >> 1) +
555 (a->element >= (a->elements >> 1) ? a->elements : 0) -
556 a->element)
557 INTR_CHECK(
558 ch->sync && ch->fs && (ch->interrupts & END_FRAME_INTR),
559 omap_dma_intr_frame,
560 a->elements - a->element)
561 INTR_CHECK(
562 ch->sync && ch->fs && !ch->bs,
563 omap_dma_intr_frame_sync,
564 a->elements - a->element)
565
566 /* Packets */
567 INTR_CHECK(
568 ch->fs && ch->bs &&
569 (ch->interrupts & END_PKT_INTR) && !ch->src_sync,
570 omap_dma_intr_packet,
571 a->pck_elements - a->pck_element)
572 INTR_CHECK(
573 ch->fs && ch->bs && ch->sync,
574 omap_dma_intr_packet_sync,
575 a->pck_elements - a->pck_element)
576
577 /* Blocks */
578 INTR_CHECK(
579 1,
580 omap_dma_intr_block,
581 (a->frames - a->frame - 1) * a->elements +
582 (a->elements - a->element))
583
584 dma->bytes = min_elems * ch->data_type;
585
586 /* Set appropriate interrupts and/or deactivate channels */
587
588#ifdef MULTI_REQ
589 /* TODO: should all of this only be done if dma->update, and otherwise
590 * inside omap_dma_transfer_generic below - check what's faster. */
317b7e67 591 if (dma->update) {
afbb5194 592#endif
b4e3104b 593
317b7e67
MT		 594 /* If the channel is element synchronized, deactivate it */
595 if (min_elems == elements[omap_dma_intr_element_sync])
596 omap_dma_deactivate_channel(s, ch);
afbb5194 597
317b7e67
MT		 598 /* If it is the last frame, set the LAST_FRAME interrupt */
599 if (min_elems == elements[omap_dma_intr_last_frame])
600 ch->status |= LAST_FRAME_INTR;
afbb5194 601
317b7e67
MT		 602 /* If exactly half of the frame was reached, set the HALF_FRAME
603 interrupt */
604 if (min_elems == elements[omap_dma_intr_half_frame])
605 ch->status |= HALF_FRAME_INTR;
afbb5194 606
317b7e67
MT		 607 /* If a full packet has been transferred, set the END_PKT interrupt */
608 if (min_elems == elements[omap_dma_intr_packet])
609 ch->status |= END_PKT_INTR;
afbb5194 610
317b7e67
MT		 611 /* If the channel is packet-synchronized, deactivate it */
612 if (min_elems == elements[omap_dma_intr_packet_sync])
613 omap_dma_deactivate_channel(s, ch);
afbb5194 614
317b7e67
MT		 615 /* If the channel is frame synchronized, deactivate it */
616 if (min_elems == elements[omap_dma_intr_frame_sync])
617 omap_dma_deactivate_channel(s, ch);
afbb5194 618
317b7e67
MT		 619 /* Set the END_FRAME interrupt */
620 if (min_elems == elements[omap_dma_intr_frame])
621 ch->status |= END_FRAME_INTR;
afbb5194 622
317b7e67
MT		 623 if (min_elems == elements[omap_dma_intr_block]) {
624 /* End of Block */
625 /* Disable the channel */
afbb5194 626
317b7e67 627 if (ch->omap_3_1_compatible_disable) {
afbb5194 628 omap_dma_disable_channel(s, ch);
317b7e67
MT		 629 if (ch->link_enabled)
630 omap_dma_enable_channel(s, &s->ch[ch->link_next_ch]);
631 } else {
632 if (!ch->auto_init)
633 omap_dma_disable_channel(s, ch);
634 else if (ch->repeat || ch->end_prog)
635 omap_dma_channel_load(ch);
636 else {
637 ch->waiting_end_prog = 1;
638 omap_dma_deactivate_channel(s, ch);
639 }
b4e3104b 640 }
afbb5194 641
317b7e67
MT		 642 if (ch->interrupts & END_BLOCK_INTR)
643 ch->status |= END_BLOCK_INTR;
644 }
afbb5194 645
317b7e67
MT		 646 /* Update packet number */
647 if (ch->fs && ch->bs) {
648 a->pck_element += min_elems;
649 a->pck_element %= a->pck_elements;
650 }
afbb5194 651
317b7e67
MT		 652 /* TODO: check if we really need to update anything here or perhaps we
653 * can skip part of this. */
afbb5194 654#ifndef MULTI_REQ
317b7e67 655 if (dma->update) {
afbb5194 656#endif
317b7e67 657 a->element += min_elems;
afbb5194 658
317b7e67
MT		 659 frames = a->element / a->elements;
660 a->element = a->element % a->elements;
661 a->frame += frames;
662 a->src += min_elems * a->elem_delta[0] + frames * a->frame_delta[0];
663 a->dest += min_elems * a->elem_delta[1] + frames * a->frame_delta[1];
afbb5194 664
317b7e67
MT		 665 /* If the channel is async, update cpc */
666 if (!ch->sync && frames)
667 ch->cpc = a->dest & 0xffff;
d4066479 668
317b7e67
MT		 669 /* TODO: if the destination port is IMIF or EMIFF, set the dirty
670 * bits on it. */
f90554ad 671#ifndef MULTI_REQ
317b7e67
MT		 672 }
673#else
b4e3104b 674 }
f90554ad 675#endif
b4e3104b
AZ		 676
677 omap_dma_interrupts_update(s);
b4e3104b
AZ		 678}
679
afbb5194 680void omap_dma_reset(struct soc_dma_s *dma)
b4e3104b
AZ		 681{
682 int i;
afbb5194 683 struct omap_dma_s *s = dma->opaque;
b4e3104b 684
afbb5194 685 soc_dma_reset(s->dma);
827df9f3
AZ		 686 if (s->model < omap_dma_4)
687 s->gcr = 0x0004;
688 else
689 s->gcr = 0x00010010;
690 s->ocp = 0x00000000;
691 memset(&s->irqstat, 0, sizeof(s->irqstat));
692 memset(&s->irqen, 0, sizeof(s->irqen));
b4e3104b
AZ		 693 s->lcd_ch.src = emiff;
694 s->lcd_ch.condition = 0;
695 s->lcd_ch.interrupts = 0;
696 s->lcd_ch.dual = 0;
827df9f3
AZ		 697 if (s->model < omap_dma_4)
698 omap_dma_enable_3_1_mapping(s);
b4e3104b 699 for (i = 0; i < s->chans; i ++) {
827df9f3
AZ		 700 s->ch[i].suspend = 0;
701 s->ch[i].prefetch = 0;
702 s->ch[i].buf_disable = 0;
703 s->ch[i].src_sync = 0;
b4e3104b
AZ		 704 memset(&s->ch[i].burst, 0, sizeof(s->ch[i].burst));
705 memset(&s->ch[i].port, 0, sizeof(s->ch[i].port));
706 memset(&s->ch[i].mode, 0, sizeof(s->ch[i].mode));
b4e3104b
AZ		 707 memset(&s->ch[i].frame_index, 0, sizeof(s->ch[i].frame_index));
708 memset(&s->ch[i].element_index, 0, sizeof(s->ch[i].element_index));
827df9f3
AZ		 709 memset(&s->ch[i].endian, 0, sizeof(s->ch[i].endian));
710 memset(&s->ch[i].endian_lock, 0, sizeof(s->ch[i].endian_lock));
711 memset(&s->ch[i].translate, 0, sizeof(s->ch[i].translate));
712 s->ch[i].write_mode = 0;
713 s->ch[i].data_type = 0;
714 s->ch[i].transparent_copy = 0;
715 s->ch[i].constant_fill = 0;
716 s->ch[i].color = 0x00000000;
717 s->ch[i].end_prog = 0;
718 s->ch[i].repeat = 0;
719 s->ch[i].auto_init = 0;
720 s->ch[i].link_enabled = 0;
721 if (s->model < omap_dma_4)
722 s->ch[i].interrupts = 0x0003;
723 else
724 s->ch[i].interrupts = 0x0000;
725 s->ch[i].status = 0;
726 s->ch[i].cstatus = 0;
727 s->ch[i].active = 0;
728 s->ch[i].enable = 0;
729 s->ch[i].sync = 0;
730 s->ch[i].pending_request = 0;
731 s->ch[i].waiting_end_prog = 0;
732 s->ch[i].cpc = 0x0000;
733 s->ch[i].fs = 0;
734 s->ch[i].bs = 0;
735 s->ch[i].omap_3_1_compatible_disable = 0;
b4e3104b 736 memset(&s->ch[i].active_set, 0, sizeof(s->ch[i].active_set));
827df9f3
AZ		 737 s->ch[i].priority = 0;
738 s->ch[i].interleave_disabled = 0;
739 s->ch[i].type = 0;
b4e3104b
AZ		 740 }
741}
742
743static int omap_dma_ch_reg_read(struct omap_dma_s *s,
744 struct omap_dma_channel_s *ch, int reg, uint16_t *value)
745{
746 switch (reg) {
747 case 0x00: /* SYS_DMA_CSDP_CH0 */
748 *value = (ch->burst[1] << 14) |
749 (ch->pack[1] << 13) |
750 (ch->port[1] << 9) |
751 (ch->burst[0] << 7) |
752 (ch->pack[0] << 6) |
753 (ch->port[0] << 2) |
754 (ch->data_type >> 1);
755 break;
756
757 case 0x02: /* SYS_DMA_CCR_CH0 */
827df9f3 758 if (s->model <= omap_dma_3_1)
b4e3104b
AZ		 759 *value = 0 << 10; /* FIFO_FLUSH reads as 0 */
760 else
761 *value = ch->omap_3_1_compatible_disable << 10;
762 *value |= (ch->mode[1] << 14) |
763 (ch->mode[0] << 12) |
764 (ch->end_prog << 11) |
765 (ch->repeat << 9) |
766 (ch->auto_init << 8) |
767 (ch->enable << 7) |
768 (ch->priority << 6) |
769 (ch->fs << 5) | ch->sync;
770 break;
771
772 case 0x04: /* SYS_DMA_CICR_CH0 */
773 *value = ch->interrupts;
774 break;
775
776 case 0x06: /* SYS_DMA_CSR_CH0 */
777 *value = ch->status;
778 ch->status &= SYNC;
779 if (!ch->omap_3_1_compatible_disable && ch->sibling) {
780 *value |= (ch->sibling->status & 0x3f) << 6;
781 ch->sibling->status &= SYNC;
782 }
783 qemu_irq_lower(ch->irq);
784 break;
785
786 case 0x08: /* SYS_DMA_CSSA_L_CH0 */
787 *value = ch->addr[0] & 0x0000ffff;
788 break;
789
790 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
791 *value = ch->addr[0] >> 16;
792 break;
793
794 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
795 *value = ch->addr[1] & 0x0000ffff;
796 break;
797
798 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
799 *value = ch->addr[1] >> 16;
800 break;
801
802 case 0x10: /* SYS_DMA_CEN_CH0 */
803 *value = ch->elements;
804 break;
805
806 case 0x12: /* SYS_DMA_CFN_CH0 */
807 *value = ch->frames;
808 break;
809
810 case 0x14: /* SYS_DMA_CFI_CH0 */
811 *value = ch->frame_index[0];
812 break;
813
814 case 0x16: /* SYS_DMA_CEI_CH0 */
815 *value = ch->element_index[0];
816 break;
817
818 case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
819 if (ch->omap_3_1_compatible_disable)
820 *value = ch->active_set.src & 0xffff; /* CSAC */
821 else
822 *value = ch->cpc;
823 break;
824
825 case 0x1a: /* DMA_CDAC */
826 *value = ch->active_set.dest & 0xffff; /* CDAC */
827 break;
828
829 case 0x1c: /* DMA_CDEI */
830 *value = ch->element_index[1];
831 break;
832
833 case 0x1e: /* DMA_CDFI */
834 *value = ch->frame_index[1];
835 break;
836
837 case 0x20: /* DMA_COLOR_L */
838 *value = ch->color & 0xffff;
839 break;
840
841 case 0x22: /* DMA_COLOR_U */
842 *value = ch->color >> 16;
843 break;
844
845 case 0x24: /* DMA_CCR2 */
846 *value = (ch->bs << 2) |
847 (ch->transparent_copy << 1) |
848 ch->constant_fill;
849 break;
850
851 case 0x28: /* DMA_CLNK_CTRL */
852 *value = (ch->link_enabled << 15) |
853 (ch->link_next_ch & 0xf);
854 break;
855
856 case 0x2a: /* DMA_LCH_CTRL */
857 *value = (ch->interleave_disabled << 15) |
858 ch->type;
859 break;
860
861 default:
862 return 1;
863 }
864 return 0;
865}
866
867static int omap_dma_ch_reg_write(struct omap_dma_s *s,
868 struct omap_dma_channel_s *ch, int reg, uint16_t value)
869{
870 switch (reg) {
871 case 0x00: /* SYS_DMA_CSDP_CH0 */
872 ch->burst[1] = (value & 0xc000) >> 14;
873 ch->pack[1] = (value & 0x2000) >> 13;
874 ch->port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9);
875 ch->burst[0] = (value & 0x0180) >> 7;
876 ch->pack[0] = (value & 0x0040) >> 6;
877 ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2);
827df9f3
AZ		 878 ch->data_type = 1 << (value & 3);
879 if (ch->port[0] >= __omap_dma_port_last)
b4e3104b
AZ		 880 printf("%s: invalid DMA port %i\n", __FUNCTION__,
881 ch->port[0]);
827df9f3 882 if (ch->port[1] >= __omap_dma_port_last)
b4e3104b
AZ		 883 printf("%s: invalid DMA port %i\n", __FUNCTION__,
884 ch->port[1]);
885 if ((value & 3) == 3)
886 printf("%s: bad data_type for DMA channel\n", __FUNCTION__);
887 break;
888
889 case 0x02: /* SYS_DMA_CCR_CH0 */
c227f099
AL		 890 ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
891 ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
b4e3104b 892 ch->end_prog = (value & 0x0800) >> 11;
827df9f3 893 if (s->model >= omap_dma_3_2)
b4e3104b
AZ		 894 ch->omap_3_1_compatible_disable = (value >> 10) & 0x1;
895 ch->repeat = (value & 0x0200) >> 9;
896 ch->auto_init = (value & 0x0100) >> 8;
897 ch->priority = (value & 0x0040) >> 6;
898 ch->fs = (value & 0x0020) >> 5;
899 ch->sync = value & 0x001f;
900
901 if (value & 0x0080)
902 omap_dma_enable_channel(s, ch);
903 else
904 omap_dma_disable_channel(s, ch);
905
906 if (ch->end_prog)
907 omap_dma_channel_end_prog(s, ch);
908
909 break;
910
911 case 0x04: /* SYS_DMA_CICR_CH0 */
827df9f3 912 ch->interrupts = value & 0x3f;
b4e3104b
AZ		 913 break;
914
915 case 0x06: /* SYS_DMA_CSR_CH0 */
c227f099 916 OMAP_RO_REG((target_phys_addr_t) reg);
b4e3104b
AZ		 917 break;
918
919 case 0x08: /* SYS_DMA_CSSA_L_CH0 */
920 ch->addr[0] &= 0xffff0000;
921 ch->addr[0] |= value;
922 break;
923
924 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
925 ch->addr[0] &= 0x0000ffff;
926 ch->addr[0] |= (uint32_t) value << 16;
927 break;
928
929 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
930 ch->addr[1] &= 0xffff0000;
931 ch->addr[1] |= value;
932 break;
933
934 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
935 ch->addr[1] &= 0x0000ffff;
936 ch->addr[1] |= (uint32_t) value << 16;
937 break;
938
939 case 0x10: /* SYS_DMA_CEN_CH0 */
940 ch->elements = value;
941 break;
942
943 case 0x12: /* SYS_DMA_CFN_CH0 */
944 ch->frames = value;
945 break;
946
947 case 0x14: /* SYS_DMA_CFI_CH0 */
948 ch->frame_index[0] = (int16_t) value;
949 break;
950
951 case 0x16: /* SYS_DMA_CEI_CH0 */
952 ch->element_index[0] = (int16_t) value;
953 break;
954
955 case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
c227f099 956 OMAP_RO_REG((target_phys_addr_t) reg);
b4e3104b
AZ		 957 break;
958
959 case 0x1c: /* DMA_CDEI */
960 ch->element_index[1] = (int16_t) value;
961 break;
962
963 case 0x1e: /* DMA_CDFI */
964 ch->frame_index[1] = (int16_t) value;
965 break;
966
967 case 0x20: /* DMA_COLOR_L */
968 ch->color &= 0xffff0000;
969 ch->color |= value;
970 break;
971
972 case 0x22: /* DMA_COLOR_U */
973 ch->color &= 0xffff;
974 ch->color |= value << 16;
975 break;
976
977 case 0x24: /* DMA_CCR2 */
827df9f3 978 ch->bs = (value >> 2) & 0x1;
b4e3104b
AZ		 979 ch->transparent_copy = (value >> 1) & 0x1;
980 ch->constant_fill = value & 0x1;
981 break;
982
983 case 0x28: /* DMA_CLNK_CTRL */
984 ch->link_enabled = (value >> 15) & 0x1;
985 if (value & (1 << 14)) { /* Stop_Lnk */
986 ch->link_enabled = 0;
987 omap_dma_disable_channel(s, ch);
988 }
989 ch->link_next_ch = value & 0x1f;
990 break;
991
992 case 0x2a: /* DMA_LCH_CTRL */
993 ch->interleave_disabled = (value >> 15) & 0x1;
994 ch->type = value & 0xf;
995 break;
996
997 default:
998 return 1;
999 }
1000 return 0;
1001}
1002
1003static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
1004 uint16_t value)
1005{
1006 switch (offset) {
1007 case 0xbc0: /* DMA_LCD_CSDP */
1008 s->brust_f2 = (value >> 14) & 0x3;
1009 s->pack_f2 = (value >> 13) & 0x1;
1010 s->data_type_f2 = (1 << ((value >> 11) & 0x3));
1011 s->brust_f1 = (value >> 7) & 0x3;
1012 s->pack_f1 = (value >> 6) & 0x1;
1013 s->data_type_f1 = (1 << ((value >> 0) & 0x3));
1014 break;
1015
1016 case 0xbc2: /* DMA_LCD_CCR */
1017 s->mode_f2 = (value >> 14) & 0x3;
1018 s->mode_f1 = (value >> 12) & 0x3;
1019 s->end_prog = (value >> 11) & 0x1;
1020 s->omap_3_1_compatible_disable = (value >> 10) & 0x1;
1021 s->repeat = (value >> 9) & 0x1;
1022 s->auto_init = (value >> 8) & 0x1;
1023 s->running = (value >> 7) & 0x1;
1024 s->priority = (value >> 6) & 0x1;
1025 s->bs = (value >> 4) & 0x1;
1026 break;
1027
1028 case 0xbc4: /* DMA_LCD_CTRL */
1029 s->dst = (value >> 8) & 0x1;
1030 s->src = ((value >> 6) & 0x3) << 1;
1031 s->condition = 0;
1032 /* Assume no bus errors and thus no BUS_ERROR irq bits. */
1033 s->interrupts = (value >> 1) & 1;
1034 s->dual = value & 1;
1035 break;
1036
1037 case 0xbc8: /* TOP_B1_L */
1038 s->src_f1_top &= 0xffff0000;
1039 s->src_f1_top |= 0x0000ffff & value;
1040 break;
1041
1042 case 0xbca: /* TOP_B1_U */
1043 s->src_f1_top &= 0x0000ffff;
1044 s->src_f1_top |= value << 16;
1045 break;
1046
1047 case 0xbcc: /* BOT_B1_L */
1048 s->src_f1_bottom &= 0xffff0000;
1049 s->src_f1_bottom |= 0x0000ffff & value;
1050 break;
1051
1052 case 0xbce: /* BOT_B1_U */
1053 s->src_f1_bottom &= 0x0000ffff;
1054 s->src_f1_bottom |= (uint32_t) value << 16;
1055 break;
1056
1057 case 0xbd0: /* TOP_B2_L */
1058 s->src_f2_top &= 0xffff0000;
1059 s->src_f2_top |= 0x0000ffff & value;
1060 break;
1061
1062 case 0xbd2: /* TOP_B2_U */
1063 s->src_f2_top &= 0x0000ffff;
1064 s->src_f2_top |= (uint32_t) value << 16;
1065 break;
1066
1067 case 0xbd4: /* BOT_B2_L */
1068 s->src_f2_bottom &= 0xffff0000;
1069 s->src_f2_bottom |= 0x0000ffff & value;
1070 break;
1071
1072 case 0xbd6: /* BOT_B2_U */
1073 s->src_f2_bottom &= 0x0000ffff;
1074 s->src_f2_bottom |= (uint32_t) value << 16;
1075 break;
1076
1077 case 0xbd8: /* DMA_LCD_SRC_EI_B1 */
1078 s->element_index_f1 = value;
1079 break;
1080
1081 case 0xbda: /* DMA_LCD_SRC_FI_B1_L */
1082 s->frame_index_f1 &= 0xffff0000;
1083 s->frame_index_f1 |= 0x0000ffff & value;
1084 break;
1085
1086 case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */
1087 s->frame_index_f1 &= 0x0000ffff;
1088 s->frame_index_f1 |= (uint32_t) value << 16;
1089 break;
1090
1091 case 0xbdc: /* DMA_LCD_SRC_EI_B2 */
1092 s->element_index_f2 = value;
1093 break;
1094
1095 case 0xbde: /* DMA_LCD_SRC_FI_B2_L */
1096 s->frame_index_f2 &= 0xffff0000;
1097 s->frame_index_f2 |= 0x0000ffff & value;
1098 break;
1099
1100 case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */
1101 s->frame_index_f2 &= 0x0000ffff;
1102 s->frame_index_f2 |= (uint32_t) value << 16;
1103 break;
1104
1105 case 0xbe0: /* DMA_LCD_SRC_EN_B1 */
1106 s->elements_f1 = value;
1107 break;
1108
1109 case 0xbe4: /* DMA_LCD_SRC_FN_B1 */
1110 s->frames_f1 = value;
1111 break;
1112
1113 case 0xbe2: /* DMA_LCD_SRC_EN_B2 */
1114 s->elements_f2 = value;
1115 break;
1116
1117 case 0xbe6: /* DMA_LCD_SRC_FN_B2 */
1118 s->frames_f2 = value;
1119 break;
1120
1121 case 0xbea: /* DMA_LCD_LCH_CTRL */
1122 s->lch_type = value & 0xf;
1123 break;
1124
1125 default:
1126 return 1;
1127 }
1128 return 0;
1129}
1130
1131static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
1132 uint16_t *ret)
1133{
1134 switch (offset) {
1135 case 0xbc0: /* DMA_LCD_CSDP */
1136 *ret = (s->brust_f2 << 14) |
1137 (s->pack_f2 << 13) |
1138 ((s->data_type_f2 >> 1) << 11) |
1139 (s->brust_f1 << 7) |
1140 (s->pack_f1 << 6) |
1141 ((s->data_type_f1 >> 1) << 0);
1142 break;
1143
1144 case 0xbc2: /* DMA_LCD_CCR */
1145 *ret = (s->mode_f2 << 14) |
1146 (s->mode_f1 << 12) |
1147 (s->end_prog << 11) |
1148 (s->omap_3_1_compatible_disable << 10) |
1149 (s->repeat << 9) |
1150 (s->auto_init << 8) |
1151 (s->running << 7) |
1152 (s->priority << 6) |
1153 (s->bs << 4);
1154 break;
1155
1156 case 0xbc4: /* DMA_LCD_CTRL */
1157 qemu_irq_lower(s->irq);
1158 *ret = (s->dst << 8) |
1159 ((s->src & 0x6) << 5) |
1160 (s->condition << 3) |
1161 (s->interrupts << 1) |
1162 s->dual;
1163 break;
1164
1165 case 0xbc8: /* TOP_B1_L */
1166 *ret = s->src_f1_top & 0xffff;
1167 break;
1168
1169 case 0xbca: /* TOP_B1_U */
1170 *ret = s->src_f1_top >> 16;
1171 break;
1172
1173 case 0xbcc: /* BOT_B1_L */
1174 *ret = s->src_f1_bottom & 0xffff;
1175 break;
1176
1177 case 0xbce: /* BOT_B1_U */
1178 *ret = s->src_f1_bottom >> 16;
1179 break;
1180
1181 case 0xbd0: /* TOP_B2_L */
1182 *ret = s->src_f2_top & 0xffff;
1183 break;
1184
1185 case 0xbd2: /* TOP_B2_U */
1186 *ret = s->src_f2_top >> 16;
1187 break;
1188
1189 case 0xbd4: /* BOT_B2_L */
1190 *ret = s->src_f2_bottom & 0xffff;
1191 break;
1192
1193 case 0xbd6: /* BOT_B2_U */
1194 *ret = s->src_f2_bottom >> 16;
1195 break;
1196
1197 case 0xbd8: /* DMA_LCD_SRC_EI_B1 */
1198 *ret = s->element_index_f1;
1199 break;
1200
1201 case 0xbda: /* DMA_LCD_SRC_FI_B1_L */
1202 *ret = s->frame_index_f1 & 0xffff;
1203 break;
1204
1205 case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */
1206 *ret = s->frame_index_f1 >> 16;
1207 break;
1208
1209 case 0xbdc: /* DMA_LCD_SRC_EI_B2 */
1210 *ret = s->element_index_f2;
1211 break;
1212
1213 case 0xbde: /* DMA_LCD_SRC_FI_B2_L */
1214 *ret = s->frame_index_f2 & 0xffff;
1215 break;
1216
1217 case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */
1218 *ret = s->frame_index_f2 >> 16;
1219 break;
1220
1221 case 0xbe0: /* DMA_LCD_SRC_EN_B1 */
1222 *ret = s->elements_f1;
1223 break;
1224
1225 case 0xbe4: /* DMA_LCD_SRC_FN_B1 */
1226 *ret = s->frames_f1;
1227 break;
1228
1229 case 0xbe2: /* DMA_LCD_SRC_EN_B2 */
1230 *ret = s->elements_f2;
1231 break;
1232
1233 case 0xbe6: /* DMA_LCD_SRC_FN_B2 */
1234 *ret = s->frames_f2;
1235 break;
1236
1237 case 0xbea: /* DMA_LCD_LCH_CTRL */
1238 *ret = s->lch_type;
1239 break;
1240
1241 default:
1242 return 1;
1243 }
1244 return 0;
1245}
1246
1247static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
1248 uint16_t value)
1249{
1250 switch (offset) {
1251 case 0x300: /* SYS_DMA_LCD_CTRL */
1252 s->src = (value & 0x40) ? imif : emiff;
1253 s->condition = 0;
1254 /* Assume no bus errors and thus no BUS_ERROR irq bits. */
1255 s->interrupts = (value >> 1) & 1;
1256 s->dual = value & 1;
1257 break;
1258
1259 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
1260 s->src_f1_top &= 0xffff0000;
1261 s->src_f1_top |= 0x0000ffff & value;
1262 break;
1263
1264 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
1265 s->src_f1_top &= 0x0000ffff;
1266 s->src_f1_top |= value << 16;
1267 break;
1268
1269 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
1270 s->src_f1_bottom &= 0xffff0000;
1271 s->src_f1_bottom |= 0x0000ffff & value;
1272 break;
1273
1274 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
1275 s->src_f1_bottom &= 0x0000ffff;
1276 s->src_f1_bottom |= value << 16;
1277 break;
1278
1279 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
1280 s->src_f2_top &= 0xffff0000;
1281 s->src_f2_top |= 0x0000ffff & value;
1282 break;
1283
1284 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
1285 s->src_f2_top &= 0x0000ffff;
1286 s->src_f2_top |= value << 16;
1287 break;
1288
1289 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
1290 s->src_f2_bottom &= 0xffff0000;
1291 s->src_f2_bottom |= 0x0000ffff & value;
1292 break;
1293
1294 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
1295 s->src_f2_bottom &= 0x0000ffff;
1296 s->src_f2_bottom |= value << 16;
1297 break;
1298
1299 default:
1300 return 1;
1301 }
1302 return 0;
1303}
1304
1305static int omap_dma_3_1_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
1306 uint16_t *ret)
1307{
1308 int i;
1309
1310 switch (offset) {
1311 case 0x300: /* SYS_DMA_LCD_CTRL */
1312 i = s->condition;
1313 s->condition = 0;
1314 qemu_irq_lower(s->irq);
1315 *ret = ((s->src == imif) << 6) | (i << 3) |
1316 (s->interrupts << 1) | s->dual;
1317 break;
1318
1319 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
1320 *ret = s->src_f1_top & 0xffff;
1321 break;
1322
1323 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
1324 *ret = s->src_f1_top >> 16;
1325 break;
1326
1327 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
1328 *ret = s->src_f1_bottom & 0xffff;
1329 break;
1330
1331 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
1332 *ret = s->src_f1_bottom >> 16;
1333 break;
1334
1335 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
1336 *ret = s->src_f2_top & 0xffff;
1337 break;
1338
1339 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
1340 *ret = s->src_f2_top >> 16;
1341 break;
1342
1343 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
1344 *ret = s->src_f2_bottom & 0xffff;
1345 break;
1346
1347 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
1348 *ret = s->src_f2_bottom >> 16;
1349 break;
1350
1351 default:
1352 return 1;
1353 }
1354 return 0;
1355}
1356
1357static int omap_dma_sys_write(struct omap_dma_s *s, int offset, uint16_t value)
1358{
1359 switch (offset) {
1360 case 0x400: /* SYS_DMA_GCR */
1361 s->gcr = value;
1362 break;
1363
1364 case 0x404: /* DMA_GSCR */
1365 if (value & 0x8)
1366 omap_dma_disable_3_1_mapping(s);
1367 else
1368 omap_dma_enable_3_1_mapping(s);
1369 break;
1370
1371 case 0x408: /* DMA_GRST */
1372 if (value & 0x1)
afbb5194 1373 omap_dma_reset(s->dma);
b4e3104b
AZ		 1374 break;
1375
1376 default:
1377 return 1;
1378 }
1379 return 0;
1380}
1381
1382static int omap_dma_sys_read(struct omap_dma_s *s, int offset,
1383 uint16_t *ret)
1384{
1385 switch (offset) {
1386 case 0x400: /* SYS_DMA_GCR */
1387 *ret = s->gcr;
1388 break;
1389
1390 case 0x404: /* DMA_GSCR */
1391 *ret = s->omap_3_1_mapping_disabled << 3;
1392 break;
1393
1394 case 0x408: /* DMA_GRST */
1395 *ret = 0;
1396 break;
1397
1398 case 0x442: /* DMA_HW_ID */
1399 case 0x444: /* DMA_PCh2_ID */
1400 case 0x446: /* DMA_PCh0_ID */
1401 case 0x448: /* DMA_PCh1_ID */
1402 case 0x44a: /* DMA_PChG_ID */
1403 case 0x44c: /* DMA_PChD_ID */
1404 *ret = 1;
1405 break;
1406
1407 case 0x44e: /* DMA_CAPS_0_U */
827df9f3 1408 *ret = (s->caps[0] >> 16) & 0xffff;
b4e3104b 1409 break;
b4e3104b 1410 case 0x450: /* DMA_CAPS_0_L */
827df9f3 1411 *ret = (s->caps[0] >> 0) & 0xffff;
b4e3104b
AZ		 1412 break;
1413
827df9f3
AZ		 1414 case 0x452: /* DMA_CAPS_1_U */
1415 *ret = (s->caps[1] >> 16) & 0xffff;
1416 break;
b4e3104b 1417 case 0x454: /* DMA_CAPS_1_L */
827df9f3 1418 *ret = (s->caps[1] >> 0) & 0xffff;
b4e3104b
AZ		 1419 break;
1420
1421 case 0x456: /* DMA_CAPS_2 */
827df9f3 1422 *ret = s->caps[2];
b4e3104b
AZ		 1423 break;
1424
1425 case 0x458: /* DMA_CAPS_3 */
827df9f3 1426 *ret = s->caps[3];
b4e3104b
AZ		 1427 break;
1428
1429 case 0x45a: /* DMA_CAPS_4 */
827df9f3 1430 *ret = s->caps[4];
b4e3104b
AZ		 1431 break;
1432
1433 case 0x460: /* DMA_PCh2_SR */
1434 case 0x480: /* DMA_PCh0_SR */
1435 case 0x482: /* DMA_PCh1_SR */
1436 case 0x4c0: /* DMA_PChD_SR_0 */
1437 printf("%s: Physical Channel Status Registers not implemented.\n",
1438 __FUNCTION__);
1439 *ret = 0xff;
1440 break;
1441
1442 default:
1443 return 1;
1444 }
1445 return 0;
1446}
1447
c227f099 1448static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr)
b4e3104b
AZ		 1449{
1450 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
8da3ff18 1451 int reg, ch;
b4e3104b
AZ		 1452 uint16_t ret;
1453
8da3ff18 1454 switch (addr) {
b4e3104b 1455 case 0x300 ... 0x3fe:
827df9f3 1456 if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
8da3ff18 1457 if (omap_dma_3_1_lcd_read(&s->lcd_ch, addr, &ret))
b4e3104b
AZ		 1458 break;
1459 return ret;
1460 }
1461 /* Fall through. */
1462 case 0x000 ... 0x2fe:
8da3ff18
PB		 1463 reg = addr & 0x3f;
1464 ch = (addr >> 6) & 0x0f;
b4e3104b
AZ		 1465 if (omap_dma_ch_reg_read(s, &s->ch[ch], reg, &ret))
1466 break;
1467 return ret;
1468
1469 case 0x404 ... 0x4fe:
827df9f3 1470 if (s->model <= omap_dma_3_1)
b4e3104b
AZ		 1471 break;
1472 /* Fall through. */
1473 case 0x400:
8da3ff18 1474 if (omap_dma_sys_read(s, addr, &ret))
b4e3104b
AZ		 1475 break;
1476 return ret;
1477
1478 case 0xb00 ... 0xbfe:
1479 if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
8da3ff18 1480 if (omap_dma_3_2_lcd_read(&s->lcd_ch, addr, &ret))
b4e3104b
AZ		 1481 break;
1482 return ret;
1483 }
1484 break;
1485 }
1486
1487 OMAP_BAD_REG(addr);
1488 return 0;
1489}
1490
c227f099 1491static void omap_dma_write(void *opaque, target_phys_addr_t addr,
b4e3104b
AZ		 1492 uint32_t value)
1493{
1494 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
8da3ff18 1495 int reg, ch;
b4e3104b 1496
8da3ff18 1497 switch (addr) {
b4e3104b 1498 case 0x300 ... 0x3fe:
827df9f3 1499 if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
8da3ff18 1500 if (omap_dma_3_1_lcd_write(&s->lcd_ch, addr, value))
b4e3104b
AZ		 1501 break;
1502 return;
1503 }
1504 /* Fall through. */
1505 case 0x000 ... 0x2fe:
8da3ff18
PB		 1506 reg = addr & 0x3f;
1507 ch = (addr >> 6) & 0x0f;
b4e3104b
AZ		 1508 if (omap_dma_ch_reg_write(s, &s->ch[ch], reg, value))
1509 break;
1510 return;
1511
1512 case 0x404 ... 0x4fe:
827df9f3 1513 if (s->model <= omap_dma_3_1)
b4e3104b
AZ		 1514 break;
1515 case 0x400:
1516 /* Fall through. */
8da3ff18 1517 if (omap_dma_sys_write(s, addr, value))
b4e3104b
AZ		 1518 break;
1519 return;
1520
1521 case 0xb00 ... 0xbfe:
1522 if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
8da3ff18 1523 if (omap_dma_3_2_lcd_write(&s->lcd_ch, addr, value))
b4e3104b
AZ		 1524 break;
1525 return;
1526 }
1527 break;
1528 }
1529
1530 OMAP_BAD_REG(addr);
1531}
1532
d60efc6b 1533static CPUReadMemoryFunc * const omap_dma_readfn[] = {
b4e3104b
AZ		 1534 omap_badwidth_read16,
1535 omap_dma_read,
1536 omap_badwidth_read16,
1537};
1538
d60efc6b 1539static CPUWriteMemoryFunc * const omap_dma_writefn[] = {
b4e3104b
AZ		 1540 omap_badwidth_write16,
1541 omap_dma_write,
1542 omap_badwidth_write16,
1543};
1544
1545static void omap_dma_request(void *opaque, int drq, int req)
1546{
1547 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
827df9f3 1548 /* The request pins are level triggered in QEMU. */
b4e3104b 1549 if (req) {
afbb5194
AZ		 1550 if (~s->dma->drqbmp & (1 << drq)) {
1551 s->dma->drqbmp |= 1 << drq;
b4e3104b
AZ		 1552 omap_dma_process_request(s, drq);
1553 }
1554 } else
afbb5194 1555 s->dma->drqbmp &= ~(1 << drq);
b4e3104b
AZ		 1556}
1557
afbb5194 1558/* XXX: this won't be needed once soc_dma knows about clocks. */
b4e3104b
AZ		 1559static void omap_dma_clk_update(void *opaque, int line, int on)
1560{
1561 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
afbb5194 1562 int i;
b4e3104b 1563
afbb5194
AZ		 1564 s->dma->freq = omap_clk_getrate(s->clk);
1565
1566 for (i = 0; i < s->chans; i ++)
1567 if (s->ch[i].active)
1568 soc_dma_set_request(s->ch[i].dma, on);
b4e3104b
AZ		 1569}
1570
827df9f3
AZ		 1571static void omap_dma_setcaps(struct omap_dma_s *s)
1572{
1573 switch (s->model) {
1574 default:
1575 case omap_dma_3_1:
1576 break;
1577 case omap_dma_3_2:
1578 case omap_dma_4:
1579 /* XXX Only available for sDMA */
1580 s->caps[0] =
1581 (1 << 19) | /* Constant Fill Capability */
1582 (1 << 18); /* Transparent BLT Capability */
1583 s->caps[1] =
1584 (1 << 1); /* 1-bit palettized capability (DMA 3.2 only) */
1585 s->caps[2] =
1586 (1 << 8) | /* SEPARATE_SRC_AND_DST_INDEX_CPBLTY */
1587 (1 << 7) | /* DST_DOUBLE_INDEX_ADRS_CPBLTY */
1588 (1 << 6) | /* DST_SINGLE_INDEX_ADRS_CPBLTY */
1589 (1 << 5) | /* DST_POST_INCRMNT_ADRS_CPBLTY */
1590 (1 << 4) | /* DST_CONST_ADRS_CPBLTY */
1591 (1 << 3) | /* SRC_DOUBLE_INDEX_ADRS_CPBLTY */
1592 (1 << 2) | /* SRC_SINGLE_INDEX_ADRS_CPBLTY */
1593 (1 << 1) | /* SRC_POST_INCRMNT_ADRS_CPBLTY */
1594 (1 << 0); /* SRC_CONST_ADRS_CPBLTY */
1595 s->caps[3] =
1596 (1 << 6) | /* BLOCK_SYNCHR_CPBLTY (DMA 4 only) */
1597 (1 << 7) | /* PKT_SYNCHR_CPBLTY (DMA 4 only) */
1598 (1 << 5) | /* CHANNEL_CHAINING_CPBLTY */
1599 (1 << 4) | /* LCh_INTERLEAVE_CPBLTY */
1600 (1 << 3) | /* AUTOINIT_REPEAT_CPBLTY (DMA 3.2 only) */
1601 (1 << 2) | /* AUTOINIT_ENDPROG_CPBLTY (DMA 3.2 only) */
1602 (1 << 1) | /* FRAME_SYNCHR_CPBLTY */
1603 (1 << 0); /* ELMNT_SYNCHR_CPBLTY */
1604 s->caps[4] =
1605 (1 << 7) | /* PKT_INTERRUPT_CPBLTY (DMA 4 only) */
1606 (1 << 6) | /* SYNC_STATUS_CPBLTY */
1607 (1 << 5) | /* BLOCK_INTERRUPT_CPBLTY */
1608 (1 << 4) | /* LAST_FRAME_INTERRUPT_CPBLTY */
1609 (1 << 3) | /* FRAME_INTERRUPT_CPBLTY */
1610 (1 << 2) | /* HALF_FRAME_INTERRUPT_CPBLTY */
1611 (1 << 1) | /* EVENT_DROP_INTERRUPT_CPBLTY */
1612 (1 << 0); /* TIMEOUT_INTERRUPT_CPBLTY (DMA 3.2 only) */
1613 break;
1614 }
1615}
1616
c227f099 1617struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
b4e3104b
AZ		 1618 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
1619 enum omap_dma_model model)
1620{
1621 int iomemtype, num_irqs, memsize, i;
1622 struct omap_dma_s *s = (struct omap_dma_s *)
1623 qemu_mallocz(sizeof(struct omap_dma_s));
1624
827df9f3 1625 if (model <= omap_dma_3_1) {
b4e3104b
AZ		 1626 num_irqs = 6;
1627 memsize = 0x800;
1628 } else {
1629 num_irqs = 16;
1630 memsize = 0xc00;
1631 }
b4e3104b
AZ		 1632 s->model = model;
1633 s->mpu = mpu;
1634 s->clk = clk;
1635 s->lcd_ch.irq = lcd_irq;
1636 s->lcd_ch.mpu = mpu;
afbb5194
AZ		 1637
1638 s->dma = soc_dma_init((model <= omap_dma_3_1) ? 9 : 16);
1639 s->dma->freq = omap_clk_getrate(clk);
1640 s->dma->transfer_fn = omap_dma_transfer_generic;
1641 s->dma->setup_fn = omap_dma_transfer_setup;
1642 s->dma->drq = qemu_allocate_irqs(omap_dma_request, s, 32);
1643 s->dma->opaque = s;
1644
b4e3104b
AZ		 1645 while (num_irqs --)
1646 s->ch[num_irqs].irq = irqs[num_irqs];
1647 for (i = 0; i < 3; i ++) {
1648 s->ch[i].sibling = &s->ch[i + 6];
1649 s->ch[i + 6].sibling = &s->ch[i];
1650 }
afbb5194
AZ		 1651 for (i = (model <= omap_dma_3_1) ? 8 : 15; i >= 0; i --) {
1652 s->ch[i].dma = &s->dma->ch[i];
1653 s->dma->ch[i].opaque = &s->ch[i];
1654 }
1655
1656 omap_dma_setcaps(s);
b4e3104b 1657 omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]);
afbb5194 1658 omap_dma_reset(s->dma);
b4e3104b
AZ		 1659 omap_dma_clk_update(s, 0, 1);
1660
1eed09cb 1661 iomemtype = cpu_register_io_memory(omap_dma_readfn,
b4e3104b 1662 omap_dma_writefn, s);
8da3ff18 1663 cpu_register_physical_memory(base, memsize, iomemtype);
b4e3104b 1664
afbb5194
AZ		 1665 mpu->drq = s->dma->drq;
1666
1667 return s->dma;
b4e3104b
AZ		 1668}
1669
827df9f3
AZ		 1670static void omap_dma_interrupts_4_update(struct omap_dma_s *s)
1671{
1672 struct omap_dma_channel_s *ch = s->ch;
1673 uint32_t bmp, bit;
1674
1675 for (bmp = 0, bit = 1; bit; ch ++, bit <<= 1)
1676 if (ch->status) {
1677 bmp |= bit;
1678 ch->cstatus |= ch->status;
1679 ch->status = 0;
1680 }
1681 if ((s->irqstat[0] |= s->irqen[0] & bmp))
1682 qemu_irq_raise(s->irq[0]);
1683 if ((s->irqstat[1] |= s->irqen[1] & bmp))
1684 qemu_irq_raise(s->irq[1]);
1685 if ((s->irqstat[2] |= s->irqen[2] & bmp))
1686 qemu_irq_raise(s->irq[2]);
1687 if ((s->irqstat[3] |= s->irqen[3] & bmp))
1688 qemu_irq_raise(s->irq[3]);
1689}
1690
c227f099 1691static uint32_t omap_dma4_read(void *opaque, target_phys_addr_t addr)
827df9f3
AZ		 1692{
1693 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
8da3ff18 1694 int irqn = 0, chnum;
827df9f3
AZ		 1695 struct omap_dma_channel_s *ch;
1696
8da3ff18 1697 switch (addr) {
827df9f3
AZ		 1698 case 0x00: /* DMA4_REVISION */
1699 return 0x40;
1700
1701 case 0x14: /* DMA4_IRQSTATUS_L3 */
1702 irqn ++;
1703 case 0x10: /* DMA4_IRQSTATUS_L2 */
1704 irqn ++;
1705 case 0x0c: /* DMA4_IRQSTATUS_L1 */
1706 irqn ++;
1707 case 0x08: /* DMA4_IRQSTATUS_L0 */
1708 return s->irqstat[irqn];
1709
1710 case 0x24: /* DMA4_IRQENABLE_L3 */
1711 irqn ++;
1712 case 0x20: /* DMA4_IRQENABLE_L2 */
1713 irqn ++;
1714 case 0x1c: /* DMA4_IRQENABLE_L1 */
1715 irqn ++;
1716 case 0x18: /* DMA4_IRQENABLE_L0 */
1717 return s->irqen[irqn];
1718
1719 case 0x28: /* DMA4_SYSSTATUS */
1720 return 1; /* RESETDONE */
1721
1722 case 0x2c: /* DMA4_OCP_SYSCONFIG */
1723 return s->ocp;
1724
1725 case 0x64: /* DMA4_CAPS_0 */
1726 return s->caps[0];
1727 case 0x6c: /* DMA4_CAPS_2 */
1728 return s->caps[2];
1729 case 0x70: /* DMA4_CAPS_3 */
1730 return s->caps[3];
1731 case 0x74: /* DMA4_CAPS_4 */
1732 return s->caps[4];
1733
1734 case 0x78: /* DMA4_GCR */
1735 return s->gcr;
1736
1737 case 0x80 ... 0xfff:
8da3ff18
PB		 1738 addr -= 0x80;
1739 chnum = addr / 0x60;
827df9f3 1740 ch = s->ch + chnum;
8da3ff18 1741 addr -= chnum * 0x60;
827df9f3
AZ		 1742 break;
1743
1744 default:
1745 OMAP_BAD_REG(addr);
1746 return 0;
1747 }
1748
1749 /* Per-channel registers */
8da3ff18 1750 switch (addr) {
827df9f3
AZ		 1751 case 0x00: /* DMA4_CCR */
1752 return (ch->buf_disable << 25) |
1753 (ch->src_sync << 24) |
1754 (ch->prefetch << 23) |
1755 ((ch->sync & 0x60) << 14) |
1756 (ch->bs << 18) |
1757 (ch->transparent_copy << 17) |
1758 (ch->constant_fill << 16) |
1759 (ch->mode[1] << 14) |
1760 (ch->mode[0] << 12) |
1761 (0 << 10) | (0 << 9) |
1762 (ch->suspend << 8) |
1763 (ch->enable << 7) |
1764 (ch->priority << 6) |
1765 (ch->fs << 5) | (ch->sync & 0x1f);
1766
1767 case 0x04: /* DMA4_CLNK_CTRL */
1768 return (ch->link_enabled << 15) | ch->link_next_ch;
1769
1770 case 0x08: /* DMA4_CICR */
1771 return ch->interrupts;
1772
1773 case 0x0c: /* DMA4_CSR */
1774 return ch->cstatus;
1775
1776 case 0x10: /* DMA4_CSDP */
1777 return (ch->endian[0] << 21) |
1778 (ch->endian_lock[0] << 20) |
1779 (ch->endian[1] << 19) |
1780 (ch->endian_lock[1] << 18) |
1781 (ch->write_mode << 16) |
1782 (ch->burst[1] << 14) |
1783 (ch->pack[1] << 13) |
1784 (ch->translate[1] << 9) |
1785 (ch->burst[0] << 7) |
1786 (ch->pack[0] << 6) |
1787 (ch->translate[0] << 2) |
1788 (ch->data_type >> 1);
1789
1790 case 0x14: /* DMA4_CEN */
1791 return ch->elements;
1792
1793 case 0x18: /* DMA4_CFN */
1794 return ch->frames;
1795
1796 case 0x1c: /* DMA4_CSSA */
1797 return ch->addr[0];
1798
1799 case 0x20: /* DMA4_CDSA */
1800 return ch->addr[1];
1801
1802 case 0x24: /* DMA4_CSEI */
1803 return ch->element_index[0];
1804
1805 case 0x28: /* DMA4_CSFI */
1806 return ch->frame_index[0];
1807
1808 case 0x2c: /* DMA4_CDEI */
1809 return ch->element_index[1];
1810
1811 case 0x30: /* DMA4_CDFI */
1812 return ch->frame_index[1];
1813
1814 case 0x34: /* DMA4_CSAC */
1815 return ch->active_set.src & 0xffff;
1816
1817 case 0x38: /* DMA4_CDAC */
1818 return ch->active_set.dest & 0xffff;
1819
1820 case 0x3c: /* DMA4_CCEN */
1821 return ch->active_set.element;
1822
1823 case 0x40: /* DMA4_CCFN */
1824 return ch->active_set.frame;
1825
1826 case 0x44: /* DMA4_COLOR */
1827 /* XXX only in sDMA */
1828 return ch->color;
1829
1830 default:
1831 OMAP_BAD_REG(addr);
1832 return 0;
1833 }
1834}
1835
c227f099 1836static void omap_dma4_write(void *opaque, target_phys_addr_t addr,
827df9f3
AZ		 1837 uint32_t value)
1838{
1839 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
8da3ff18 1840 int chnum, irqn = 0;
827df9f3
AZ		 1841 struct omap_dma_channel_s *ch;
1842
8da3ff18 1843 switch (addr) {
827df9f3
AZ		 1844 case 0x14: /* DMA4_IRQSTATUS_L3 */
1845 irqn ++;
1846 case 0x10: /* DMA4_IRQSTATUS_L2 */
1847 irqn ++;
1848 case 0x0c: /* DMA4_IRQSTATUS_L1 */
1849 irqn ++;
1850 case 0x08: /* DMA4_IRQSTATUS_L0 */
1851 s->irqstat[irqn] &= ~value;
1852 if (!s->irqstat[irqn])
1853 qemu_irq_lower(s->irq[irqn]);
1854 return;
1855
1856 case 0x24: /* DMA4_IRQENABLE_L3 */
1857 irqn ++;
1858 case 0x20: /* DMA4_IRQENABLE_L2 */
1859 irqn ++;
1860 case 0x1c: /* DMA4_IRQENABLE_L1 */
1861 irqn ++;
1862 case 0x18: /* DMA4_IRQENABLE_L0 */
1863 s->irqen[irqn] = value;
1864 return;
1865
1866 case 0x2c: /* DMA4_OCP_SYSCONFIG */
1867 if (value & 2) /* SOFTRESET */
afbb5194 1868 omap_dma_reset(s->dma);
827df9f3
AZ		 1869 s->ocp = value & 0x3321;
1870 if (((s->ocp >> 12) & 3) == 3) /* MIDLEMODE */
1871 fprintf(stderr, "%s: invalid DMA power mode\n", __FUNCTION__);
1872 return;
1873
1874 case 0x78: /* DMA4_GCR */
1875 s->gcr = value & 0x00ff00ff;
1876 if ((value & 0xff) == 0x00) /* MAX_CHANNEL_FIFO_DEPTH */
1877 fprintf(stderr, "%s: wrong FIFO depth in GCR\n", __FUNCTION__);
1878 return;
1879
1880 case 0x80 ... 0xfff:
8da3ff18
PB		 1881 addr -= 0x80;
1882 chnum = addr / 0x60;
827df9f3 1883 ch = s->ch + chnum;
8da3ff18 1884 addr -= chnum * 0x60;
827df9f3
AZ		 1885 break;
1886
1887 case 0x00: /* DMA4_REVISION */
1888 case 0x28: /* DMA4_SYSSTATUS */
1889 case 0x64: /* DMA4_CAPS_0 */
1890 case 0x6c: /* DMA4_CAPS_2 */
1891 case 0x70: /* DMA4_CAPS_3 */
1892 case 0x74: /* DMA4_CAPS_4 */
1893 OMAP_RO_REG(addr);
1894 return;
1895
1896 default:
1897 OMAP_BAD_REG(addr);
1898 return;
1899 }
1900
1901 /* Per-channel registers */
8da3ff18 1902 switch (addr) {
827df9f3
AZ		 1903 case 0x00: /* DMA4_CCR */
1904 ch->buf_disable = (value >> 25) & 1;
1905 ch->src_sync = (value >> 24) & 1; /* XXX For CamDMA must be 1 */
1906 if (ch->buf_disable && !ch->src_sync)
1907 fprintf(stderr, "%s: Buffering disable is not allowed in "
1908 "destination synchronised mode\n", __FUNCTION__);
1909 ch->prefetch = (value >> 23) & 1;
1910 ch->bs = (value >> 18) & 1;
1911 ch->transparent_copy = (value >> 17) & 1;
1912 ch->constant_fill = (value >> 16) & 1;
c227f099
AL		 1913 ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
1914 ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
827df9f3
AZ		 1915 ch->suspend = (value & 0x0100) >> 8;
1916 ch->priority = (value & 0x0040) >> 6;
1917 ch->fs = (value & 0x0020) >> 5;
1918 if (ch->fs && ch->bs && ch->mode[0] && ch->mode[1])
1919 fprintf(stderr, "%s: For a packet transfer at least one port "
1920 "must be constant-addressed\n", __FUNCTION__);
1921 ch->sync = (value & 0x001f) | ((value >> 14) & 0x0060);
1922 /* XXX must be 0x01 for CamDMA */
1923
1924 if (value & 0x0080)
1925 omap_dma_enable_channel(s, ch);
1926 else
1927 omap_dma_disable_channel(s, ch);
1928
1929 break;
1930
1931 case 0x04: /* DMA4_CLNK_CTRL */
1932 ch->link_enabled = (value >> 15) & 0x1;
1933 ch->link_next_ch = value & 0x1f;
1934 break;
1935
1936 case 0x08: /* DMA4_CICR */
1937 ch->interrupts = value & 0x09be;
1938 break;
1939
1940 case 0x0c: /* DMA4_CSR */
1941 ch->cstatus &= ~value;
1942 break;
1943
1944 case 0x10: /* DMA4_CSDP */
1945 ch->endian[0] =(value >> 21) & 1;
1946 ch->endian_lock[0] =(value >> 20) & 1;
1947 ch->endian[1] =(value >> 19) & 1;
1948 ch->endian_lock[1] =(value >> 18) & 1;
1949 if (ch->endian[0] != ch->endian[1])
afbb5194 1950 fprintf(stderr, "%s: DMA endiannes conversion enable attempt\n",
827df9f3
AZ		 1951 __FUNCTION__);
1952 ch->write_mode = (value >> 16) & 3;
1953 ch->burst[1] = (value & 0xc000) >> 14;
1954 ch->pack[1] = (value & 0x2000) >> 13;
1955 ch->translate[1] = (value & 0x1e00) >> 9;
1956 ch->burst[0] = (value & 0x0180) >> 7;
1957 ch->pack[0] = (value & 0x0040) >> 6;
1958 ch->translate[0] = (value & 0x003c) >> 2;
1959 if (ch->translate[0] | ch->translate[1])
1960 fprintf(stderr, "%s: bad MReqAddressTranslate sideband signal\n",
1961 __FUNCTION__);
1962 ch->data_type = 1 << (value & 3);
1963 if ((value & 3) == 3)
1964 printf("%s: bad data_type for DMA channel\n", __FUNCTION__);
1965 break;
1966
1967 case 0x14: /* DMA4_CEN */
afbb5194 1968 ch->set_update = 1;
827df9f3
AZ		 1969 ch->elements = value & 0xffffff;
1970 break;
1971
1972 case 0x18: /* DMA4_CFN */
1973 ch->frames = value & 0xffff;
afbb5194 1974 ch->set_update = 1;
827df9f3
AZ		 1975 break;
1976
1977 case 0x1c: /* DMA4_CSSA */
c227f099 1978 ch->addr[0] = (target_phys_addr_t) (uint32_t) value;
afbb5194 1979 ch->set_update = 1;
827df9f3
AZ		 1980 break;
1981
1982 case 0x20: /* DMA4_CDSA */
c227f099 1983 ch->addr[1] = (target_phys_addr_t) (uint32_t) value;
afbb5194 1984 ch->set_update = 1;
827df9f3
AZ		 1985 break;
1986
1987 case 0x24: /* DMA4_CSEI */
1988 ch->element_index[0] = (int16_t) value;
afbb5194 1989 ch->set_update = 1;
827df9f3
AZ		 1990 break;
1991
1992 case 0x28: /* DMA4_CSFI */
1993 ch->frame_index[0] = (int32_t) value;
afbb5194 1994 ch->set_update = 1;
827df9f3
AZ		 1995 break;
1996
1997 case 0x2c: /* DMA4_CDEI */
1998 ch->element_index[1] = (int16_t) value;
afbb5194 1999 ch->set_update = 1;
827df9f3
AZ		 2000 break;
2001
2002 case 0x30: /* DMA4_CDFI */
2003 ch->frame_index[1] = (int32_t) value;
afbb5194 2004 ch->set_update = 1;
827df9f3
AZ		 2005 break;
2006
2007 case 0x44: /* DMA4_COLOR */
2008 /* XXX only in sDMA */
2009 ch->color = value;
2010 break;
2011
2012 case 0x34: /* DMA4_CSAC */
2013 case 0x38: /* DMA4_CDAC */
2014 case 0x3c: /* DMA4_CCEN */
2015 case 0x40: /* DMA4_CCFN */
2016 OMAP_RO_REG(addr);
2017 break;
2018
2019 default:
2020 OMAP_BAD_REG(addr);
2021 }
2022}
2023
d60efc6b 2024static CPUReadMemoryFunc * const omap_dma4_readfn[] = {
827df9f3
AZ		 2025 omap_badwidth_read16,
2026 omap_dma4_read,
2027 omap_dma4_read,
2028};
2029
d60efc6b 2030static CPUWriteMemoryFunc * const omap_dma4_writefn[] = {
827df9f3
AZ		 2031 omap_badwidth_write16,
2032 omap_dma4_write,
2033 omap_dma4_write,
2034};
2035
c227f099 2036struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
827df9f3
AZ		 2037 struct omap_mpu_state_s *mpu, int fifo,
2038 int chans, omap_clk iclk, omap_clk fclk)
2039{
afbb5194 2040 int iomemtype, i;
827df9f3
AZ		 2041 struct omap_dma_s *s = (struct omap_dma_s *)
2042 qemu_mallocz(sizeof(struct omap_dma_s));
2043
827df9f3
AZ		 2044 s->model = omap_dma_4;
2045 s->chans = chans;
2046 s->mpu = mpu;
2047 s->clk = fclk;
afbb5194
AZ		 2048
2049 s->dma = soc_dma_init(s->chans);
2050 s->dma->freq = omap_clk_getrate(fclk);
2051 s->dma->transfer_fn = omap_dma_transfer_generic;
2052 s->dma->setup_fn = omap_dma_transfer_setup;
2053 s->dma->drq = qemu_allocate_irqs(omap_dma_request, s, 64);
2054 s->dma->opaque = s;
2055 for (i = 0; i < s->chans; i ++) {
2056 s->ch[i].dma = &s->dma->ch[i];
2057 s->dma->ch[i].opaque = &s->ch[i];
2058 }
2059
827df9f3
AZ		 2060 memcpy(&s->irq, irqs, sizeof(s->irq));
2061 s->intr_update = omap_dma_interrupts_4_update;
afbb5194 2062
827df9f3 2063 omap_dma_setcaps(s);
827df9f3 2064 omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]);
afbb5194
AZ		 2065 omap_dma_reset(s->dma);
2066 omap_dma_clk_update(s, 0, !!s->dma->freq);
827df9f3 2067
1eed09cb 2068 iomemtype = cpu_register_io_memory(omap_dma4_readfn,
827df9f3 2069 omap_dma4_writefn, s);
8da3ff18 2070 cpu_register_physical_memory(base, 0x1000, iomemtype);
827df9f3 2071
afbb5194
AZ		 2072 mpu->drq = s->dma->drq;
2073
2074 return s->dma;
827df9f3
AZ		 2075}
2076
afbb5194 2077struct omap_dma_lcd_channel_s *omap_dma_get_lcdch(struct soc_dma_s *dma)
b4e3104b 2078{
afbb5194
AZ		 2079 struct omap_dma_s *s = dma->opaque;
2080
b4e3104b
AZ		 2081 return &s->lcd_ch;
2082}
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