[qemu.git] / hw / grlib_irqmp.c

/*
 * QEMU GRLIB IRQMP Emulator
 *
 * (Multiprocessor and extended interrupt not supported)
 *
 * Copyright (c) 2010-2011 AdaCore
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "sysbus.h"
#include "cpu.h"

#include "grlib.h"

#include "trace.h"

#define IRQMP_MAX_CPU 16
#define IRQMP_REG_SIZE 256      /* Size of memory mapped registers */

/* Memory mapped register offsets */
#define LEVEL_OFFSET     0x00
#define PENDING_OFFSET   0x04
#define FORCE0_OFFSET    0x08
#define CLEAR_OFFSET     0x0C
#define MP_STATUS_OFFSET 0x10
#define BROADCAST_OFFSET 0x14
#define MASK_OFFSET      0x40
#define FORCE_OFFSET     0x80
#define EXTENDED_OFFSET  0xC0

typedef struct IRQMPState IRQMPState;

typedef struct IRQMP {
    SysBusDevice busdev;
    MemoryRegion iomem;

    void *set_pil_in;
    void *set_pil_in_opaque;

    IRQMPState *state;
} IRQMP;

struct IRQMPState {
    uint32_t level;
    uint32_t pending;
    uint32_t clear;
    uint32_t broadcast;

    uint32_t mask[IRQMP_MAX_CPU];
    uint32_t force[IRQMP_MAX_CPU];
    uint32_t extended[IRQMP_MAX_CPU];

    IRQMP    *parent;
};

static void grlib_irqmp_check_irqs(IRQMPState *state)
{
    uint32_t      pend   = 0;
    uint32_t      level0 = 0;
    uint32_t      level1 = 0;
    set_pil_in_fn set_pil_in;

    assert(state != NULL);
    assert(state->parent != NULL);

    /* IRQ for CPU 0 (no SMP support) */
    pend = (state->pending | state->force[0])
        & state->mask[0];

    level0 = pend & ~state->level;
    level1 = pend &  state->level;

    trace_grlib_irqmp_check_irqs(state->pending, state->force[0],
                                 state->mask[0], level1, level0);

    set_pil_in = (set_pil_in_fn)state->parent->set_pil_in;

    /* Trigger level1 interrupt first and level0 if there is no level1 */
    if (level1 != 0) {
        set_pil_in(state->parent->set_pil_in_opaque, level1);
    } else {
        set_pil_in(state->parent->set_pil_in_opaque, level0);
    }
}

void grlib_irqmp_ack(DeviceState *dev, int intno)
{
    SysBusDevice *sdev;
    IRQMP        *irqmp;
    IRQMPState   *state;
    uint32_t      mask;

    assert(dev != NULL);

    sdev = sysbus_from_qdev(dev);
    assert(sdev != NULL);

    irqmp = FROM_SYSBUS(typeof(*irqmp), sdev);
    assert(irqmp != NULL);

    state = irqmp->state;
    assert(state != NULL);

    intno &= 15;
    mask = 1 << intno;

    trace_grlib_irqmp_ack(intno);

    /* Clear registers */
    state->pending  &= ~mask;
    state->force[0] &= ~mask; /* Only CPU 0 (No SMP support) */

    grlib_irqmp_check_irqs(state);
}

void grlib_irqmp_set_irq(void *opaque, int irq, int level)
{
    IRQMP      *irqmp;
    IRQMPState *s;
    int         i = 0;

    assert(opaque != NULL);

    irqmp = FROM_SYSBUS(typeof(*irqmp), sysbus_from_qdev(opaque));
    assert(irqmp != NULL);

    s = irqmp->state;
    assert(s         != NULL);
    assert(s->parent != NULL);


    if (level) {
        trace_grlib_irqmp_set_irq(irq);

        if (s->broadcast & 1 << irq) {
            /* Broadcasted IRQ */
            for (i = 0; i < IRQMP_MAX_CPU; i++) {
                s->force[i] |= 1 << irq;
            }
        } else {
            s->pending |= 1 << irq;
        }
        grlib_irqmp_check_irqs(s);

    }
}

static uint64_t grlib_irqmp_read(void *opaque, target_phys_addr_t addr,
                                 unsigned size)
{
    IRQMP      *irqmp = opaque;
    IRQMPState *state;

    assert(irqmp != NULL);
    state = irqmp->state;
    assert(state != NULL);

    addr &= 0xff;

    /* global registers */
    switch (addr) {
    case LEVEL_OFFSET:
        return state->level;

    case PENDING_OFFSET:
        return state->pending;

    case FORCE0_OFFSET:
        /* This register is an "alias" for the force register of CPU 0 */
        return state->force[0];

    case CLEAR_OFFSET:
    case MP_STATUS_OFFSET:
        /* Always read as 0 */
        return 0;

    case BROADCAST_OFFSET:
        return state->broadcast;

    default:
        break;
    }

    /* mask registers */
    if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) {
        int cpu = (addr - MASK_OFFSET) / 4;
        assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);

        return state->mask[cpu];
    }

    /* force registers */
    if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) {
        int cpu = (addr - FORCE_OFFSET) / 4;
        assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);

        return state->force[cpu];
    }

    /* extended (not supported) */
    if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) {
        int cpu = (addr - EXTENDED_OFFSET) / 4;
        assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);

        return state->extended[cpu];
    }

    trace_grlib_irqmp_readl_unknown(addr);
    return 0;
}

static void grlib_irqmp_write(void *opaque, target_phys_addr_t addr,
                              uint64_t value, unsigned size)
{
    IRQMP      *irqmp = opaque;
    IRQMPState *state;

    assert(irqmp != NULL);
    state = irqmp->state;
    assert(state != NULL);

    addr &= 0xff;

    /* global registers */
    switch (addr) {
    case LEVEL_OFFSET:
        value &= 0xFFFF << 1; /* clean up the value */
        state->level = value;
        return;

    case PENDING_OFFSET:
        /* Read Only */
        return;

    case FORCE0_OFFSET:
        /* This register is an "alias" for the force register of CPU 0 */

        value &= 0xFFFE; /* clean up the value */
        state->force[0] = value;
        grlib_irqmp_check_irqs(irqmp->state);
        return;

    case CLEAR_OFFSET:
        value &= ~1; /* clean up the value */
        state->pending &= ~value;
        return;

    case MP_STATUS_OFFSET:
        /* Read Only (no SMP support) */
        return;

    case BROADCAST_OFFSET:
        value &= 0xFFFE; /* clean up the value */
        state->broadcast = value;
        return;

    default:
        break;
    }

    /* mask registers */
    if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) {
        int cpu = (addr - MASK_OFFSET) / 4;
        assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);

        value &= ~1; /* clean up the value */
        state->mask[cpu] = value;
        grlib_irqmp_check_irqs(irqmp->state);
        return;
    }

    /* force registers */
    if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) {
        int cpu = (addr - FORCE_OFFSET) / 4;
        assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);

        uint32_t force = value & 0xFFFE;
        uint32_t clear = (value >> 16) & 0xFFFE;
        uint32_t old   = state->force[cpu];

        state->force[cpu] = (old | force) & ~clear;
        grlib_irqmp_check_irqs(irqmp->state);
        return;
    }

    /* extended (not supported) */
    if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) {
        int cpu = (addr - EXTENDED_OFFSET) / 4;
        assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);

        value &= 0xF; /* clean up the value */
        state->extended[cpu] = value;
        return;
    }

    trace_grlib_irqmp_writel_unknown(addr, value);
}

static const MemoryRegionOps grlib_irqmp_ops = {
    .read = grlib_irqmp_read,
    .write = grlib_irqmp_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

static void grlib_irqmp_reset(DeviceState *d)
{
    IRQMP *irqmp = container_of(d, IRQMP, busdev.qdev);
    assert(irqmp        != NULL);
    assert(irqmp->state != NULL);

    memset(irqmp->state, 0, sizeof *irqmp->state);
    irqmp->state->parent = irqmp;
}

static int grlib_irqmp_init(SysBusDevice *dev)
{
    IRQMP *irqmp = FROM_SYSBUS(typeof(*irqmp), dev);

    assert(irqmp != NULL);

    /* Check parameters */
    if (irqmp->set_pil_in == NULL) {
        return -1;
    }

    memory_region_init_io(&irqmp->iomem, &grlib_irqmp_ops, irqmp,
                          "irqmp", IRQMP_REG_SIZE);

    irqmp->state = g_malloc0(sizeof *irqmp->state);

    sysbus_init_mmio(dev, &irqmp->iomem);

    return 0;
}

static Property grlib_irqmp_properties[] = {
    DEFINE_PROP_PTR("set_pil_in", IRQMP, set_pil_in),
    DEFINE_PROP_PTR("set_pil_in_opaque", IRQMP, set_pil_in_opaque),
    DEFINE_PROP_END_OF_LIST(),
};

static void grlib_irqmp_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = grlib_irqmp_init;
    dc->reset = grlib_irqmp_reset;
    dc->props = grlib_irqmp_properties;
}

static TypeInfo grlib_irqmp_info = {
    .name          = "grlib,irqmp",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(IRQMP),
    .class_init    = grlib_irqmp_class_init,
};

static void grlib_irqmp_register_types(void)
{
    type_register_static(&grlib_irqmp_info);
}

type_init(grlib_irqmp_register_types)
Commit	Line	Data
3f10bcbb FC	1	/*
	2	* QEMU GRLIB IRQMP Emulator
	3	*
	4	* (Multiprocessor and extended interrupt not supported)
	5	*
	6	* Copyright (c) 2010-2011 AdaCore
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	*/
	26
	27	#include "sysbus.h"
	28	#include "cpu.h"
	29
	30	#include "grlib.h"
	31
	32	#include "trace.h"
	33
	34	#define IRQMP_MAX_CPU 16
	35	#define IRQMP_REG_SIZE 256 /* Size of memory mapped registers */
	36
	37	/* Memory mapped register offsets */
	38	#define LEVEL_OFFSET 0x00
	39	#define PENDING_OFFSET 0x04
	40	#define FORCE0_OFFSET 0x08
	41	#define CLEAR_OFFSET 0x0C
	42	#define MP_STATUS_OFFSET 0x10
	43	#define BROADCAST_OFFSET 0x14
	44	#define MASK_OFFSET 0x40
	45	#define FORCE_OFFSET 0x80
	46	#define EXTENDED_OFFSET 0xC0
	47
	48	typedef struct IRQMPState IRQMPState;
	49
	50	typedef struct IRQMP {
	51	SysBusDevice busdev;
847b52c1	52	MemoryRegion iomem;
3f10bcbb FC	53
	54	void *set_pil_in;
	55	void *set_pil_in_opaque;
	56
	57	IRQMPState *state;
	58	} IRQMP;
	59
	60	struct IRQMPState {
	61	uint32_t level;
	62	uint32_t pending;
	63	uint32_t clear;
	64	uint32_t broadcast;
	65
	66	uint32_t mask[IRQMP_MAX_CPU];
	67	uint32_t force[IRQMP_MAX_CPU];
	68	uint32_t extended[IRQMP_MAX_CPU];
	69
	70	IRQMP *parent;
	71	};
	72
	73	static void grlib_irqmp_check_irqs(IRQMPState *state)
	74	{
	75	uint32_t pend = 0;
	76	uint32_t level0 = 0;
	77	uint32_t level1 = 0;
	78	set_pil_in_fn set_pil_in;
	79
	80	assert(state != NULL);
	81	assert(state->parent != NULL);
	82
	83	/* IRQ for CPU 0 (no SMP support) */
	84	pend = (state->pending \| state->force[0])
	85	& state->mask[0];
	86
	87	level0 = pend & ~state->level;
	88	level1 = pend & state->level;
	89
	90	trace_grlib_irqmp_check_irqs(state->pending, state->force[0],
	91	state->mask[0], level1, level0);
	92
	93	set_pil_in = (set_pil_in_fn)state->parent->set_pil_in;
	94
	95	/* Trigger level1 interrupt first and level0 if there is no level1 */
	96	if (level1 != 0) {
	97	set_pil_in(state->parent->set_pil_in_opaque, level1);
	98	} else {
	99	set_pil_in(state->parent->set_pil_in_opaque, level0);
	100	}
	101	}
	102
	103	void grlib_irqmp_ack(DeviceState *dev, int intno)
	104	{
	105	SysBusDevice *sdev;
	106	IRQMP *irqmp;
	107	IRQMPState *state;
	108	uint32_t mask;
	109
	110	assert(dev != NULL);
	111
	112	sdev = sysbus_from_qdev(dev);
	113	assert(sdev != NULL);
	114
	115	irqmp = FROM_SYSBUS(typeof(*irqmp), sdev);
	116	assert(irqmp != NULL);
117
118	state = irqmp->state;
119	assert(state != NULL);
120
121	intno &= 15;
122	mask = 1 << intno;
123
124	trace_grlib_irqmp_ack(intno);
125
126	/* Clear registers */
127	state->pending &= ~mask;
128	state->force[0] &= ~mask; /* Only CPU 0 (No SMP support) */
129
130	grlib_irqmp_check_irqs(state);
131	}
132
133	void grlib_irqmp_set_irq(void *opaque, int irq, int level)
134	{
135	IRQMP *irqmp;
136	IRQMPState *s;
137	int i = 0;
138
139	assert(opaque != NULL);
140
141	irqmp = FROM_SYSBUS(typeof(*irqmp), sysbus_from_qdev(opaque));
142	assert(irqmp != NULL);
143
144	s = irqmp->state;
145	assert(s != NULL);
146	assert(s->parent != NULL);
147
148
149	if (level) {
150	trace_grlib_irqmp_set_irq(irq);
151
152	if (s->broadcast & 1 << irq) {
153	/* Broadcasted IRQ */
154	for (i = 0; i < IRQMP_MAX_CPU; i++) {
155	s->force[i] \|= 1 << irq;
156	}
157	} else {
158	s->pending \|= 1 << irq;
159	}
160	grlib_irqmp_check_irqs(s);
161
162	}
163	}
164
847b52c1 AK	165	static uint64_t grlib_irqmp_read(void *opaque, target_phys_addr_t addr,
847b52c1 AK	166	unsigned size)
3f10bcbb FC	167	{
	168	IRQMP *irqmp = opaque;
	169	IRQMPState *state;
	170
	171	assert(irqmp != NULL);
	172	state = irqmp->state;
	173	assert(state != NULL);
	174
	175	addr &= 0xff;
	176
	177	/* global registers */
	178	switch (addr) {
	179	case LEVEL_OFFSET:
	180	return state->level;
	181
	182	case PENDING_OFFSET:
	183	return state->pending;
	184
	185	case FORCE0_OFFSET:
	186	/* This register is an "alias" for the force register of CPU 0 */
	187	return state->force[0];
	188
	189	case CLEAR_OFFSET:
	190	case MP_STATUS_OFFSET:
	191	/* Always read as 0 */
	192	return 0;
	193
	194	case BROADCAST_OFFSET:
	195	return state->broadcast;
	196
	197	default:
	198	break;
	199	}
	200
	201	/* mask registers */
	202	if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) {
	203	int cpu = (addr - MASK_OFFSET) / 4;
	204	assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
	205
	206	return state->mask[cpu];
	207	}
	208
	209	/* force registers */
	210	if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) {
	211	int cpu = (addr - FORCE_OFFSET) / 4;
	212	assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
	213
	214	return state->force[cpu];
	215	}
	216
	217	/* extended (not supported) */
	218	if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) {
	219	int cpu = (addr - EXTENDED_OFFSET) / 4;
	220	assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
	221
	222	return state->extended[cpu];
	223	}
	224
b4548fcc	225	trace_grlib_irqmp_readl_unknown(addr);
3f10bcbb FC	226	return 0;
	227	}
	228
847b52c1 AK	229	static void grlib_irqmp_write(void *opaque, target_phys_addr_t addr,
847b52c1 AK	230	uint64_t value, unsigned size)
3f10bcbb FC	231	{
	232	IRQMP *irqmp = opaque;
	233	IRQMPState *state;
	234
	235	assert(irqmp != NULL);
	236	state = irqmp->state;
	237	assert(state != NULL);
	238
	239	addr &= 0xff;
	240
	241	/* global registers */
	242	switch (addr) {
	243	case LEVEL_OFFSET:
	244	value &= 0xFFFF << 1; /* clean up the value */
	245	state->level = value;
	246	return;
	247
	248	case PENDING_OFFSET:
	249	/* Read Only */
	250	return;
	251
	252	case FORCE0_OFFSET:
	253	/* This register is an "alias" for the force register of CPU 0 */
	254
	255	value &= 0xFFFE; /* clean up the value */
	256	state->force[0] = value;
	257	grlib_irqmp_check_irqs(irqmp->state);
	258	return;
	259
	260	case CLEAR_OFFSET:
	261	value &= ~1; /* clean up the value */
	262	state->pending &= ~value;
	263	return;
	264
	265	case MP_STATUS_OFFSET:
	266	/* Read Only (no SMP support) */
	267	return;
	268
	269	case BROADCAST_OFFSET:
	270	value &= 0xFFFE; /* clean up the value */
	271	state->broadcast = value;
	272	return;
	273
	274	default:
	275	break;
	276	}
	277
	278	/* mask registers */
	279	if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) {
	280	int cpu = (addr - MASK_OFFSET) / 4;
	281	assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
	282
	283	value &= ~1; /* clean up the value */
	284	state->mask[cpu] = value;
	285	grlib_irqmp_check_irqs(irqmp->state);
	286	return;
	287	}
	288
	289	/* force registers */
	290	if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) {
	291	int cpu = (addr - FORCE_OFFSET) / 4;
	292	assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
	293
	294	uint32_t force = value & 0xFFFE;
295	uint32_t clear = (value >> 16) & 0xFFFE;
296	uint32_t old = state->force[cpu];
297
298	state->force[cpu] = (old \| force) & ~clear;
299	grlib_irqmp_check_irqs(irqmp->state);
300	return;
301	}
302
303	/* extended (not supported) */
304	if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) {
305	int cpu = (addr - EXTENDED_OFFSET) / 4;
306	assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
307
308	value &= 0xF; /* clean up the value */
309	state->extended[cpu] = value;
310	return;
311	}
312
b4548fcc	313	trace_grlib_irqmp_writel_unknown(addr, value);
3f10bcbb FC	314	}
3f10bcbb FC	315
847b52c1 AK	316	static const MemoryRegionOps grlib_irqmp_ops = {
	317	.read = grlib_irqmp_read,
	318	.write = grlib_irqmp_write,
	319	.endianness = DEVICE_NATIVE_ENDIAN,
	320	.valid = {
	321	.min_access_size = 4,
	322	.max_access_size = 4,
	323	},
3f10bcbb FC	324	};
	325
	326	static void grlib_irqmp_reset(DeviceState *d)
	327	{
	328	IRQMP *irqmp = container_of(d, IRQMP, busdev.qdev);
	329	assert(irqmp != NULL);
	330	assert(irqmp->state != NULL);
	331
	332	memset(irqmp->state, 0, sizeof *irqmp->state);
	333	irqmp->state->parent = irqmp;
	334	}
	335
	336	static int grlib_irqmp_init(SysBusDevice *dev)
	337	{
	338	IRQMP irqmp = FROM_SYSBUS(typeof(irqmp), dev);
3f10bcbb FC	339
	340	assert(irqmp != NULL);
	341
	342	/* Check parameters */
	343	if (irqmp->set_pil_in == NULL) {
	344	return -1;
	345	}
	346
847b52c1 AK	347	memory_region_init_io(&irqmp->iomem, &grlib_irqmp_ops, irqmp,
847b52c1 AK	348	"irqmp", IRQMP_REG_SIZE);
3f10bcbb	349
7267c094	350	irqmp->state = g_malloc0(sizeof *irqmp->state);
3f10bcbb	351
750ecd44	352	sysbus_init_mmio(dev, &irqmp->iomem);
3f10bcbb FC	353
	354	return 0;
	355	}
	356
999e12bb AL	357	static Property grlib_irqmp_properties[] = {
	358	DEFINE_PROP_PTR("set_pil_in", IRQMP, set_pil_in),
	359	DEFINE_PROP_PTR("set_pil_in_opaque", IRQMP, set_pil_in_opaque),
	360	DEFINE_PROP_END_OF_LIST(),
	361	};
	362
	363	static void grlib_irqmp_class_init(ObjectClass klass, void data)
	364	{
39bffca2	365	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	366	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	367
	368	k->init = grlib_irqmp_init;
39bffca2 AL	369	dc->reset = grlib_irqmp_reset;
39bffca2 AL	370	dc->props = grlib_irqmp_properties;
999e12bb AL	371	}
999e12bb AL	372
39bffca2 AL	373	static TypeInfo grlib_irqmp_info = {
	374	.name = "grlib,irqmp",
	375	.parent = TYPE_SYS_BUS_DEVICE,
	376	.instance_size = sizeof(IRQMP),
	377	.class_init = grlib_irqmp_class_init,
3f10bcbb FC	378	};
3f10bcbb FC	379
83f7d43a	380	static void grlib_irqmp_register_types(void)
3f10bcbb	381	{
39bffca2	382	type_register_static(&grlib_irqmp_info);
3f10bcbb FC	383	}
3f10bcbb FC	384
83f7d43a	385	type_init(grlib_irqmp_register_types)