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Merge remote-tracking branch 'remotes/kvm/uq/master' into staging
[qemu.git] / target-ppc / fpu_helper.c
CommitLineData
bd23cd45
BS		 1/*
2 * PowerPC floating point and SPE emulation helpers for QEMU.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include "cpu.h"
bd23cd45
BS		 20#include "helper.h"
21
22/*****************************************************************************/
23/* Floating point operations helpers */
8e703949 24uint64_t helper_float32_to_float64(CPUPPCState *env, uint32_t arg)
bd23cd45
BS		 25{
26 CPU_FloatU f;
27 CPU_DoubleU d;
28
29 f.l = arg;
30 d.d = float32_to_float64(f.f, &env->fp_status);
31 return d.ll;
32}
33
8e703949 34uint32_t helper_float64_to_float32(CPUPPCState *env, uint64_t arg)
bd23cd45
BS		 35{
36 CPU_FloatU f;
37 CPU_DoubleU d;
38
39 d.ll = arg;
40 f.f = float64_to_float32(d.d, &env->fp_status);
41 return f.l;
42}
43
44static inline int isden(float64 d)
45{
46 CPU_DoubleU u;
47
48 u.d = d;
49
50 return ((u.ll >> 52) & 0x7FF) == 0;
51}
52
da29cb7b
TM		 53static inline int ppc_float32_get_unbiased_exp(float32 f)
54{
55 return ((f >> 23) & 0xFF) - 127;
56}
57
58static inline int ppc_float64_get_unbiased_exp(float64 f)
59{
60 return ((f >> 52) & 0x7FF) - 1023;
61}
62
8e703949 63uint32_t helper_compute_fprf(CPUPPCState *env, uint64_t arg, uint32_t set_fprf)
bd23cd45
BS		 64{
65 CPU_DoubleU farg;
66 int isneg;
67 int ret;
68
69 farg.ll = arg;
70 isneg = float64_is_neg(farg.d);
71 if (unlikely(float64_is_any_nan(farg.d))) {
72 if (float64_is_signaling_nan(farg.d)) {
73 /* Signaling NaN: flags are undefined */
74 ret = 0x00;
75 } else {
76 /* Quiet NaN */
77 ret = 0x11;
78 }
79 } else if (unlikely(float64_is_infinity(farg.d))) {
80 /* +/- infinity */
81 if (isneg) {
82 ret = 0x09;
83 } else {
84 ret = 0x05;
85 }
86 } else {
87 if (float64_is_zero(farg.d)) {
88 /* +/- zero */
89 if (isneg) {
90 ret = 0x12;
91 } else {
92 ret = 0x02;
93 }
94 } else {
95 if (isden(farg.d)) {
96 /* Denormalized numbers */
97 ret = 0x10;
98 } else {
99 /* Normalized numbers */
100 ret = 0x00;
101 }
102 if (isneg) {
103 ret |= 0x08;
104 } else {
105 ret |= 0x04;
106 }
107 }
108 }
109 if (set_fprf) {
110 /* We update FPSCR_FPRF */
111 env->fpscr &= ~(0x1F << FPSCR_FPRF);
112 env->fpscr |= ret << FPSCR_FPRF;
113 }
114 /* We just need fpcc to update Rc1 */
115 return ret & 0xF;
116}
117
118/* Floating-point invalid operations exception */
59800ec8
TM		 119static inline uint64_t fload_invalid_op_excp(CPUPPCState *env, int op,
120 int set_fpcc)
bd23cd45
BS		 121{
122 uint64_t ret = 0;
123 int ve;
124
125 ve = fpscr_ve;
126 switch (op) {
127 case POWERPC_EXCP_FP_VXSNAN:
128 env->fpscr |= 1 << FPSCR_VXSNAN;
129 break;
130 case POWERPC_EXCP_FP_VXSOFT:
131 env->fpscr |= 1 << FPSCR_VXSOFT;
132 break;
133 case POWERPC_EXCP_FP_VXISI:
134 /* Magnitude subtraction of infinities */
135 env->fpscr |= 1 << FPSCR_VXISI;
136 goto update_arith;
137 case POWERPC_EXCP_FP_VXIDI:
138 /* Division of infinity by infinity */
139 env->fpscr |= 1 << FPSCR_VXIDI;
140 goto update_arith;
141 case POWERPC_EXCP_FP_VXZDZ:
142 /* Division of zero by zero */
143 env->fpscr |= 1 << FPSCR_VXZDZ;
144 goto update_arith;
145 case POWERPC_EXCP_FP_VXIMZ:
146 /* Multiplication of zero by infinity */
147 env->fpscr |= 1 << FPSCR_VXIMZ;
148 goto update_arith;
149 case POWERPC_EXCP_FP_VXVC:
150 /* Ordered comparison of NaN */
151 env->fpscr |= 1 << FPSCR_VXVC;
59800ec8
TM		 152 if (set_fpcc) {
153 env->fpscr &= ~(0xF << FPSCR_FPCC);
154 env->fpscr |= 0x11 << FPSCR_FPCC;
155 }
bd23cd45
BS		 156 /* We must update the target FPR before raising the exception */
157 if (ve != 0) {
158 env->exception_index = POWERPC_EXCP_PROGRAM;
159 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
160 /* Update the floating-point enabled exception summary */
161 env->fpscr |= 1 << FPSCR_FEX;
162 /* Exception is differed */
163 ve = 0;
164 }
165 break;
166 case POWERPC_EXCP_FP_VXSQRT:
167 /* Square root of a negative number */
168 env->fpscr |= 1 << FPSCR_VXSQRT;
169 update_arith:
170 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
171 if (ve == 0) {
172 /* Set the result to quiet NaN */
173 ret = 0x7FF8000000000000ULL;
59800ec8
TM		 174 if (set_fpcc) {
175 env->fpscr &= ~(0xF << FPSCR_FPCC);
176 env->fpscr |= 0x11 << FPSCR_FPCC;
177 }
bd23cd45
BS		 178 }
179 break;
180 case POWERPC_EXCP_FP_VXCVI:
181 /* Invalid conversion */
182 env->fpscr |= 1 << FPSCR_VXCVI;
183 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
184 if (ve == 0) {
185 /* Set the result to quiet NaN */
186 ret = 0x7FF8000000000000ULL;
59800ec8
TM		 187 if (set_fpcc) {
188 env->fpscr &= ~(0xF << FPSCR_FPCC);
189 env->fpscr |= 0x11 << FPSCR_FPCC;
190 }
bd23cd45
BS		 191 }
192 break;
193 }
194 /* Update the floating-point invalid operation summary */
195 env->fpscr |= 1 << FPSCR_VX;
196 /* Update the floating-point exception summary */
197 env->fpscr |= 1 << FPSCR_FX;
198 if (ve != 0) {
199 /* Update the floating-point enabled exception summary */
200 env->fpscr |= 1 << FPSCR_FEX;
201 if (msr_fe0 != 0 || msr_fe1 != 0) {
202 helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
203 POWERPC_EXCP_FP | op);
204 }
205 }
206 return ret;
207}
208
8e703949 209static inline void float_zero_divide_excp(CPUPPCState *env)
bd23cd45
BS		 210{
211 env->fpscr |= 1 << FPSCR_ZX;
212 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
213 /* Update the floating-point exception summary */
214 env->fpscr |= 1 << FPSCR_FX;
215 if (fpscr_ze != 0) {
216 /* Update the floating-point enabled exception summary */
217 env->fpscr |= 1 << FPSCR_FEX;
218 if (msr_fe0 != 0 || msr_fe1 != 0) {
219 helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
220 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
221 }
222 }
223}
224
8e703949 225static inline void float_overflow_excp(CPUPPCState *env)
bd23cd45
BS		 226{
227 env->fpscr |= 1 << FPSCR_OX;
228 /* Update the floating-point exception summary */
229 env->fpscr |= 1 << FPSCR_FX;
230 if (fpscr_oe != 0) {
231 /* XXX: should adjust the result */
232 /* Update the floating-point enabled exception summary */
233 env->fpscr |= 1 << FPSCR_FEX;
234 /* We must update the target FPR before raising the exception */
235 env->exception_index = POWERPC_EXCP_PROGRAM;
236 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
237 } else {
238 env->fpscr |= 1 << FPSCR_XX;
239 env->fpscr |= 1 << FPSCR_FI;
240 }
241}
242
8e703949 243static inline void float_underflow_excp(CPUPPCState *env)
bd23cd45
BS		 244{
245 env->fpscr |= 1 << FPSCR_UX;
246 /* Update the floating-point exception summary */
247 env->fpscr |= 1 << FPSCR_FX;
248 if (fpscr_ue != 0) {
249 /* XXX: should adjust the result */
250 /* Update the floating-point enabled exception summary */
251 env->fpscr |= 1 << FPSCR_FEX;
252 /* We must update the target FPR before raising the exception */
253 env->exception_index = POWERPC_EXCP_PROGRAM;
254 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
255 }
256}
257
8e703949 258static inline void float_inexact_excp(CPUPPCState *env)
bd23cd45
BS		 259{
260 env->fpscr |= 1 << FPSCR_XX;
261 /* Update the floating-point exception summary */
262 env->fpscr |= 1 << FPSCR_FX;
263 if (fpscr_xe != 0) {
264 /* Update the floating-point enabled exception summary */
265 env->fpscr |= 1 << FPSCR_FEX;
266 /* We must update the target FPR before raising the exception */
267 env->exception_index = POWERPC_EXCP_PROGRAM;
268 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
269 }
270}
271
8e703949 272static inline void fpscr_set_rounding_mode(CPUPPCState *env)
bd23cd45
BS		 273{
274 int rnd_type;
275
276 /* Set rounding mode */
277 switch (fpscr_rn) {
278 case 0:
279 /* Best approximation (round to nearest) */
280 rnd_type = float_round_nearest_even;
281 break;
282 case 1:
283 /* Smaller magnitude (round toward zero) */
284 rnd_type = float_round_to_zero;
285 break;
286 case 2:
287 /* Round toward +infinite */
288 rnd_type = float_round_up;
289 break;
290 default:
291 case 3:
292 /* Round toward -infinite */
293 rnd_type = float_round_down;
294 break;
295 }
296 set_float_rounding_mode(rnd_type, &env->fp_status);
297}
298
8e703949 299void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit)
bd23cd45
BS		 300{
301 int prev;
302
303 prev = (env->fpscr >> bit) & 1;
304 env->fpscr &= ~(1 << bit);
305 if (prev == 1) {
306 switch (bit) {
307 case FPSCR_RN1:
308 case FPSCR_RN:
8e703949 309 fpscr_set_rounding_mode(env);
bd23cd45
BS		 310 break;
311 default:
312 break;
313 }
314 }
315}
316
8e703949 317void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
bd23cd45
BS		 318{
319 int prev;
320
321 prev = (env->fpscr >> bit) & 1;
322 env->fpscr |= 1 << bit;
323 if (prev == 0) {
324 switch (bit) {
325 case FPSCR_VX:
326 env->fpscr |= 1 << FPSCR_FX;
327 if (fpscr_ve) {
328 goto raise_ve;
329 }
90638255 330 break;
bd23cd45
BS		 331 case FPSCR_OX:
332 env->fpscr |= 1 << FPSCR_FX;
333 if (fpscr_oe) {
334 goto raise_oe;
335 }
336 break;
337 case FPSCR_UX:
338 env->fpscr |= 1 << FPSCR_FX;
339 if (fpscr_ue) {
340 goto raise_ue;
341 }
342 break;
343 case FPSCR_ZX:
344 env->fpscr |= 1 << FPSCR_FX;
345 if (fpscr_ze) {
346 goto raise_ze;
347 }
348 break;
349 case FPSCR_XX:
350 env->fpscr |= 1 << FPSCR_FX;
351 if (fpscr_xe) {
352 goto raise_xe;
353 }
354 break;
355 case FPSCR_VXSNAN:
356 case FPSCR_VXISI:
357 case FPSCR_VXIDI:
358 case FPSCR_VXZDZ:
359 case FPSCR_VXIMZ:
360 case FPSCR_VXVC:
361 case FPSCR_VXSOFT:
362 case FPSCR_VXSQRT:
363 case FPSCR_VXCVI:
364 env->fpscr |= 1 << FPSCR_VX;
365 env->fpscr |= 1 << FPSCR_FX;
366 if (fpscr_ve != 0) {
367 goto raise_ve;
368 }
369 break;
370 case FPSCR_VE:
371 if (fpscr_vx != 0) {
372 raise_ve:
373 env->error_code = POWERPC_EXCP_FP;
374 if (fpscr_vxsnan) {
375 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
376 }
377 if (fpscr_vxisi) {
378 env->error_code |= POWERPC_EXCP_FP_VXISI;
379 }
380 if (fpscr_vxidi) {
381 env->error_code |= POWERPC_EXCP_FP_VXIDI;
382 }
383 if (fpscr_vxzdz) {
384 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
385 }
386 if (fpscr_vximz) {
387 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
388 }
389 if (fpscr_vxvc) {
390 env->error_code |= POWERPC_EXCP_FP_VXVC;
391 }
392 if (fpscr_vxsoft) {
393 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
394 }
395 if (fpscr_vxsqrt) {
396 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
397 }
398 if (fpscr_vxcvi) {
399 env->error_code |= POWERPC_EXCP_FP_VXCVI;
400 }
401 goto raise_excp;
402 }
403 break;
404 case FPSCR_OE:
405 if (fpscr_ox != 0) {
406 raise_oe:
407 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
408 goto raise_excp;
409 }
410 break;
411 case FPSCR_UE:
412 if (fpscr_ux != 0) {
413 raise_ue:
414 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
415 goto raise_excp;
416 }
417 break;
418 case FPSCR_ZE:
419 if (fpscr_zx != 0) {
420 raise_ze:
421 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
422 goto raise_excp;
423 }
424 break;
425 case FPSCR_XE:
426 if (fpscr_xx != 0) {
427 raise_xe:
428 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
429 goto raise_excp;
430 }
431 break;
432 case FPSCR_RN1:
433 case FPSCR_RN:
8e703949 434 fpscr_set_rounding_mode(env);
bd23cd45
BS		 435 break;
436 default:
437 break;
438 raise_excp:
439 /* Update the floating-point enabled exception summary */
440 env->fpscr |= 1 << FPSCR_FEX;
441 /* We have to update Rc1 before raising the exception */
442 env->exception_index = POWERPC_EXCP_PROGRAM;
443 break;
444 }
445 }
446}
447
8e703949 448void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
bd23cd45 449{
7d08d856 450 target_ulong prev, new;
bd23cd45
BS		 451 int i;
452
453 prev = env->fpscr;
7d08d856
AJ		 454 new = (target_ulong)arg;
455 new &= ~0x60000000LL;
456 new |= prev & 0x60000000LL;
457 for (i = 0; i < sizeof(target_ulong) * 2; i++) {
bd23cd45 458 if (mask & (1 << i)) {
7d08d856
AJ		 459 env->fpscr &= ~(0xFLL << (4 * i));
460 env->fpscr |= new & (0xFLL << (4 * i));
bd23cd45
BS		 461 }
462 }
463 /* Update VX and FEX */
464 if (fpscr_ix != 0) {
465 env->fpscr |= 1 << FPSCR_VX;
466 } else {
467 env->fpscr &= ~(1 << FPSCR_VX);
468 }
469 if ((fpscr_ex & fpscr_eex) != 0) {
470 env->fpscr |= 1 << FPSCR_FEX;
471 env->exception_index = POWERPC_EXCP_PROGRAM;
472 /* XXX: we should compute it properly */
473 env->error_code = POWERPC_EXCP_FP;
474 } else {
475 env->fpscr &= ~(1 << FPSCR_FEX);
476 }
8e703949 477 fpscr_set_rounding_mode(env);
bd23cd45
BS		 478}
479
d6478bc7
FC		 480void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
481{
482 helper_store_fpscr(env, arg, mask);
483}
484
8e703949 485void helper_float_check_status(CPUPPCState *env)
bd23cd45 486{
db72c9f2
TG		 487 int status = get_float_exception_flags(&env->fp_status);
488
489 if (status & float_flag_divbyzero) {
490 float_zero_divide_excp(env);
491 } else if (status & float_flag_overflow) {
492 float_overflow_excp(env);
493 } else if (status & float_flag_underflow) {
494 float_underflow_excp(env);
495 } else if (status & float_flag_inexact) {
496 float_inexact_excp(env);
497 }
498
bd23cd45
BS		 499 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
500 (env->error_code & POWERPC_EXCP_FP)) {
501 /* Differred floating-point exception after target FPR update */
502 if (msr_fe0 != 0 || msr_fe1 != 0) {
503 helper_raise_exception_err(env, env->exception_index,
504 env->error_code);
505 }
bd23cd45
BS		 506 }
507}
508
8e703949 509void helper_reset_fpstatus(CPUPPCState *env)
bd23cd45
BS		 510{
511 set_float_exception_flags(0, &env->fp_status);
512}
513
514/* fadd - fadd. */
8e703949 515uint64_t helper_fadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
bd23cd45
BS		 516{
517 CPU_DoubleU farg1, farg2;
518
519 farg1.ll = arg1;
520 farg2.ll = arg2;
521
522 if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
523 float64_is_neg(farg1.d) != float64_is_neg(farg2.d))) {
524 /* Magnitude subtraction of infinities */
59800ec8 525 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
bd23cd45
BS		 526 } else {
527 if (unlikely(float64_is_signaling_nan(farg1.d) ||
528 float64_is_signaling_nan(farg2.d))) {
529 /* sNaN addition */
59800ec8 530 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
bd23cd45
BS		 531 }
532 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
533 }
534
535 return farg1.ll;
536}
537
538/* fsub - fsub. */
8e703949 539uint64_t helper_fsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
bd23cd45
BS		 540{
541 CPU_DoubleU farg1, farg2;
542
543 farg1.ll = arg1;
544 farg2.ll = arg2;
545
546 if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
547 float64_is_neg(farg1.d) == float64_is_neg(farg2.d))) {
548 /* Magnitude subtraction of infinities */
59800ec8 549 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
bd23cd45
BS		 550 } else {
551 if (unlikely(float64_is_signaling_nan(farg1.d) ||
552 float64_is_signaling_nan(farg2.d))) {
553 /* sNaN subtraction */
59800ec8 554 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
bd23cd45
BS		 555 }
556 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
557 }
558
559 return farg1.ll;
560}
561
562/* fmul - fmul. */
8e703949 563uint64_t helper_fmul(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
bd23cd45
BS		 564{
565 CPU_DoubleU farg1, farg2;
566
567 farg1.ll = arg1;
568 farg2.ll = arg2;
569
570 if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
571 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
572 /* Multiplication of zero by infinity */
59800ec8 573 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
bd23cd45
BS		 574 } else {
575 if (unlikely(float64_is_signaling_nan(farg1.d) ||
576 float64_is_signaling_nan(farg2.d))) {
577 /* sNaN multiplication */
59800ec8 578 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
bd23cd45
BS		 579 }
580 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
581 }
582
583 return farg1.ll;
584}
585
586/* fdiv - fdiv. */
8e703949 587uint64_t helper_fdiv(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
bd23cd45
BS		 588{
589 CPU_DoubleU farg1, farg2;
590
591 farg1.ll = arg1;
592 farg2.ll = arg2;
593
594 if (unlikely(float64_is_infinity(farg1.d) &&
595 float64_is_infinity(farg2.d))) {
596 /* Division of infinity by infinity */
59800ec8 597 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI, 1);
bd23cd45
BS		 598 } else if (unlikely(float64_is_zero(farg1.d) && float64_is_zero(farg2.d))) {
599 /* Division of zero by zero */
59800ec8 600 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, 1);
bd23cd45
BS		 601 } else {
602 if (unlikely(float64_is_signaling_nan(farg1.d) ||
603 float64_is_signaling_nan(farg2.d))) {
604 /* sNaN division */
59800ec8 605 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
bd23cd45
BS		 606 }
607 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
608 }
609
610 return farg1.ll;
611}
612
bd23cd45 613
fab7fe42
TM		 614#define FPU_FCTI(op, cvt, nanval) \
615uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \
616{ \
617 CPU_DoubleU farg; \
618 \
619 farg.ll = arg; \
620 farg.ll = float64_to_##cvt(farg.d, &env->fp_status); \
621 \
622 if (unlikely(env->fp_status.float_exception_flags)) { \
623 if (float64_is_any_nan(arg)) { \
624 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1); \
625 if (float64_is_signaling_nan(arg)) { \
626 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); \
627 } \
628 farg.ll = nanval; \
629 } else if (env->fp_status.float_exception_flags & \
630 float_flag_invalid) { \
631 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1); \
632 } \
633 helper_float_check_status(env); \
634 } \
635 return farg.ll; \
636 }
637
7dff9abe
TM		 638FPU_FCTI(fctiw, int32, 0x80000000U)
639FPU_FCTI(fctiwz, int32_round_to_zero, 0x80000000U)
640FPU_FCTI(fctiwu, uint32, 0x00000000U)
641FPU_FCTI(fctiwuz, uint32_round_to_zero, 0x00000000U)
fab7fe42 642#if defined(TARGET_PPC64)
7dff9abe
TM		 643FPU_FCTI(fctid, int64, 0x8000000000000000ULL)
644FPU_FCTI(fctidz, int64_round_to_zero, 0x8000000000000000ULL)
645FPU_FCTI(fctidu, uint64, 0x0000000000000000ULL)
646FPU_FCTI(fctiduz, uint64_round_to_zero, 0x0000000000000000ULL)
fab7fe42 647#endif
bd23cd45
BS		 648
649#if defined(TARGET_PPC64)
bd23cd45 650
28288b48
TM		 651#define FPU_FCFI(op, cvtr, is_single) \
652uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \
653{ \
654 CPU_DoubleU farg; \
655 \
656 if (is_single) { \
657 float32 tmp = cvtr(arg, &env->fp_status); \
658 farg.d = float32_to_float64(tmp, &env->fp_status); \
659 } else { \
660 farg.d = cvtr(arg, &env->fp_status); \
661 } \
662 helper_float_check_status(env); \
663 return farg.ll; \
bd23cd45
BS		 664}
665
28288b48
TM		 666FPU_FCFI(fcfid, int64_to_float64, 0)
667FPU_FCFI(fcfids, int64_to_float32, 1)
668FPU_FCFI(fcfidu, uint64_to_float64, 0)
669FPU_FCFI(fcfidus, uint64_to_float32, 1)
bd23cd45
BS		 670
671#endif
672
8e703949
BS		 673static inline uint64_t do_fri(CPUPPCState *env, uint64_t arg,
674 int rounding_mode)
bd23cd45
BS		 675{
676 CPU_DoubleU farg;
677
678 farg.ll = arg;
679
680 if (unlikely(float64_is_signaling_nan(farg.d))) {
681 /* sNaN round */
c7386080 682 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
7dff9abe 683 farg.ll = arg | 0x0008000000000000ULL;
bd23cd45 684 } else {
c7386080
TM		 685 int inexact = get_float_exception_flags(&env->fp_status) &
686 float_flag_inexact;
bd23cd45
BS		 687 set_float_rounding_mode(rounding_mode, &env->fp_status);
688 farg.ll = float64_round_to_int(farg.d, &env->fp_status);
689 /* Restore rounding mode from FPSCR */
8e703949 690 fpscr_set_rounding_mode(env);
c7386080
TM		 691
692 /* fri* does not set FPSCR[XX] */
693 if (!inexact) {
694 env->fp_status.float_exception_flags &= ~float_flag_inexact;
695 }
bd23cd45 696 }
c7386080 697 helper_float_check_status(env);
bd23cd45
BS		 698 return farg.ll;
699}
700
8e703949 701uint64_t helper_frin(CPUPPCState *env, uint64_t arg)
bd23cd45 702{
c7386080 703 return do_fri(env, arg, float_round_ties_away);
bd23cd45
BS		 704}
705
8e703949 706uint64_t helper_friz(CPUPPCState *env, uint64_t arg)
bd23cd45 707{
8e703949 708 return do_fri(env, arg, float_round_to_zero);
bd23cd45
BS		 709}
710
8e703949 711uint64_t helper_frip(CPUPPCState *env, uint64_t arg)
bd23cd45 712{
8e703949 713 return do_fri(env, arg, float_round_up);
bd23cd45
BS		 714}
715
8e703949 716uint64_t helper_frim(CPUPPCState *env, uint64_t arg)
bd23cd45 717{
8e703949 718 return do_fri(env, arg, float_round_down);
bd23cd45
BS		 719}
720
721/* fmadd - fmadd. */
8e703949
BS		 722uint64_t helper_fmadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
723 uint64_t arg3)
bd23cd45
BS		 724{
725 CPU_DoubleU farg1, farg2, farg3;
726
727 farg1.ll = arg1;
728 farg2.ll = arg2;
729 farg3.ll = arg3;
730
731 if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
732 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
733 /* Multiplication of zero by infinity */
59800ec8 734 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
bd23cd45
BS		 735 } else {
736 if (unlikely(float64_is_signaling_nan(farg1.d) ||
737 float64_is_signaling_nan(farg2.d) ||
738 float64_is_signaling_nan(farg3.d))) {
739 /* sNaN operation */
59800ec8 740 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
bd23cd45
BS		 741 }
742 /* This is the way the PowerPC specification defines it */
743 float128 ft0_128, ft1_128;
744
745 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
746 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
747 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
748 if (unlikely(float128_is_infinity(ft0_128) &&
749 float64_is_infinity(farg3.d) &&
750 float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) {
751 /* Magnitude subtraction of infinities */
59800ec8 752 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
bd23cd45
BS		 753 } else {
754 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
755 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
756 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
757 }
758 }
759
760 return farg1.ll;
761}
762
763/* fmsub - fmsub. */
8e703949
BS		 764uint64_t helper_fmsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
765 uint64_t arg3)
bd23cd45
BS		 766{
767 CPU_DoubleU farg1, farg2, farg3;
768
769 farg1.ll = arg1;
770 farg2.ll = arg2;
771 farg3.ll = arg3;
772
773 if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
774 (float64_is_zero(farg1.d) &&
775 float64_is_infinity(farg2.d)))) {
776 /* Multiplication of zero by infinity */
59800ec8 777 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
bd23cd45
BS		 778 } else {
779 if (unlikely(float64_is_signaling_nan(farg1.d) ||
780 float64_is_signaling_nan(farg2.d) ||
781 float64_is_signaling_nan(farg3.d))) {
782 /* sNaN operation */
59800ec8 783 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
bd23cd45
BS		 784 }
785 /* This is the way the PowerPC specification defines it */
786 float128 ft0_128, ft1_128;
787
788 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
789 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
790 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
791 if (unlikely(float128_is_infinity(ft0_128) &&
792 float64_is_infinity(farg3.d) &&
793 float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) {
794 /* Magnitude subtraction of infinities */
59800ec8 795 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
bd23cd45
BS		 796 } else {
797 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
798 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
799 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
800 }
801 }
802 return farg1.ll;
803}
804
805/* fnmadd - fnmadd. */
8e703949
BS		 806uint64_t helper_fnmadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
807 uint64_t arg3)
bd23cd45
BS		 808{
809 CPU_DoubleU farg1, farg2, farg3;
810
811 farg1.ll = arg1;
812 farg2.ll = arg2;
813 farg3.ll = arg3;
814
815 if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
816 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
817 /* Multiplication of zero by infinity */
59800ec8 818 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
bd23cd45
BS		 819 } else {
820 if (unlikely(float64_is_signaling_nan(farg1.d) ||
821 float64_is_signaling_nan(farg2.d) ||
822 float64_is_signaling_nan(farg3.d))) {
823 /* sNaN operation */
59800ec8 824 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
bd23cd45
BS		 825 }
826 /* This is the way the PowerPC specification defines it */
827 float128 ft0_128, ft1_128;
828
829 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
830 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
831 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
832 if (unlikely(float128_is_infinity(ft0_128) &&
833 float64_is_infinity(farg3.d) &&
834 float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) {
835 /* Magnitude subtraction of infinities */
59800ec8 836 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
bd23cd45
BS		 837 } else {
838 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
839 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
840 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
841 }
842 if (likely(!float64_is_any_nan(farg1.d))) {
843 farg1.d = float64_chs(farg1.d);
844 }
845 }
846 return farg1.ll;
847}
848
849/* fnmsub - fnmsub. */
8e703949
BS		 850uint64_t helper_fnmsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
851 uint64_t arg3)
bd23cd45
BS		 852{
853 CPU_DoubleU farg1, farg2, farg3;
854
855 farg1.ll = arg1;
856 farg2.ll = arg2;
857 farg3.ll = arg3;
858
859 if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
860 (float64_is_zero(farg1.d) &&
861 float64_is_infinity(farg2.d)))) {
862 /* Multiplication of zero by infinity */
59800ec8 863 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
bd23cd45
BS		 864 } else {
865 if (unlikely(float64_is_signaling_nan(farg1.d) ||
866 float64_is_signaling_nan(farg2.d) ||
867 float64_is_signaling_nan(farg3.d))) {
868 /* sNaN operation */
59800ec8 869 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
bd23cd45
BS		 870 }
871 /* This is the way the PowerPC specification defines it */
872 float128 ft0_128, ft1_128;
873
874 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
875 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
876 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
877 if (unlikely(float128_is_infinity(ft0_128) &&
878 float64_is_infinity(farg3.d) &&
879 float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) {
880 /* Magnitude subtraction of infinities */
59800ec8 881 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
bd23cd45
BS		 882 } else {
883 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
884 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
885 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
886 }
887 if (likely(!float64_is_any_nan(farg1.d))) {
888 farg1.d = float64_chs(farg1.d);
889 }
890 }
891 return farg1.ll;
892}
893
894/* frsp - frsp. */
8e703949 895uint64_t helper_frsp(CPUPPCState *env, uint64_t arg)
bd23cd45
BS		 896{
897 CPU_DoubleU farg;
898 float32 f32;
899
900 farg.ll = arg;
901
902 if (unlikely(float64_is_signaling_nan(farg.d))) {
903 /* sNaN square root */
59800ec8 904 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
bd23cd45
BS		 905 }
906 f32 = float64_to_float32(farg.d, &env->fp_status);
907 farg.d = float32_to_float64(f32, &env->fp_status);
908
909 return farg.ll;
910}
911
912/* fsqrt - fsqrt. */
8e703949 913uint64_t helper_fsqrt(CPUPPCState *env, uint64_t arg)
bd23cd45
BS		 914{
915 CPU_DoubleU farg;
916
917 farg.ll = arg;
918
919 if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
920 /* Square root of a negative nonzero number */
59800ec8 921 farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1);
bd23cd45
BS		 922 } else {
923 if (unlikely(float64_is_signaling_nan(farg.d))) {
924 /* sNaN square root */
59800ec8 925 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
bd23cd45
BS		 926 }
927 farg.d = float64_sqrt(farg.d, &env->fp_status);
928 }
929 return farg.ll;
930}
931
932/* fre - fre. */
8e703949 933uint64_t helper_fre(CPUPPCState *env, uint64_t arg)
bd23cd45
BS		 934{
935 CPU_DoubleU farg;
936
937 farg.ll = arg;
938
939 if (unlikely(float64_is_signaling_nan(farg.d))) {
940 /* sNaN reciprocal */
59800ec8 941 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
bd23cd45
BS		 942 }
943 farg.d = float64_div(float64_one, farg.d, &env->fp_status);
944 return farg.d;
945}
946
947/* fres - fres. */
8e703949 948uint64_t helper_fres(CPUPPCState *env, uint64_t arg)
bd23cd45
BS		 949{
950 CPU_DoubleU farg;
951 float32 f32;
952
953 farg.ll = arg;
954
955 if (unlikely(float64_is_signaling_nan(farg.d))) {
956 /* sNaN reciprocal */
59800ec8 957 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
bd23cd45
BS		 958 }
959 farg.d = float64_div(float64_one, farg.d, &env->fp_status);
960 f32 = float64_to_float32(farg.d, &env->fp_status);
961 farg.d = float32_to_float64(f32, &env->fp_status);
962
963 return farg.ll;
964}
965
966/* frsqrte - frsqrte. */
8e703949 967uint64_t helper_frsqrte(CPUPPCState *env, uint64_t arg)
bd23cd45
BS		 968{
969 CPU_DoubleU farg;
970 float32 f32;
971
972 farg.ll = arg;
973
974 if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
975 /* Reciprocal square root of a negative nonzero number */
59800ec8 976 farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1);
bd23cd45
BS		 977 } else {
978 if (unlikely(float64_is_signaling_nan(farg.d))) {
979 /* sNaN reciprocal square root */
59800ec8 980 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
bd23cd45
BS		 981 }
982 farg.d = float64_sqrt(farg.d, &env->fp_status);
983 farg.d = float64_div(float64_one, farg.d, &env->fp_status);
984 f32 = float64_to_float32(farg.d, &env->fp_status);
985 farg.d = float32_to_float64(f32, &env->fp_status);
986 }
987 return farg.ll;
988}
989
990/* fsel - fsel. */
8e703949
BS		 991uint64_t helper_fsel(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
992 uint64_t arg3)
bd23cd45
BS		 993{
994 CPU_DoubleU farg1;
995
996 farg1.ll = arg1;
997
998 if ((!float64_is_neg(farg1.d) || float64_is_zero(farg1.d)) &&
999 !float64_is_any_nan(farg1.d)) {
1000 return arg2;
1001 } else {
1002 return arg3;
1003 }
1004}
1005
da29cb7b
TM		 1006uint32_t helper_ftdiv(uint64_t fra, uint64_t frb)
1007{
1008 int fe_flag = 0;
1009 int fg_flag = 0;
1010
1011 if (unlikely(float64_is_infinity(fra) ||
1012 float64_is_infinity(frb) ||
1013 float64_is_zero(frb))) {
1014 fe_flag = 1;
1015 fg_flag = 1;
1016 } else {
1017 int e_a = ppc_float64_get_unbiased_exp(fra);
1018 int e_b = ppc_float64_get_unbiased_exp(frb);
1019
1020 if (unlikely(float64_is_any_nan(fra) ||
1021 float64_is_any_nan(frb))) {
1022 fe_flag = 1;
1023 } else if ((e_b <= -1022) || (e_b >= 1021)) {
1024 fe_flag = 1;
1025 } else if (!float64_is_zero(fra) &&
1026 (((e_a - e_b) >= 1023) ||
1027 ((e_a - e_b) <= -1021) ||
1028 (e_a <= -970))) {
1029 fe_flag = 1;
1030 }
1031
1032 if (unlikely(float64_is_zero_or_denormal(frb))) {
1033 /* XB is not zero because of the above check and */
1034 /* so must be denormalized. */
1035 fg_flag = 1;
1036 }
1037 }
1038
1039 return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
1040}
6d41d146
TM		 1041
1042uint32_t helper_ftsqrt(uint64_t frb)
1043{
1044 int fe_flag = 0;
1045 int fg_flag = 0;
1046
1047 if (unlikely(float64_is_infinity(frb) || float64_is_zero(frb))) {
1048 fe_flag = 1;
1049 fg_flag = 1;
1050 } else {
1051 int e_b = ppc_float64_get_unbiased_exp(frb);
1052
1053 if (unlikely(float64_is_any_nan(frb))) {
1054 fe_flag = 1;
1055 } else if (unlikely(float64_is_zero(frb))) {
1056 fe_flag = 1;
1057 } else if (unlikely(float64_is_neg(frb))) {
1058 fe_flag = 1;
1059 } else if (!float64_is_zero(frb) && (e_b <= (-1022+52))) {
1060 fe_flag = 1;
1061 }
1062
1063 if (unlikely(float64_is_zero_or_denormal(frb))) {
1064 /* XB is not zero because of the above check and */
1065 /* therefore must be denormalized. */
1066 fg_flag = 1;
1067 }
1068 }
1069
1070 return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
1071}
da29cb7b 1072
8e703949
BS		 1073void helper_fcmpu(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
1074 uint32_t crfD)
bd23cd45
BS		 1075{
1076 CPU_DoubleU farg1, farg2;
1077 uint32_t ret = 0;
1078
1079 farg1.ll = arg1;
1080 farg2.ll = arg2;
1081
1082 if (unlikely(float64_is_any_nan(farg1.d) ||
1083 float64_is_any_nan(farg2.d))) {
1084 ret = 0x01UL;
1085 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1086 ret = 0x08UL;
1087 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1088 ret = 0x04UL;
1089 } else {
1090 ret = 0x02UL;
1091 }
1092
1093 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1094 env->fpscr |= ret << FPSCR_FPRF;
1095 env->crf[crfD] = ret;
1096 if (unlikely(ret == 0x01UL
1097 && (float64_is_signaling_nan(farg1.d) ||
1098 float64_is_signaling_nan(farg2.d)))) {
1099 /* sNaN comparison */
59800ec8 1100 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
bd23cd45
BS		 1101 }
1102}
1103
8e703949
BS		 1104void helper_fcmpo(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
1105 uint32_t crfD)
bd23cd45
BS		 1106{
1107 CPU_DoubleU farg1, farg2;
1108 uint32_t ret = 0;
1109
1110 farg1.ll = arg1;
1111 farg2.ll = arg2;
1112
1113 if (unlikely(float64_is_any_nan(farg1.d) ||
1114 float64_is_any_nan(farg2.d))) {
1115 ret = 0x01UL;
1116 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1117 ret = 0x08UL;
1118 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1119 ret = 0x04UL;
1120 } else {
1121 ret = 0x02UL;
1122 }
1123
1124 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1125 env->fpscr |= ret << FPSCR_FPRF;
1126 env->crf[crfD] = ret;
1127 if (unlikely(ret == 0x01UL)) {
1128 if (float64_is_signaling_nan(farg1.d) ||
1129 float64_is_signaling_nan(farg2.d)) {
1130 /* sNaN comparison */
8e703949 1131 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
59800ec8 1132 POWERPC_EXCP_FP_VXVC, 1);
bd23cd45
BS		 1133 } else {
1134 /* qNaN comparison */
59800ec8 1135 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 1);
bd23cd45
BS		 1136 }
1137 }
1138}
1139
1140/* Single-precision floating-point conversions */
8e703949 1141static inline uint32_t efscfsi(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1142{
1143 CPU_FloatU u;
1144
1145 u.f = int32_to_float32(val, &env->vec_status);
1146
1147 return u.l;
1148}
1149
8e703949 1150static inline uint32_t efscfui(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1151{
1152 CPU_FloatU u;
1153
1154 u.f = uint32_to_float32(val, &env->vec_status);
1155
1156 return u.l;
1157}
1158
8e703949 1159static inline int32_t efsctsi(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1160{
1161 CPU_FloatU u;
1162
1163 u.l = val;
1164 /* NaN are not treated the same way IEEE 754 does */
1165 if (unlikely(float32_is_quiet_nan(u.f))) {
1166 return 0;
1167 }
1168
1169 return float32_to_int32(u.f, &env->vec_status);
1170}
1171
8e703949 1172static inline uint32_t efsctui(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1173{
1174 CPU_FloatU u;
1175
1176 u.l = val;
1177 /* NaN are not treated the same way IEEE 754 does */
1178 if (unlikely(float32_is_quiet_nan(u.f))) {
1179 return 0;
1180 }
1181
1182 return float32_to_uint32(u.f, &env->vec_status);
1183}
1184
8e703949 1185static inline uint32_t efsctsiz(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1186{
1187 CPU_FloatU u;
1188
1189 u.l = val;
1190 /* NaN are not treated the same way IEEE 754 does */
1191 if (unlikely(float32_is_quiet_nan(u.f))) {
1192 return 0;
1193 }
1194
1195 return float32_to_int32_round_to_zero(u.f, &env->vec_status);
1196}
1197
8e703949 1198static inline uint32_t efsctuiz(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1199{
1200 CPU_FloatU u;
1201
1202 u.l = val;
1203 /* NaN are not treated the same way IEEE 754 does */
1204 if (unlikely(float32_is_quiet_nan(u.f))) {
1205 return 0;
1206 }
1207
1208 return float32_to_uint32_round_to_zero(u.f, &env->vec_status);
1209}
1210
8e703949 1211static inline uint32_t efscfsf(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1212{
1213 CPU_FloatU u;
1214 float32 tmp;
1215
1216 u.f = int32_to_float32(val, &env->vec_status);
1217 tmp = int64_to_float32(1ULL << 32, &env->vec_status);
1218 u.f = float32_div(u.f, tmp, &env->vec_status);
1219
1220 return u.l;
1221}
1222
8e703949 1223static inline uint32_t efscfuf(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1224{
1225 CPU_FloatU u;
1226 float32 tmp;
1227
1228 u.f = uint32_to_float32(val, &env->vec_status);
1229 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1230 u.f = float32_div(u.f, tmp, &env->vec_status);
1231
1232 return u.l;
1233}
1234
8e703949 1235static inline uint32_t efsctsf(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1236{
1237 CPU_FloatU u;
1238 float32 tmp;
1239
1240 u.l = val;
1241 /* NaN are not treated the same way IEEE 754 does */
1242 if (unlikely(float32_is_quiet_nan(u.f))) {
1243 return 0;
1244 }
1245 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1246 u.f = float32_mul(u.f, tmp, &env->vec_status);
1247
1248 return float32_to_int32(u.f, &env->vec_status);
1249}
1250
8e703949 1251static inline uint32_t efsctuf(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1252{
1253 CPU_FloatU u;
1254 float32 tmp;
1255
1256 u.l = val;
1257 /* NaN are not treated the same way IEEE 754 does */
1258 if (unlikely(float32_is_quiet_nan(u.f))) {
1259 return 0;
1260 }
1261 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1262 u.f = float32_mul(u.f, tmp, &env->vec_status);
1263
1264 return float32_to_uint32(u.f, &env->vec_status);
1265}
1266
8e703949
BS		 1267#define HELPER_SPE_SINGLE_CONV(name) \
1268 uint32_t helper_e##name(CPUPPCState *env, uint32_t val) \
1269 { \
1270 return e##name(env, val); \
bd23cd45
BS		 1271 }
1272/* efscfsi */
1273HELPER_SPE_SINGLE_CONV(fscfsi);
1274/* efscfui */
1275HELPER_SPE_SINGLE_CONV(fscfui);
1276/* efscfuf */
1277HELPER_SPE_SINGLE_CONV(fscfuf);
1278/* efscfsf */
1279HELPER_SPE_SINGLE_CONV(fscfsf);
1280/* efsctsi */
1281HELPER_SPE_SINGLE_CONV(fsctsi);
1282/* efsctui */
1283HELPER_SPE_SINGLE_CONV(fsctui);
1284/* efsctsiz */
1285HELPER_SPE_SINGLE_CONV(fsctsiz);
1286/* efsctuiz */
1287HELPER_SPE_SINGLE_CONV(fsctuiz);
1288/* efsctsf */
1289HELPER_SPE_SINGLE_CONV(fsctsf);
1290/* efsctuf */
1291HELPER_SPE_SINGLE_CONV(fsctuf);
1292
8e703949
BS		 1293#define HELPER_SPE_VECTOR_CONV(name) \
1294 uint64_t helper_ev##name(CPUPPCState *env, uint64_t val) \
1295 { \
1296 return ((uint64_t)e##name(env, val >> 32) << 32) | \
1297 (uint64_t)e##name(env, val); \
bd23cd45
BS		 1298 }
1299/* evfscfsi */
1300HELPER_SPE_VECTOR_CONV(fscfsi);
1301/* evfscfui */
1302HELPER_SPE_VECTOR_CONV(fscfui);
1303/* evfscfuf */
1304HELPER_SPE_VECTOR_CONV(fscfuf);
1305/* evfscfsf */
1306HELPER_SPE_VECTOR_CONV(fscfsf);
1307/* evfsctsi */
1308HELPER_SPE_VECTOR_CONV(fsctsi);
1309/* evfsctui */
1310HELPER_SPE_VECTOR_CONV(fsctui);
1311/* evfsctsiz */
1312HELPER_SPE_VECTOR_CONV(fsctsiz);
1313/* evfsctuiz */
1314HELPER_SPE_VECTOR_CONV(fsctuiz);
1315/* evfsctsf */
1316HELPER_SPE_VECTOR_CONV(fsctsf);
1317/* evfsctuf */
1318HELPER_SPE_VECTOR_CONV(fsctuf);
1319
1320/* Single-precision floating-point arithmetic */
8e703949 1321static inline uint32_t efsadd(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1322{
1323 CPU_FloatU u1, u2;
1324
1325 u1.l = op1;
1326 u2.l = op2;
1327 u1.f = float32_add(u1.f, u2.f, &env->vec_status);
1328 return u1.l;
1329}
1330
8e703949 1331static inline uint32_t efssub(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1332{
1333 CPU_FloatU u1, u2;
1334
1335 u1.l = op1;
1336 u2.l = op2;
1337 u1.f = float32_sub(u1.f, u2.f, &env->vec_status);
1338 return u1.l;
1339}
1340
8e703949 1341static inline uint32_t efsmul(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1342{
1343 CPU_FloatU u1, u2;
1344
1345 u1.l = op1;
1346 u2.l = op2;
1347 u1.f = float32_mul(u1.f, u2.f, &env->vec_status);
1348 return u1.l;
1349}
1350
8e703949 1351static inline uint32_t efsdiv(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1352{
1353 CPU_FloatU u1, u2;
1354
1355 u1.l = op1;
1356 u2.l = op2;
1357 u1.f = float32_div(u1.f, u2.f, &env->vec_status);
1358 return u1.l;
1359}
1360
8e703949
BS		 1361#define HELPER_SPE_SINGLE_ARITH(name) \
1362 uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1363 { \
1364 return e##name(env, op1, op2); \
bd23cd45
BS		 1365 }
1366/* efsadd */
1367HELPER_SPE_SINGLE_ARITH(fsadd);
1368/* efssub */
1369HELPER_SPE_SINGLE_ARITH(fssub);
1370/* efsmul */
1371HELPER_SPE_SINGLE_ARITH(fsmul);
1372/* efsdiv */
1373HELPER_SPE_SINGLE_ARITH(fsdiv);
1374
1375#define HELPER_SPE_VECTOR_ARITH(name) \
8e703949 1376 uint64_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
bd23cd45 1377 { \
8e703949
BS		 1378 return ((uint64_t)e##name(env, op1 >> 32, op2 >> 32) << 32) | \
1379 (uint64_t)e##name(env, op1, op2); \
bd23cd45
BS		 1380 }
1381/* evfsadd */
1382HELPER_SPE_VECTOR_ARITH(fsadd);
1383/* evfssub */
1384HELPER_SPE_VECTOR_ARITH(fssub);
1385/* evfsmul */
1386HELPER_SPE_VECTOR_ARITH(fsmul);
1387/* evfsdiv */
1388HELPER_SPE_VECTOR_ARITH(fsdiv);
1389
1390/* Single-precision floating-point comparisons */
8e703949 1391static inline uint32_t efscmplt(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1392{
1393 CPU_FloatU u1, u2;
1394
1395 u1.l = op1;
1396 u2.l = op2;
1397 return float32_lt(u1.f, u2.f, &env->vec_status) ? 4 : 0;
1398}
1399
8e703949 1400static inline uint32_t efscmpgt(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1401{
1402 CPU_FloatU u1, u2;
1403
1404 u1.l = op1;
1405 u2.l = op2;
1406 return float32_le(u1.f, u2.f, &env->vec_status) ? 0 : 4;
1407}
1408
8e703949 1409static inline uint32_t efscmpeq(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1410{
1411 CPU_FloatU u1, u2;
1412
1413 u1.l = op1;
1414 u2.l = op2;
1415 return float32_eq(u1.f, u2.f, &env->vec_status) ? 4 : 0;
1416}
1417
8e703949 1418static inline uint32_t efststlt(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1419{
1420 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
8e703949 1421 return efscmplt(env, op1, op2);
bd23cd45
BS		 1422}
1423
8e703949 1424static inline uint32_t efststgt(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1425{
1426 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
8e703949 1427 return efscmpgt(env, op1, op2);
bd23cd45
BS		 1428}
1429
8e703949 1430static inline uint32_t efststeq(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1431{
1432 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
8e703949 1433 return efscmpeq(env, op1, op2);
bd23cd45
BS		 1434}
1435
8e703949
BS		 1436#define HELPER_SINGLE_SPE_CMP(name) \
1437 uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1438 { \
1439 return e##name(env, op1, op2) << 2; \
bd23cd45
BS		 1440 }
1441/* efststlt */
1442HELPER_SINGLE_SPE_CMP(fststlt);
1443/* efststgt */
1444HELPER_SINGLE_SPE_CMP(fststgt);
1445/* efststeq */
1446HELPER_SINGLE_SPE_CMP(fststeq);
1447/* efscmplt */
1448HELPER_SINGLE_SPE_CMP(fscmplt);
1449/* efscmpgt */
1450HELPER_SINGLE_SPE_CMP(fscmpgt);
1451/* efscmpeq */
1452HELPER_SINGLE_SPE_CMP(fscmpeq);
1453
1454static inline uint32_t evcmp_merge(int t0, int t1)
1455{
1456 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
1457}
1458
1459#define HELPER_VECTOR_SPE_CMP(name) \
8e703949 1460 uint32_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
bd23cd45 1461 { \
8e703949
BS		 1462 return evcmp_merge(e##name(env, op1 >> 32, op2 >> 32), \
1463 e##name(env, op1, op2)); \
bd23cd45
BS		 1464 }
1465/* evfststlt */
1466HELPER_VECTOR_SPE_CMP(fststlt);
1467/* evfststgt */
1468HELPER_VECTOR_SPE_CMP(fststgt);
1469/* evfststeq */
1470HELPER_VECTOR_SPE_CMP(fststeq);
1471/* evfscmplt */
1472HELPER_VECTOR_SPE_CMP(fscmplt);
1473/* evfscmpgt */
1474HELPER_VECTOR_SPE_CMP(fscmpgt);
1475/* evfscmpeq */
1476HELPER_VECTOR_SPE_CMP(fscmpeq);
1477
1478/* Double-precision floating-point conversion */
8e703949 1479uint64_t helper_efdcfsi(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1480{
1481 CPU_DoubleU u;
1482
1483 u.d = int32_to_float64(val, &env->vec_status);
1484
1485 return u.ll;
1486}
1487
8e703949 1488uint64_t helper_efdcfsid(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1489{
1490 CPU_DoubleU u;
1491
1492 u.d = int64_to_float64(val, &env->vec_status);
1493
1494 return u.ll;
1495}
1496
8e703949 1497uint64_t helper_efdcfui(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1498{
1499 CPU_DoubleU u;
1500
1501 u.d = uint32_to_float64(val, &env->vec_status);
1502
1503 return u.ll;
1504}
1505
8e703949 1506uint64_t helper_efdcfuid(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1507{
1508 CPU_DoubleU u;
1509
1510 u.d = uint64_to_float64(val, &env->vec_status);
1511
1512 return u.ll;
1513}
1514
8e703949 1515uint32_t helper_efdctsi(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1516{
1517 CPU_DoubleU u;
1518
1519 u.ll = val;
1520 /* NaN are not treated the same way IEEE 754 does */
1521 if (unlikely(float64_is_any_nan(u.d))) {
1522 return 0;
1523 }
1524
1525 return float64_to_int32(u.d, &env->vec_status);
1526}
1527
8e703949 1528uint32_t helper_efdctui(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1529{
1530 CPU_DoubleU u;
1531
1532 u.ll = val;
1533 /* NaN are not treated the same way IEEE 754 does */
1534 if (unlikely(float64_is_any_nan(u.d))) {
1535 return 0;
1536 }
1537
1538 return float64_to_uint32(u.d, &env->vec_status);
1539}
1540
8e703949 1541uint32_t helper_efdctsiz(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1542{
1543 CPU_DoubleU u;
1544
1545 u.ll = val;
1546 /* NaN are not treated the same way IEEE 754 does */
1547 if (unlikely(float64_is_any_nan(u.d))) {
1548 return 0;
1549 }
1550
1551 return float64_to_int32_round_to_zero(u.d, &env->vec_status);
1552}
1553
8e703949 1554uint64_t helper_efdctsidz(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1555{
1556 CPU_DoubleU u;
1557
1558 u.ll = val;
1559 /* NaN are not treated the same way IEEE 754 does */
1560 if (unlikely(float64_is_any_nan(u.d))) {
1561 return 0;
1562 }
1563
1564 return float64_to_int64_round_to_zero(u.d, &env->vec_status);
1565}
1566
8e703949 1567uint32_t helper_efdctuiz(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1568{
1569 CPU_DoubleU u;
1570
1571 u.ll = val;
1572 /* NaN are not treated the same way IEEE 754 does */
1573 if (unlikely(float64_is_any_nan(u.d))) {
1574 return 0;
1575 }
1576
1577 return float64_to_uint32_round_to_zero(u.d, &env->vec_status);
1578}
1579
8e703949 1580uint64_t helper_efdctuidz(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1581{
1582 CPU_DoubleU u;
1583
1584 u.ll = val;
1585 /* NaN are not treated the same way IEEE 754 does */
1586 if (unlikely(float64_is_any_nan(u.d))) {
1587 return 0;
1588 }
1589
1590 return float64_to_uint64_round_to_zero(u.d, &env->vec_status);
1591}
1592
8e703949 1593uint64_t helper_efdcfsf(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1594{
1595 CPU_DoubleU u;
1596 float64 tmp;
1597
1598 u.d = int32_to_float64(val, &env->vec_status);
1599 tmp = int64_to_float64(1ULL << 32, &env->vec_status);
1600 u.d = float64_div(u.d, tmp, &env->vec_status);
1601
1602 return u.ll;
1603}
1604
8e703949 1605uint64_t helper_efdcfuf(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1606{
1607 CPU_DoubleU u;
1608 float64 tmp;
1609
1610 u.d = uint32_to_float64(val, &env->vec_status);
1611 tmp = int64_to_float64(1ULL << 32, &env->vec_status);
1612 u.d = float64_div(u.d, tmp, &env->vec_status);
1613
1614 return u.ll;
1615}
1616
8e703949 1617uint32_t helper_efdctsf(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1618{
1619 CPU_DoubleU u;
1620 float64 tmp;
1621
1622 u.ll = val;
1623 /* NaN are not treated the same way IEEE 754 does */
1624 if (unlikely(float64_is_any_nan(u.d))) {
1625 return 0;
1626 }
1627 tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
1628 u.d = float64_mul(u.d, tmp, &env->vec_status);
1629
1630 return float64_to_int32(u.d, &env->vec_status);
1631}
1632
8e703949 1633uint32_t helper_efdctuf(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1634{
1635 CPU_DoubleU u;
1636 float64 tmp;
1637
1638 u.ll = val;
1639 /* NaN are not treated the same way IEEE 754 does */
1640 if (unlikely(float64_is_any_nan(u.d))) {
1641 return 0;
1642 }
1643 tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
1644 u.d = float64_mul(u.d, tmp, &env->vec_status);
1645
1646 return float64_to_uint32(u.d, &env->vec_status);
1647}
1648
8e703949 1649uint32_t helper_efscfd(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1650{
1651 CPU_DoubleU u1;
1652 CPU_FloatU u2;
1653
1654 u1.ll = val;
1655 u2.f = float64_to_float32(u1.d, &env->vec_status);
1656
1657 return u2.l;
1658}
1659
8e703949 1660uint64_t helper_efdcfs(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1661{
1662 CPU_DoubleU u2;
1663 CPU_FloatU u1;
1664
1665 u1.l = val;
1666 u2.d = float32_to_float64(u1.f, &env->vec_status);
1667
1668 return u2.ll;
1669}
1670
1671/* Double precision fixed-point arithmetic */
8e703949 1672uint64_t helper_efdadd(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1673{
1674 CPU_DoubleU u1, u2;
1675
1676 u1.ll = op1;
1677 u2.ll = op2;
1678 u1.d = float64_add(u1.d, u2.d, &env->vec_status);
1679 return u1.ll;
1680}
1681
8e703949 1682uint64_t helper_efdsub(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1683{
1684 CPU_DoubleU u1, u2;
1685
1686 u1.ll = op1;
1687 u2.ll = op2;
1688 u1.d = float64_sub(u1.d, u2.d, &env->vec_status);
1689 return u1.ll;
1690}
1691
8e703949 1692uint64_t helper_efdmul(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1693{
1694 CPU_DoubleU u1, u2;
1695
1696 u1.ll = op1;
1697 u2.ll = op2;
1698 u1.d = float64_mul(u1.d, u2.d, &env->vec_status);
1699 return u1.ll;
1700}
1701
8e703949 1702uint64_t helper_efddiv(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1703{
1704 CPU_DoubleU u1, u2;
1705
1706 u1.ll = op1;
1707 u2.ll = op2;
1708 u1.d = float64_div(u1.d, u2.d, &env->vec_status);
1709 return u1.ll;
1710}
1711
1712/* Double precision floating point helpers */
8e703949 1713uint32_t helper_efdtstlt(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1714{
1715 CPU_DoubleU u1, u2;
1716
1717 u1.ll = op1;
1718 u2.ll = op2;
1719 return float64_lt(u1.d, u2.d, &env->vec_status) ? 4 : 0;
1720}
1721
8e703949 1722uint32_t helper_efdtstgt(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1723{
1724 CPU_DoubleU u1, u2;
1725
1726 u1.ll = op1;
1727 u2.ll = op2;
1728 return float64_le(u1.d, u2.d, &env->vec_status) ? 0 : 4;
1729}
1730
8e703949 1731uint32_t helper_efdtsteq(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1732{
1733 CPU_DoubleU u1, u2;
1734
1735 u1.ll = op1;
1736 u2.ll = op2;
1737 return float64_eq_quiet(u1.d, u2.d, &env->vec_status) ? 4 : 0;
1738}
1739
8e703949 1740uint32_t helper_efdcmplt(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1741{
1742 /* XXX: TODO: test special values (NaN, infinites, ...) */
8e703949 1743 return helper_efdtstlt(env, op1, op2);
bd23cd45
BS		 1744}
1745
8e703949 1746uint32_t helper_efdcmpgt(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1747{
1748 /* XXX: TODO: test special values (NaN, infinites, ...) */
8e703949 1749 return helper_efdtstgt(env, op1, op2);
bd23cd45
BS		 1750}
1751
8e703949 1752uint32_t helper_efdcmpeq(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1753{
1754 /* XXX: TODO: test special values (NaN, infinites, ...) */
8e703949 1755 return helper_efdtsteq(env, op1, op2);
bd23cd45 1756}
3c3cbbdc
TM		 1757
1758#define DECODE_SPLIT(opcode, shift1, nb1, shift2, nb2) \
1759 (((((opcode) >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
1760 (((opcode) >> (shift2)) & ((1 << (nb2)) - 1)))
1761
1762#define xT(opcode) DECODE_SPLIT(opcode, 0, 1, 21, 5)
1763#define xA(opcode) DECODE_SPLIT(opcode, 2, 1, 16, 5)
1764#define xB(opcode) DECODE_SPLIT(opcode, 1, 1, 11, 5)
1765#define xC(opcode) DECODE_SPLIT(opcode, 3, 1, 6, 5)
1766#define BF(opcode) (((opcode) >> (31-8)) & 7)
1767
1768typedef union _ppc_vsr_t {
1769 uint64_t u64[2];
1770 uint32_t u32[4];
1771 float32 f32[4];
1772 float64 f64[2];
1773} ppc_vsr_t;
1774
1775static void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
1776{
1777 if (n < 32) {
1778 vsr->f64[0] = env->fpr[n];
1779 vsr->u64[1] = env->vsr[n];
1780 } else {
1781 vsr->u64[0] = env->avr[n-32].u64[0];
1782 vsr->u64[1] = env->avr[n-32].u64[1];
1783 }
1784}
1785
1786static void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
1787{
1788 if (n < 32) {
1789 env->fpr[n] = vsr->f64[0];
1790 env->vsr[n] = vsr->u64[1];
1791 } else {
1792 env->avr[n-32].u64[0] = vsr->u64[0];
1793 env->avr[n-32].u64[1] = vsr->u64[1];
1794 }
1795}
1796
1797#define float64_to_float64(x, env) x
ee6e02c0
TM		 1798
1799
1800/* VSX_ADD_SUB - VSX floating point add/subract
1801 * name - instruction mnemonic
1802 * op - operation (add or sub)
1803 * nels - number of elements (1, 2 or 4)
1804 * tp - type (float32 or float64)
1805 * fld - vsr_t field (f32 or f64)
1806 * sfprf - set FPRF
1807 */
3fd0aadf 1808#define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf, r2sp) \
ee6e02c0
TM		 1809void helper_##name(CPUPPCState *env, uint32_t opcode) \
1810{ \
1811 ppc_vsr_t xt, xa, xb; \
1812 int i; \
1813 \
1814 getVSR(xA(opcode), &xa, env); \
1815 getVSR(xB(opcode), &xb, env); \
1816 getVSR(xT(opcode), &xt, env); \
1817 helper_reset_fpstatus(env); \
1818 \
1819 for (i = 0; i < nels; i++) { \
1820 float_status tstat = env->fp_status; \
1821 set_float_exception_flags(0, &tstat); \
1822 xt.fld[i] = tp##_##op(xa.fld[i], xb.fld[i], &tstat); \
1823 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1824 \
1825 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1826 if (tp##_is_infinity(xa.fld[i]) && tp##_is_infinity(xb.fld[i])) {\
1827 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, sfprf); \
1828 } else if (tp##_is_signaling_nan(xa.fld[i]) || \
1829 tp##_is_signaling_nan(xb.fld[i])) { \
1830 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
1831 } \
1832 } \
1833 \
3fd0aadf
TM		 1834 if (r2sp) { \
1835 xt.fld[i] = helper_frsp(env, xt.fld[i]); \
1836 } \
1837 \
ee6e02c0
TM		 1838 if (sfprf) { \
1839 helper_compute_fprf(env, xt.fld[i], sfprf); \
1840 } \
1841 } \
1842 putVSR(xT(opcode), &xt, env); \
1843 helper_float_check_status(env); \
1844}
1845
3fd0aadf
TM		 1846VSX_ADD_SUB(xsadddp, add, 1, float64, f64, 1, 0)
1847VSX_ADD_SUB(xsaddsp, add, 1, float64, f64, 1, 1)
1848VSX_ADD_SUB(xvadddp, add, 2, float64, f64, 0, 0)
1849VSX_ADD_SUB(xvaddsp, add, 4, float32, f32, 0, 0)
1850VSX_ADD_SUB(xssubdp, sub, 1, float64, f64, 1, 0)
1851VSX_ADD_SUB(xssubsp, sub, 1, float64, f64, 1, 1)
1852VSX_ADD_SUB(xvsubdp, sub, 2, float64, f64, 0, 0)
1853VSX_ADD_SUB(xvsubsp, sub, 4, float32, f32, 0, 0)
5e591d88
TM		 1854
1855/* VSX_MUL - VSX floating point multiply
1856 * op - instruction mnemonic
1857 * nels - number of elements (1, 2 or 4)
1858 * tp - type (float32 or float64)
1859 * fld - vsr_t field (f32 or f64)
1860 * sfprf - set FPRF
1861 */
ab9408a2 1862#define VSX_MUL(op, nels, tp, fld, sfprf, r2sp) \
5e591d88
TM		 1863void helper_##op(CPUPPCState *env, uint32_t opcode) \
1864{ \
1865 ppc_vsr_t xt, xa, xb; \
1866 int i; \
1867 \
1868 getVSR(xA(opcode), &xa, env); \
1869 getVSR(xB(opcode), &xb, env); \
1870 getVSR(xT(opcode), &xt, env); \
1871 helper_reset_fpstatus(env); \
1872 \
1873 for (i = 0; i < nels; i++) { \
1874 float_status tstat = env->fp_status; \
1875 set_float_exception_flags(0, &tstat); \
1876 xt.fld[i] = tp##_mul(xa.fld[i], xb.fld[i], &tstat); \
1877 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1878 \
1879 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1880 if ((tp##_is_infinity(xa.fld[i]) && tp##_is_zero(xb.fld[i])) || \
1881 (tp##_is_infinity(xb.fld[i]) && tp##_is_zero(xa.fld[i]))) { \
1882 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, sfprf); \
1883 } else if (tp##_is_signaling_nan(xa.fld[i]) || \
1884 tp##_is_signaling_nan(xb.fld[i])) { \
1885 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
1886 } \
1887 } \
1888 \
ab9408a2
TM		 1889 if (r2sp) { \
1890 xt.fld[i] = helper_frsp(env, xt.fld[i]); \
1891 } \
1892 \
5e591d88
TM		 1893 if (sfprf) { \
1894 helper_compute_fprf(env, xt.fld[i], sfprf); \
1895 } \
1896 } \
1897 \
1898 putVSR(xT(opcode), &xt, env); \
1899 helper_float_check_status(env); \
1900}
1901
ab9408a2
TM		 1902VSX_MUL(xsmuldp, 1, float64, f64, 1, 0)
1903VSX_MUL(xsmulsp, 1, float64, f64, 1, 1)
1904VSX_MUL(xvmuldp, 2, float64, f64, 0, 0)
1905VSX_MUL(xvmulsp, 4, float32, f32, 0, 0)
4b98eeef
TM		 1906
1907/* VSX_DIV - VSX floating point divide
1908 * op - instruction mnemonic
1909 * nels - number of elements (1, 2 or 4)
1910 * tp - type (float32 or float64)
1911 * fld - vsr_t field (f32 or f64)
1912 * sfprf - set FPRF
1913 */
b24d0b47 1914#define VSX_DIV(op, nels, tp, fld, sfprf, r2sp) \
4b98eeef
TM		 1915void helper_##op(CPUPPCState *env, uint32_t opcode) \
1916{ \
1917 ppc_vsr_t xt, xa, xb; \
1918 int i; \
1919 \
1920 getVSR(xA(opcode), &xa, env); \
1921 getVSR(xB(opcode), &xb, env); \
1922 getVSR(xT(opcode), &xt, env); \
1923 helper_reset_fpstatus(env); \
1924 \
1925 for (i = 0; i < nels; i++) { \
1926 float_status tstat = env->fp_status; \
1927 set_float_exception_flags(0, &tstat); \
1928 xt.fld[i] = tp##_div(xa.fld[i], xb.fld[i], &tstat); \
1929 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1930 \
1931 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1932 if (tp##_is_infinity(xa.fld[i]) && tp##_is_infinity(xb.fld[i])) { \
1933 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI, sfprf); \
1934 } else if (tp##_is_zero(xa.fld[i]) && \
1935 tp##_is_zero(xb.fld[i])) { \
1936 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, sfprf); \
1937 } else if (tp##_is_signaling_nan(xa.fld[i]) || \
1938 tp##_is_signaling_nan(xb.fld[i])) { \
1939 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
1940 } \
1941 } \
1942 \
b24d0b47
TM		 1943 if (r2sp) { \
1944 xt.fld[i] = helper_frsp(env, xt.fld[i]); \
1945 } \
1946 \
4b98eeef
TM		 1947 if (sfprf) { \
1948 helper_compute_fprf(env, xt.fld[i], sfprf); \
1949 } \
1950 } \
1951 \
1952 putVSR(xT(opcode), &xt, env); \
1953 helper_float_check_status(env); \
1954}
1955
b24d0b47
TM		 1956VSX_DIV(xsdivdp, 1, float64, f64, 1, 0)
1957VSX_DIV(xsdivsp, 1, float64, f64, 1, 1)
1958VSX_DIV(xvdivdp, 2, float64, f64, 0, 0)
1959VSX_DIV(xvdivsp, 4, float32, f32, 0, 0)
2009227f
TM		 1960
1961/* VSX_RE - VSX floating point reciprocal estimate
1962 * op - instruction mnemonic
1963 * nels - number of elements (1, 2 or 4)
1964 * tp - type (float32 or float64)
1965 * fld - vsr_t field (f32 or f64)
1966 * sfprf - set FPRF
1967 */
2c0c52ae 1968#define VSX_RE(op, nels, tp, fld, sfprf, r2sp) \
2009227f
TM		 1969void helper_##op(CPUPPCState *env, uint32_t opcode) \
1970{ \
1971 ppc_vsr_t xt, xb; \
1972 int i; \
1973 \
1974 getVSR(xB(opcode), &xb, env); \
1975 getVSR(xT(opcode), &xt, env); \
1976 helper_reset_fpstatus(env); \
1977 \
1978 for (i = 0; i < nels; i++) { \
1979 if (unlikely(tp##_is_signaling_nan(xb.fld[i]))) { \
1980 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
1981 } \
1982 xt.fld[i] = tp##_div(tp##_one, xb.fld[i], &env->fp_status); \
2c0c52ae
TM		 1983 \
1984 if (r2sp) { \
1985 xt.fld[i] = helper_frsp(env, xt.fld[i]); \
1986 } \
1987 \
2009227f
TM		 1988 if (sfprf) { \
1989 helper_compute_fprf(env, xt.fld[0], sfprf); \
1990 } \
1991 } \
1992 \
1993 putVSR(xT(opcode), &xt, env); \
1994 helper_float_check_status(env); \
1995}
1996
2c0c52ae
TM		 1997VSX_RE(xsredp, 1, float64, f64, 1, 0)
1998VSX_RE(xsresp, 1, float64, f64, 1, 1)
1999VSX_RE(xvredp, 2, float64, f64, 0, 0)
2000VSX_RE(xvresp, 4, float32, f32, 0, 0)
d32404fe
TM		 2001
2002/* VSX_SQRT - VSX floating point square root
2003 * op - instruction mnemonic
2004 * nels - number of elements (1, 2 or 4)
2005 * tp - type (float32 or float64)
2006 * fld - vsr_t field (f32 or f64)
2007 * sfprf - set FPRF
2008 */
cea4e574 2009#define VSX_SQRT(op, nels, tp, fld, sfprf, r2sp) \
d32404fe
TM		 2010void helper_##op(CPUPPCState *env, uint32_t opcode) \
2011{ \
2012 ppc_vsr_t xt, xb; \
2013 int i; \
2014 \
2015 getVSR(xB(opcode), &xb, env); \
2016 getVSR(xT(opcode), &xt, env); \
2017 helper_reset_fpstatus(env); \
2018 \
2019 for (i = 0; i < nels; i++) { \
2020 float_status tstat = env->fp_status; \
2021 set_float_exception_flags(0, &tstat); \
2022 xt.fld[i] = tp##_sqrt(xb.fld[i], &tstat); \
2023 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
2024 \
2025 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
2026 if (tp##_is_neg(xb.fld[i]) && !tp##_is_zero(xb.fld[i])) { \
2027 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, sfprf); \
2028 } else if (tp##_is_signaling_nan(xb.fld[i])) { \
2029 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
2030 } \
2031 } \
2032 \
cea4e574
TM		 2033 if (r2sp) { \
2034 xt.fld[i] = helper_frsp(env, xt.fld[i]); \
2035 } \
2036 \
d32404fe
TM		 2037 if (sfprf) { \
2038 helper_compute_fprf(env, xt.fld[i], sfprf); \
2039 } \
2040 } \
2041 \
2042 putVSR(xT(opcode), &xt, env); \
2043 helper_float_check_status(env); \
2044}
2045
cea4e574
TM		 2046VSX_SQRT(xssqrtdp, 1, float64, f64, 1, 0)
2047VSX_SQRT(xssqrtsp, 1, float64, f64, 1, 1)
2048VSX_SQRT(xvsqrtdp, 2, float64, f64, 0, 0)
2049VSX_SQRT(xvsqrtsp, 4, float32, f32, 0, 0)
d3f9df8f
TM		 2050
2051/* VSX_RSQRTE - VSX floating point reciprocal square root estimate
2052 * op - instruction mnemonic
2053 * nels - number of elements (1, 2 or 4)
2054 * tp - type (float32 or float64)
2055 * fld - vsr_t field (f32 or f64)
2056 * sfprf - set FPRF
2057 */
968e76bc 2058#define VSX_RSQRTE(op, nels, tp, fld, sfprf, r2sp) \
d3f9df8f
TM		 2059void helper_##op(CPUPPCState *env, uint32_t opcode) \
2060{ \
2061 ppc_vsr_t xt, xb; \
2062 int i; \
2063 \
2064 getVSR(xB(opcode), &xb, env); \
2065 getVSR(xT(opcode), &xt, env); \
2066 helper_reset_fpstatus(env); \
2067 \
2068 for (i = 0; i < nels; i++) { \
2069 float_status tstat = env->fp_status; \
2070 set_float_exception_flags(0, &tstat); \
2071 xt.fld[i] = tp##_sqrt(xb.fld[i], &tstat); \
2072 xt.fld[i] = tp##_div(tp##_one, xt.fld[i], &tstat); \
2073 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
2074 \
2075 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
2076 if (tp##_is_neg(xb.fld[i]) && !tp##_is_zero(xb.fld[i])) { \
2077 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, sfprf); \
2078 } else if (tp##_is_signaling_nan(xb.fld[i])) { \
2079 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
2080 } \
2081 } \
2082 \
968e76bc
TM		 2083 if (r2sp) { \
2084 xt.fld[i] = helper_frsp(env, xt.fld[i]); \
2085 } \
2086 \
d3f9df8f
TM		 2087 if (sfprf) { \
2088 helper_compute_fprf(env, xt.fld[i], sfprf); \
2089 } \
2090 } \
2091 \
2092 putVSR(xT(opcode), &xt, env); \
2093 helper_float_check_status(env); \
2094}
2095
968e76bc
TM		 2096VSX_RSQRTE(xsrsqrtedp, 1, float64, f64, 1, 0)
2097VSX_RSQRTE(xsrsqrtesp, 1, float64, f64, 1, 1)
2098VSX_RSQRTE(xvrsqrtedp, 2, float64, f64, 0, 0)
2099VSX_RSQRTE(xvrsqrtesp, 4, float32, f32, 0, 0)
bc80838f 2100
bc80838f
TM		 2101/* VSX_TDIV - VSX floating point test for divide
2102 * op - instruction mnemonic
2103 * nels - number of elements (1, 2 or 4)
2104 * tp - type (float32 or float64)
2105 * fld - vsr_t field (f32 or f64)
2106 * emin - minimum unbiased exponent
2107 * emax - maximum unbiased exponent
2108 * nbits - number of fraction bits
2109 */
2110#define VSX_TDIV(op, nels, tp, fld, emin, emax, nbits) \
2111void helper_##op(CPUPPCState *env, uint32_t opcode) \
2112{ \
2113 ppc_vsr_t xa, xb; \
2114 int i; \
2115 int fe_flag = 0; \
2116 int fg_flag = 0; \
2117 \
2118 getVSR(xA(opcode), &xa, env); \
2119 getVSR(xB(opcode), &xb, env); \
2120 \
2121 for (i = 0; i < nels; i++) { \
2122 if (unlikely(tp##_is_infinity(xa.fld[i]) || \
2123 tp##_is_infinity(xb.fld[i]) || \
2124 tp##_is_zero(xb.fld[i]))) { \
2125 fe_flag = 1; \
2126 fg_flag = 1; \
2127 } else { \
2128 int e_a = ppc_##tp##_get_unbiased_exp(xa.fld[i]); \
2129 int e_b = ppc_##tp##_get_unbiased_exp(xb.fld[i]); \
2130 \
2131 if (unlikely(tp##_is_any_nan(xa.fld[i]) || \
2132 tp##_is_any_nan(xb.fld[i]))) { \
2133 fe_flag = 1; \
2134 } else if ((e_b <= emin) || (e_b >= (emax-2))) { \
2135 fe_flag = 1; \
2136 } else if (!tp##_is_zero(xa.fld[i]) && \
2137 (((e_a - e_b) >= emax) || \
2138 ((e_a - e_b) <= (emin+1)) || \
2139 (e_a <= (emin+nbits)))) { \
2140 fe_flag = 1; \
2141 } \
2142 \
2143 if (unlikely(tp##_is_zero_or_denormal(xb.fld[i]))) { \
2144 /* XB is not zero because of the above check and */ \
2145 /* so must be denormalized. */ \
2146 fg_flag = 1; \
2147 } \
2148 } \
2149 } \
2150 \
2151 env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
2152}
2153
2154VSX_TDIV(xstdivdp, 1, float64, f64, -1022, 1023, 52)
2155VSX_TDIV(xvtdivdp, 2, float64, f64, -1022, 1023, 52)
2156VSX_TDIV(xvtdivsp, 4, float32, f32, -126, 127, 23)
5cb151ac
TM		 2157
2158/* VSX_TSQRT - VSX floating point test for square root
2159 * op - instruction mnemonic
2160 * nels - number of elements (1, 2 or 4)
2161 * tp - type (float32 or float64)
2162 * fld - vsr_t field (f32 or f64)
2163 * emin - minimum unbiased exponent
2164 * emax - maximum unbiased exponent
2165 * nbits - number of fraction bits
2166 */
2167#define VSX_TSQRT(op, nels, tp, fld, emin, nbits) \
2168void helper_##op(CPUPPCState *env, uint32_t opcode) \
2169{ \
2170 ppc_vsr_t xa, xb; \
2171 int i; \
2172 int fe_flag = 0; \
2173 int fg_flag = 0; \
2174 \
2175 getVSR(xA(opcode), &xa, env); \
2176 getVSR(xB(opcode), &xb, env); \
2177 \
2178 for (i = 0; i < nels; i++) { \
2179 if (unlikely(tp##_is_infinity(xb.fld[i]) || \
2180 tp##_is_zero(xb.fld[i]))) { \
2181 fe_flag = 1; \
2182 fg_flag = 1; \
2183 } else { \
2184 int e_b = ppc_##tp##_get_unbiased_exp(xb.fld[i]); \
2185 \
2186 if (unlikely(tp##_is_any_nan(xb.fld[i]))) { \
2187 fe_flag = 1; \
2188 } else if (unlikely(tp##_is_zero(xb.fld[i]))) { \
2189 fe_flag = 1; \
2190 } else if (unlikely(tp##_is_neg(xb.fld[i]))) { \
2191 fe_flag = 1; \
2192 } else if (!tp##_is_zero(xb.fld[i]) && \
2193 (e_b <= (emin+nbits))) { \
2194 fe_flag = 1; \
2195 } \
2196 \
2197 if (unlikely(tp##_is_zero_or_denormal(xb.fld[i]))) { \
2198 /* XB is not zero because of the above check and */ \
2199 /* therefore must be denormalized. */ \
2200 fg_flag = 1; \
2201 } \
2202 } \
2203 } \
2204 \
2205 env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
2206}
2207
2208VSX_TSQRT(xstsqrtdp, 1, float64, f64, -1022, 52)
2209VSX_TSQRT(xvtsqrtdp, 2, float64, f64, -1022, 52)
2210VSX_TSQRT(xvtsqrtsp, 4, float32, f32, -126, 23)
595c6eef
TM		 2211
2212/* VSX_MADD - VSX floating point muliply/add variations
2213 * op - instruction mnemonic
2214 * nels - number of elements (1, 2 or 4)
2215 * tp - type (float32 or float64)
2216 * fld - vsr_t field (f32 or f64)
2217 * maddflgs - flags for the float*muladd routine that control the
2218 * various forms (madd, msub, nmadd, nmsub)
2219 * afrm - A form (1=A, 0=M)
2220 * sfprf - set FPRF
2221 */
f53f81e0 2222#define VSX_MADD(op, nels, tp, fld, maddflgs, afrm, sfprf, r2sp) \
595c6eef
TM		 2223void helper_##op(CPUPPCState *env, uint32_t opcode) \
2224{ \
2225 ppc_vsr_t xt_in, xa, xb, xt_out; \
2226 ppc_vsr_t *b, *c; \
2227 int i; \
2228 \
2229 if (afrm) { /* AxB + T */ \
2230 b = &xb; \
2231 c = &xt_in; \
2232 } else { /* AxT + B */ \
2233 b = &xt_in; \
2234 c = &xb; \
2235 } \
2236 \
2237 getVSR(xA(opcode), &xa, env); \
2238 getVSR(xB(opcode), &xb, env); \
2239 getVSR(xT(opcode), &xt_in, env); \
2240 \
2241 xt_out = xt_in; \
2242 \
2243 helper_reset_fpstatus(env); \
2244 \
2245 for (i = 0; i < nels; i++) { \
2246 float_status tstat = env->fp_status; \
2247 set_float_exception_flags(0, &tstat); \
f53f81e0
TM		 2248 if (r2sp && (tstat.float_rounding_mode == float_round_nearest_even)) {\
2249 /* Avoid double rounding errors by rounding the intermediate */ \
2250 /* result to odd. */ \
2251 set_float_rounding_mode(float_round_to_zero, &tstat); \
2252 xt_out.fld[i] = tp##_muladd(xa.fld[i], b->fld[i], c->fld[i], \
2253 maddflgs, &tstat); \
2254 xt_out.fld[i] |= (get_float_exception_flags(&tstat) & \
2255 float_flag_inexact) != 0; \
2256 } else { \
2257 xt_out.fld[i] = tp##_muladd(xa.fld[i], b->fld[i], c->fld[i], \
2258 maddflgs, &tstat); \
2259 } \
595c6eef
TM		 2260 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
2261 \
2262 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
2263 if (tp##_is_signaling_nan(xa.fld[i]) || \
2264 tp##_is_signaling_nan(b->fld[i]) || \
2265 tp##_is_signaling_nan(c->fld[i])) { \
2266 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
2267 tstat.float_exception_flags &= ~float_flag_invalid; \
2268 } \
2269 if ((tp##_is_infinity(xa.fld[i]) && tp##_is_zero(b->fld[i])) || \
2270 (tp##_is_zero(xa.fld[i]) && tp##_is_infinity(b->fld[i]))) { \
2271 xt_out.fld[i] = float64_to_##tp(fload_invalid_op_excp(env, \
2272 POWERPC_EXCP_FP_VXIMZ, sfprf), &env->fp_status); \
2273 tstat.float_exception_flags &= ~float_flag_invalid; \
2274 } \
2275 if ((tstat.float_exception_flags & float_flag_invalid) && \
2276 ((tp##_is_infinity(xa.fld[i]) || \
2277 tp##_is_infinity(b->fld[i])) && \
2278 tp##_is_infinity(c->fld[i]))) { \
2279 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, sfprf); \
2280 } \
2281 } \
f53f81e0
TM		 2282 \
2283 if (r2sp) { \
2284 xt_out.fld[i] = helper_frsp(env, xt_out.fld[i]); \
2285 } \
2286 \
595c6eef
TM		 2287 if (sfprf) { \
2288 helper_compute_fprf(env, xt_out.fld[i], sfprf); \
2289 } \
2290 } \
2291 putVSR(xT(opcode), &xt_out, env); \
2292 helper_float_check_status(env); \
2293}
2294
2295#define MADD_FLGS 0
2296#define MSUB_FLGS float_muladd_negate_c
2297#define NMADD_FLGS float_muladd_negate_result
2298#define NMSUB_FLGS (float_muladd_negate_c | float_muladd_negate_result)
2299
f53f81e0
TM		 2300VSX_MADD(xsmaddadp, 1, float64, f64, MADD_FLGS, 1, 1, 0)
2301VSX_MADD(xsmaddmdp, 1, float64, f64, MADD_FLGS, 0, 1, 0)
2302VSX_MADD(xsmsubadp, 1, float64, f64, MSUB_FLGS, 1, 1, 0)
2303VSX_MADD(xsmsubmdp, 1, float64, f64, MSUB_FLGS, 0, 1, 0)
2304VSX_MADD(xsnmaddadp, 1, float64, f64, NMADD_FLGS, 1, 1, 0)
2305VSX_MADD(xsnmaddmdp, 1, float64, f64, NMADD_FLGS, 0, 1, 0)
2306VSX_MADD(xsnmsubadp, 1, float64, f64, NMSUB_FLGS, 1, 1, 0)
2307VSX_MADD(xsnmsubmdp, 1, float64, f64, NMSUB_FLGS, 0, 1, 0)
2308
2309VSX_MADD(xsmaddasp, 1, float64, f64, MADD_FLGS, 1, 1, 1)
2310VSX_MADD(xsmaddmsp, 1, float64, f64, MADD_FLGS, 0, 1, 1)
2311VSX_MADD(xsmsubasp, 1, float64, f64, MSUB_FLGS, 1, 1, 1)
2312VSX_MADD(xsmsubmsp, 1, float64, f64, MSUB_FLGS, 0, 1, 1)
2313VSX_MADD(xsnmaddasp, 1, float64, f64, NMADD_FLGS, 1, 1, 1)
2314VSX_MADD(xsnmaddmsp, 1, float64, f64, NMADD_FLGS, 0, 1, 1)
2315VSX_MADD(xsnmsubasp, 1, float64, f64, NMSUB_FLGS, 1, 1, 1)
2316VSX_MADD(xsnmsubmsp, 1, float64, f64, NMSUB_FLGS, 0, 1, 1)
2317
2318VSX_MADD(xvmaddadp, 2, float64, f64, MADD_FLGS, 1, 0, 0)
2319VSX_MADD(xvmaddmdp, 2, float64, f64, MADD_FLGS, 0, 0, 0)
2320VSX_MADD(xvmsubadp, 2, float64, f64, MSUB_FLGS, 1, 0, 0)
2321VSX_MADD(xvmsubmdp, 2, float64, f64, MSUB_FLGS, 0, 0, 0)
2322VSX_MADD(xvnmaddadp, 2, float64, f64, NMADD_FLGS, 1, 0, 0)
2323VSX_MADD(xvnmaddmdp, 2, float64, f64, NMADD_FLGS, 0, 0, 0)
2324VSX_MADD(xvnmsubadp, 2, float64, f64, NMSUB_FLGS, 1, 0, 0)
2325VSX_MADD(xvnmsubmdp, 2, float64, f64, NMSUB_FLGS, 0, 0, 0)
2326
2327VSX_MADD(xvmaddasp, 4, float32, f32, MADD_FLGS, 1, 0, 0)
2328VSX_MADD(xvmaddmsp, 4, float32, f32, MADD_FLGS, 0, 0, 0)
2329VSX_MADD(xvmsubasp, 4, float32, f32, MSUB_FLGS, 1, 0, 0)
2330VSX_MADD(xvmsubmsp, 4, float32, f32, MSUB_FLGS, 0, 0, 0)
2331VSX_MADD(xvnmaddasp, 4, float32, f32, NMADD_FLGS, 1, 0, 0)
2332VSX_MADD(xvnmaddmsp, 4, float32, f32, NMADD_FLGS, 0, 0, 0)
2333VSX_MADD(xvnmsubasp, 4, float32, f32, NMSUB_FLGS, 1, 0, 0)
2334VSX_MADD(xvnmsubmsp, 4, float32, f32, NMSUB_FLGS, 0, 0, 0)
4f17e9c7
TM		 2335
2336#define VSX_SCALAR_CMP(op, ordered) \
2337void helper_##op(CPUPPCState *env, uint32_t opcode) \
2338{ \
2339 ppc_vsr_t xa, xb; \
2340 uint32_t cc = 0; \
2341 \
2342 getVSR(xA(opcode), &xa, env); \
2343 getVSR(xB(opcode), &xb, env); \
2344 \
2345 if (unlikely(float64_is_any_nan(xa.f64[0]) || \
2346 float64_is_any_nan(xb.f64[0]))) { \
2347 if (float64_is_signaling_nan(xa.f64[0]) || \
2348 float64_is_signaling_nan(xb.f64[0])) { \
2349 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
2350 } \
2351 if (ordered) { \
2352 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0); \
2353 } \
2354 cc = 1; \
2355 } else { \
2356 if (float64_lt(xa.f64[0], xb.f64[0], &env->fp_status)) { \
2357 cc = 8; \
2358 } else if (!float64_le(xa.f64[0], xb.f64[0], &env->fp_status)) { \
2359 cc = 4; \
2360 } else { \
2361 cc = 2; \
2362 } \
2363 } \
2364 \
2365 env->fpscr &= ~(0x0F << FPSCR_FPRF); \
2366 env->fpscr |= cc << FPSCR_FPRF; \
2367 env->crf[BF(opcode)] = cc; \
2368 \
2369 helper_float_check_status(env); \
2370}
2371
2372VSX_SCALAR_CMP(xscmpodp, 1)
2373VSX_SCALAR_CMP(xscmpudp, 0)
959e9c9d 2374
7dff9abe 2375#define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ULL)
959e9c9d
TM		 2376#define float32_snan_to_qnan(x) ((x) | 0x00400000)
2377
2378/* VSX_MAX_MIN - VSX floating point maximum/minimum
2379 * name - instruction mnemonic
2380 * op - operation (max or min)
2381 * nels - number of elements (1, 2 or 4)
2382 * tp - type (float32 or float64)
2383 * fld - vsr_t field (f32 or f64)
2384 */
2385#define VSX_MAX_MIN(name, op, nels, tp, fld) \
2386void helper_##name(CPUPPCState *env, uint32_t opcode) \
2387{ \
2388 ppc_vsr_t xt, xa, xb; \
2389 int i; \
2390 \
2391 getVSR(xA(opcode), &xa, env); \
2392 getVSR(xB(opcode), &xb, env); \
2393 getVSR(xT(opcode), &xt, env); \
2394 \
2395 for (i = 0; i < nels; i++) { \
2396 xt.fld[i] = tp##_##op(xa.fld[i], xb.fld[i], &env->fp_status); \
2397 if (unlikely(tp##_is_signaling_nan(xa.fld[i]) || \
2398 tp##_is_signaling_nan(xb.fld[i]))) { \
2399 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
2400 } \
2401 } \
2402 \
2403 putVSR(xT(opcode), &xt, env); \
2404 helper_float_check_status(env); \
2405}
2406
2407VSX_MAX_MIN(xsmaxdp, maxnum, 1, float64, f64)
2408VSX_MAX_MIN(xvmaxdp, maxnum, 2, float64, f64)
2409VSX_MAX_MIN(xvmaxsp, maxnum, 4, float32, f32)
2410VSX_MAX_MIN(xsmindp, minnum, 1, float64, f64)
2411VSX_MAX_MIN(xvmindp, minnum, 2, float64, f64)
2412VSX_MAX_MIN(xvminsp, minnum, 4, float32, f32)
354a6dec
TM		 2413
2414/* VSX_CMP - VSX floating point compare
2415 * op - instruction mnemonic
2416 * nels - number of elements (1, 2 or 4)
2417 * tp - type (float32 or float64)
2418 * fld - vsr_t field (f32 or f64)
2419 * cmp - comparison operation
2420 * svxvc - set VXVC bit
2421 */
2422#define VSX_CMP(op, nels, tp, fld, cmp, svxvc) \
2423void helper_##op(CPUPPCState *env, uint32_t opcode) \
2424{ \
2425 ppc_vsr_t xt, xa, xb; \
2426 int i; \
2427 int all_true = 1; \
2428 int all_false = 1; \
2429 \
2430 getVSR(xA(opcode), &xa, env); \
2431 getVSR(xB(opcode), &xb, env); \
2432 getVSR(xT(opcode), &xt, env); \
2433 \
2434 for (i = 0; i < nels; i++) { \
2435 if (unlikely(tp##_is_any_nan(xa.fld[i]) || \
2436 tp##_is_any_nan(xb.fld[i]))) { \
2437 if (tp##_is_signaling_nan(xa.fld[i]) || \
2438 tp##_is_signaling_nan(xb.fld[i])) { \
2439 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
2440 } \
2441 if (svxvc) { \
2442 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0); \
2443 } \
2444 xt.fld[i] = 0; \
2445 all_true = 0; \
2446 } else { \
2447 if (tp##_##cmp(xb.fld[i], xa.fld[i], &env->fp_status) == 1) { \
2448 xt.fld[i] = -1; \
2449 all_false = 0; \
2450 } else { \
2451 xt.fld[i] = 0; \
2452 all_true = 0; \
2453 } \
2454 } \
2455 } \
2456 \
2457 putVSR(xT(opcode), &xt, env); \
2458 if ((opcode >> (31-21)) & 1) { \
2459 env->crf[6] = (all_true ? 0x8 : 0) | (all_false ? 0x2 : 0); \
2460 } \
2461 helper_float_check_status(env); \
2462 }
2463
2464VSX_CMP(xvcmpeqdp, 2, float64, f64, eq, 0)
2465VSX_CMP(xvcmpgedp, 2, float64, f64, le, 1)
2466VSX_CMP(xvcmpgtdp, 2, float64, f64, lt, 1)
2467VSX_CMP(xvcmpeqsp, 4, float32, f32, eq, 0)
2468VSX_CMP(xvcmpgesp, 4, float32, f32, le, 1)
2469VSX_CMP(xvcmpgtsp, 4, float32, f32, lt, 1)
ed8ac568
TM		 2470
2471#if defined(HOST_WORDS_BIGENDIAN)
2472#define JOFFSET 0
2473#else
2474#define JOFFSET 1
2475#endif
2476
2477/* VSX_CVT_FP_TO_FP - VSX floating point/floating point conversion
2478 * op - instruction mnemonic
2479 * nels - number of elements (1, 2 or 4)
2480 * stp - source type (float32 or float64)
2481 * ttp - target type (float32 or float64)
2482 * sfld - source vsr_t field
2483 * tfld - target vsr_t field (f32 or f64)
2484 * sfprf - set FPRF
2485 */
2486#define VSX_CVT_FP_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf) \
2487void helper_##op(CPUPPCState *env, uint32_t opcode) \
2488{ \
2489 ppc_vsr_t xt, xb; \
2490 int i; \
2491 \
2492 getVSR(xB(opcode), &xb, env); \
2493 getVSR(xT(opcode), &xt, env); \
2494 \
2495 for (i = 0; i < nels; i++) { \
2496 int j = 2*i + JOFFSET; \
2497 xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status); \
2498 if (unlikely(stp##_is_signaling_nan(xb.sfld))) { \
2499 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
2500 xt.tfld = ttp##_snan_to_qnan(xt.tfld); \
2501 } \
2502 if (sfprf) { \
2503 helper_compute_fprf(env, ttp##_to_float64(xt.tfld, \
2504 &env->fp_status), sfprf); \
2505 } \
2506 } \
2507 \
2508 putVSR(xT(opcode), &xt, env); \
2509 helper_float_check_status(env); \
2510}
2511
2512VSX_CVT_FP_TO_FP(xscvdpsp, 1, float64, float32, f64[i], f32[j], 1)
2513VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, f32[j], f64[i], 1)
2514VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, f64[i], f32[j], 0)
2515VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, f32[j], f64[i], 0)
5177d2ca 2516
7ee19fb9
TM		 2517uint64_t helper_xscvdpspn(CPUPPCState *env, uint64_t xb)
2518{
2519 float_status tstat = env->fp_status;
2520 set_float_exception_flags(0, &tstat);
2521
2522 return (uint64_t)float64_to_float32(xb, &tstat) << 32;
2523}
2524
2525uint64_t helper_xscvspdpn(CPUPPCState *env, uint64_t xb)
2526{
2527 float_status tstat = env->fp_status;
2528 set_float_exception_flags(0, &tstat);
2529
2530 return float32_to_float64(xb >> 32, &tstat);
2531}
2532
5177d2ca
TM		 2533/* VSX_CVT_FP_TO_INT - VSX floating point to integer conversion
2534 * op - instruction mnemonic
2535 * nels - number of elements (1, 2 or 4)
2536 * stp - source type (float32 or float64)
2537 * ttp - target type (int32, uint32, int64 or uint64)
2538 * sfld - source vsr_t field
2539 * tfld - target vsr_t field
2540 * jdef - definition of the j index (i or 2*i)
2541 * rnan - resulting NaN
2542 */
2543#define VSX_CVT_FP_TO_INT(op, nels, stp, ttp, sfld, tfld, jdef, rnan) \
2544void helper_##op(CPUPPCState *env, uint32_t opcode) \
2545{ \
2546 ppc_vsr_t xt, xb; \
2547 int i; \
2548 \
2549 getVSR(xB(opcode), &xb, env); \
2550 getVSR(xT(opcode), &xt, env); \
2551 \
2552 for (i = 0; i < nels; i++) { \
2553 int j = jdef; \
2554 if (unlikely(stp##_is_any_nan(xb.sfld))) { \
2555 if (stp##_is_signaling_nan(xb.sfld)) { \
2556 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
2557 } \
2558 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0); \
2559 xt.tfld = rnan; \
2560 } else { \
2561 xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status); \
2562 if (env->fp_status.float_exception_flags & float_flag_invalid) { \
2563 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0); \
2564 } \
2565 } \
2566 } \
2567 \
2568 putVSR(xT(opcode), &xt, env); \
2569 helper_float_check_status(env); \
2570}
2571
2572VSX_CVT_FP_TO_INT(xscvdpsxds, 1, float64, int64, f64[j], u64[i], i, \
7dff9abe 2573 0x8000000000000000ULL)
5177d2ca 2574VSX_CVT_FP_TO_INT(xscvdpsxws, 1, float64, int32, f64[i], u32[j], \
7dff9abe
TM		 2575 2*i + JOFFSET, 0x80000000U)
2576VSX_CVT_FP_TO_INT(xscvdpuxds, 1, float64, uint64, f64[j], u64[i], i, 0ULL)
5177d2ca 2577VSX_CVT_FP_TO_INT(xscvdpuxws, 1, float64, uint32, f64[i], u32[j], \
7dff9abe 2578 2*i + JOFFSET, 0U)
5177d2ca 2579VSX_CVT_FP_TO_INT(xvcvdpsxds, 2, float64, int64, f64[j], u64[i], i, \
7dff9abe 2580 0x8000000000000000ULL)
5177d2ca 2581VSX_CVT_FP_TO_INT(xvcvdpsxws, 2, float64, int32, f64[i], u32[j], \
7dff9abe
TM		 2582 2*i + JOFFSET, 0x80000000U)
2583VSX_CVT_FP_TO_INT(xvcvdpuxds, 2, float64, uint64, f64[j], u64[i], i, 0ULL)
5177d2ca 2584VSX_CVT_FP_TO_INT(xvcvdpuxws, 2, float64, uint32, f64[i], u32[j], \
7dff9abe 2585 2*i + JOFFSET, 0U)
5177d2ca 2586VSX_CVT_FP_TO_INT(xvcvspsxds, 2, float32, int64, f32[j], u64[i], \
7dff9abe 2587 2*i + JOFFSET, 0x8000000000000000ULL)
5177d2ca 2588VSX_CVT_FP_TO_INT(xvcvspsxws, 4, float32, int32, f32[j], u32[j], i, \
7dff9abe 2589 0x80000000U)
5177d2ca 2590VSX_CVT_FP_TO_INT(xvcvspuxds, 2, float32, uint64, f32[j], u64[i], \
7dff9abe
TM		 2591 2*i + JOFFSET, 0ULL)
2592VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, f32[j], u32[i], i, 0U)
5177d2ca
TM		 2593
2594/* VSX_CVT_INT_TO_FP - VSX integer to floating point conversion
2595 * op - instruction mnemonic
2596 * nels - number of elements (1, 2 or 4)
2597 * stp - source type (int32, uint32, int64 or uint64)
2598 * ttp - target type (float32 or float64)
2599 * sfld - source vsr_t field
2600 * tfld - target vsr_t field
2601 * jdef - definition of the j index (i or 2*i)
2602 * sfprf - set FPRF
2603 */
74698350 2604#define VSX_CVT_INT_TO_FP(op, nels, stp, ttp, sfld, tfld, jdef, sfprf, r2sp) \
5177d2ca
TM		 2605void helper_##op(CPUPPCState *env, uint32_t opcode) \
2606{ \
2607 ppc_vsr_t xt, xb; \
2608 int i; \
2609 \
2610 getVSR(xB(opcode), &xb, env); \
2611 getVSR(xT(opcode), &xt, env); \
2612 \
2613 for (i = 0; i < nels; i++) { \
2614 int j = jdef; \
2615 xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status); \
74698350
TM		 2616 if (r2sp) { \
2617 xt.tfld = helper_frsp(env, xt.tfld); \
2618 } \
5177d2ca
TM		 2619 if (sfprf) { \
2620 helper_compute_fprf(env, xt.tfld, sfprf); \
2621 } \
2622 } \
2623 \
2624 putVSR(xT(opcode), &xt, env); \
2625 helper_float_check_status(env); \
2626}
2627
74698350
TM		 2628VSX_CVT_INT_TO_FP(xscvsxddp, 1, int64, float64, u64[j], f64[i], i, 1, 0)
2629VSX_CVT_INT_TO_FP(xscvuxddp, 1, uint64, float64, u64[j], f64[i], i, 1, 0)
2630VSX_CVT_INT_TO_FP(xscvsxdsp, 1, int64, float64, u64[j], f64[i], i, 1, 1)
2631VSX_CVT_INT_TO_FP(xscvuxdsp, 1, uint64, float64, u64[j], f64[i], i, 1, 1)
2632VSX_CVT_INT_TO_FP(xvcvsxddp, 2, int64, float64, u64[j], f64[i], i, 0, 0)
2633VSX_CVT_INT_TO_FP(xvcvuxddp, 2, uint64, float64, u64[j], f64[i], i, 0, 0)
5177d2ca 2634VSX_CVT_INT_TO_FP(xvcvsxwdp, 2, int32, float64, u32[j], f64[i], \
74698350 2635 2*i + JOFFSET, 0, 0)
5177d2ca 2636VSX_CVT_INT_TO_FP(xvcvuxwdp, 2, uint64, float64, u32[j], f64[i], \
74698350 2637 2*i + JOFFSET, 0, 0)
5177d2ca 2638VSX_CVT_INT_TO_FP(xvcvsxdsp, 2, int64, float32, u64[i], f32[j], \
74698350 2639 2*i + JOFFSET, 0, 0)
5177d2ca 2640VSX_CVT_INT_TO_FP(xvcvuxdsp, 2, uint64, float32, u64[i], f32[j], \
74698350
TM		 2641 2*i + JOFFSET, 0, 0)
2642VSX_CVT_INT_TO_FP(xvcvsxwsp, 4, int32, float32, u32[j], f32[i], i, 0, 0)
2643VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, u32[j], f32[i], i, 0, 0)
88e33d08
TM		 2644
2645/* For "use current rounding mode", define a value that will not be one of
2646 * the existing rounding model enums.
2647 */
2648#define FLOAT_ROUND_CURRENT (float_round_nearest_even + float_round_down + \
2649 float_round_up + float_round_to_zero)
2650
2651/* VSX_ROUND - VSX floating point round
2652 * op - instruction mnemonic
2653 * nels - number of elements (1, 2 or 4)
2654 * tp - type (float32 or float64)
2655 * fld - vsr_t field (f32 or f64)
2656 * rmode - rounding mode
2657 * sfprf - set FPRF
2658 */
2659#define VSX_ROUND(op, nels, tp, fld, rmode, sfprf) \
2660void helper_##op(CPUPPCState *env, uint32_t opcode) \
2661{ \
2662 ppc_vsr_t xt, xb; \
2663 int i; \
2664 getVSR(xB(opcode), &xb, env); \
2665 getVSR(xT(opcode), &xt, env); \
2666 \
2667 if (rmode != FLOAT_ROUND_CURRENT) { \
2668 set_float_rounding_mode(rmode, &env->fp_status); \
2669 } \
2670 \
2671 for (i = 0; i < nels; i++) { \
2672 if (unlikely(tp##_is_signaling_nan(xb.fld[i]))) { \
2673 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
2674 xt.fld[i] = tp##_snan_to_qnan(xb.fld[i]); \
2675 } else { \
2676 xt.fld[i] = tp##_round_to_int(xb.fld[i], &env->fp_status); \
2677 } \
2678 if (sfprf) { \
2679 helper_compute_fprf(env, xt.fld[i], sfprf); \
2680 } \
2681 } \
2682 \
2683 /* If this is not a "use current rounding mode" instruction, \
2684 * then inhibit setting of the XX bit and restore rounding \
2685 * mode from FPSCR */ \
2686 if (rmode != FLOAT_ROUND_CURRENT) { \
2687 fpscr_set_rounding_mode(env); \
2688 env->fp_status.float_exception_flags &= ~float_flag_inexact; \
2689 } \
2690 \
2691 putVSR(xT(opcode), &xt, env); \
2692 helper_float_check_status(env); \
2693}
2694
2695VSX_ROUND(xsrdpi, 1, float64, f64, float_round_nearest_even, 1)
2696VSX_ROUND(xsrdpic, 1, float64, f64, FLOAT_ROUND_CURRENT, 1)
2697VSX_ROUND(xsrdpim, 1, float64, f64, float_round_down, 1)
2698VSX_ROUND(xsrdpip, 1, float64, f64, float_round_up, 1)
2699VSX_ROUND(xsrdpiz, 1, float64, f64, float_round_to_zero, 1)
2700
2701VSX_ROUND(xvrdpi, 2, float64, f64, float_round_nearest_even, 0)
2702VSX_ROUND(xvrdpic, 2, float64, f64, FLOAT_ROUND_CURRENT, 0)
2703VSX_ROUND(xvrdpim, 2, float64, f64, float_round_down, 0)
2704VSX_ROUND(xvrdpip, 2, float64, f64, float_round_up, 0)
2705VSX_ROUND(xvrdpiz, 2, float64, f64, float_round_to_zero, 0)
2706
2707VSX_ROUND(xvrspi, 4, float32, f32, float_round_nearest_even, 0)
2708VSX_ROUND(xvrspic, 4, float32, f32, FLOAT_ROUND_CURRENT, 0)
2709VSX_ROUND(xvrspim, 4, float32, f32, float_round_down, 0)
2710VSX_ROUND(xvrspip, 4, float32, f32, float_round_up, 0)
2711VSX_ROUND(xvrspiz, 4, float32, f32, float_round_to_zero, 0)
3d1140bf
TM		 2712
2713uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb)
2714{
2715 helper_reset_fpstatus(env);
2716
2717 uint64_t xt = helper_frsp(env, xb);
2718
2719 helper_compute_fprf(env, xt, 1);
2720 helper_float_check_status(env);
2721 return xt;
2722}
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