[qemu.git] / hw / arm / fsl-imx31.c

/*
 * Copyright (c) 2013 Jean-Christophe Dubois <[email protected]>
 *
 * i.MX31 SOC emulation.
 *
 * Based on hw/arm/fsl-imx31.c
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "cpu.h"
#include "hw/arm/fsl-imx31.h"
#include "sysemu/sysemu.h"
#include "exec/address-spaces.h"
#include "hw/boards.h"
#include "chardev/char.h"

static void fsl_imx31_init(Object *obj)
{
    FslIMX31State *s = FSL_IMX31(obj);
    int i;

    object_initialize(&s->cpu, sizeof(s->cpu), "arm1136-" TYPE_ARM_CPU);

    sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic),
                          TYPE_IMX_AVIC);

    sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX31_CCM);

    for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
        sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]),
                              TYPE_IMX_SERIAL);
    }

    sysbus_init_child_obj(obj, "gpt", &s->gpt, sizeof(s->gpt), TYPE_IMX31_GPT);

    for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
        sysbus_init_child_obj(obj, "epit[*]", &s->epit[i], sizeof(s->epit[i]),
                              TYPE_IMX_EPIT);
    }

    for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
        sysbus_init_child_obj(obj, "i2c[*]", &s->i2c[i], sizeof(s->i2c[i]),
                              TYPE_IMX_I2C);
    }

    for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
        sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]),
                              TYPE_IMX_GPIO);
    }
}

static void fsl_imx31_realize(DeviceState *dev, Error **errp)
{
    FslIMX31State *s = FSL_IMX31(dev);
    uint16_t i;
    Error *err = NULL;

    object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX31_AVIC_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));

    object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX31_CCM_ADDR);

    /* Initialize all UARTS */
    for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } serial_table[FSL_IMX31_NUM_UARTS] = {
            { FSL_IMX31_UART1_ADDR, FSL_IMX31_UART1_IRQ },
            { FSL_IMX31_UART2_ADDR, FSL_IMX31_UART2_IRQ },
        };

        qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));

        object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }

        sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            serial_table[i].irq));
    }

    s->gpt.ccm = IMX_CCM(&s->ccm);

    object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX31_GPT_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
                       qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX31_GPT_IRQ));

    /* Initialize all EPIT timers */
    for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } epit_table[FSL_IMX31_NUM_EPITS] = {
            { FSL_IMX31_EPIT1_ADDR, FSL_IMX31_EPIT1_IRQ },
            { FSL_IMX31_EPIT2_ADDR, FSL_IMX31_EPIT2_IRQ },
        };

        s->epit[i].ccm = IMX_CCM(&s->ccm);

        object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }

        sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            epit_table[i].irq));
    }

    /* Initialize all I2C */
    for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } i2c_table[FSL_IMX31_NUM_I2CS] = {
            { FSL_IMX31_I2C1_ADDR, FSL_IMX31_I2C1_IRQ },
            { FSL_IMX31_I2C2_ADDR, FSL_IMX31_I2C2_IRQ },
            { FSL_IMX31_I2C3_ADDR, FSL_IMX31_I2C3_IRQ }
        };

        /* Initialize the I2C */
        object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        /* Map I2C memory */
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
        /* Connect I2C IRQ to PIC */
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            i2c_table[i].irq));
    }

    /* Initialize all GPIOs */
    for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } gpio_table[FSL_IMX31_NUM_GPIOS] = {
            { FSL_IMX31_GPIO1_ADDR, FSL_IMX31_GPIO1_IRQ },
            { FSL_IMX31_GPIO2_ADDR, FSL_IMX31_GPIO2_IRQ },
            { FSL_IMX31_GPIO3_ADDR, FSL_IMX31_GPIO3_IRQ }
        };

        object_property_set_bool(OBJECT(&s->gpio[i]), false, "has-edge-sel",
                                 &error_abort);
        object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
        /* Connect GPIO IRQ to PIC */
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            gpio_table[i].irq));
    }

    /* On a real system, the first 16k is a `secure boot rom' */
    memory_region_init_rom(&s->secure_rom, NULL, "imx31.secure_rom",
                           FSL_IMX31_SECURE_ROM_SIZE, &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(get_system_memory(), FSL_IMX31_SECURE_ROM_ADDR,
                                &s->secure_rom);

    /* There is also a 16k ROM */
    memory_region_init_rom(&s->rom, NULL, "imx31.rom",
                           FSL_IMX31_ROM_SIZE, &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(get_system_memory(), FSL_IMX31_ROM_ADDR,
                                &s->rom);

    /* initialize internal RAM (16 KB) */
    memory_region_init_ram(&s->iram, NULL, "imx31.iram", FSL_IMX31_IRAM_SIZE,
                           &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ADDR,
                                &s->iram);

    /* internal RAM (16 KB) is aliased over 256 MB - 16 KB */
    memory_region_init_alias(&s->iram_alias, NULL, "imx31.iram_alias",
                             &s->iram, 0, FSL_IMX31_IRAM_ALIAS_SIZE);
    memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ALIAS_ADDR,
                                &s->iram_alias);
}

static void fsl_imx31_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->realize = fsl_imx31_realize;
    dc->desc = "i.MX31 SOC";
    /*
     * Reason: uses serial_hds in realize and the kzm board does not
     * support multiple CPUs
     */
    dc->user_creatable = false;
}

static const TypeInfo fsl_imx31_type_info = {
    .name = TYPE_FSL_IMX31,
    .parent = TYPE_DEVICE,
    .instance_size = sizeof(FslIMX31State),
    .instance_init = fsl_imx31_init,
    .class_init = fsl_imx31_class_init,
};

static void fsl_imx31_register_types(void)
{
    type_register_static(&fsl_imx31_type_info);
}

type_init(fsl_imx31_register_types)
Commit	Line	Data
558df83d JCD	1	/*
	2	* Copyright (c) 2013 Jean-Christophe Dubois <[email protected]>
	3	*
	4	* i.MX31 SOC emulation.
	5	*
	6	* Based on hw/arm/fsl-imx31.c
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful, but WITHOUT
	14	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	15	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	16	* for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License along
	19	* with this program; if not, see <http://www.gnu.org/licenses/>.
	20	*/
	21
12b16722	22	#include "qemu/osdep.h"
da34e65c	23	#include "qapi/error.h"
4771d756 PB	24	#include "qemu-common.h"
4771d756 PB	25	#include "cpu.h"
558df83d JCD	26	#include "hw/arm/fsl-imx31.h"
	27	#include "sysemu/sysemu.h"
	28	#include "exec/address-spaces.h"
	29	#include "hw/boards.h"
8228e353	30	#include "chardev/char.h"
558df83d JCD	31
	32	static void fsl_imx31_init(Object *obj)
	33	{
	34	FslIMX31State *s = FSL_IMX31(obj);
	35	int i;
	36
	37	object_initialize(&s->cpu, sizeof(s->cpu), "arm1136-" TYPE_ARM_CPU);
	38
aac409c9 TH	39	sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic),
aac409c9 TH	40	TYPE_IMX_AVIC);
558df83d	41
aac409c9	42	sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX31_CCM);
558df83d JCD	43
558df83d JCD	44	for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
aac409c9 TH	45	sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]),
aac409c9 TH	46	TYPE_IMX_SERIAL);
558df83d JCD	47	}
558df83d JCD	48
aac409c9	49	sysbus_init_child_obj(obj, "gpt", &s->gpt, sizeof(s->gpt), TYPE_IMX31_GPT);
558df83d JCD	50
558df83d JCD	51	for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
aac409c9 TH	52	sysbus_init_child_obj(obj, "epit[*]", &s->epit[i], sizeof(s->epit[i]),
aac409c9 TH	53	TYPE_IMX_EPIT);
558df83d	54	}
d4e26d10 JCD	55
d4e26d10 JCD	56	for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
aac409c9 TH	57	sysbus_init_child_obj(obj, "i2c[*]", &s->i2c[i], sizeof(s->i2c[i]),
aac409c9 TH	58	TYPE_IMX_I2C);
d4e26d10	59	}
dde0c4ca JCD	60
dde0c4ca JCD	61	for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
aac409c9 TH	62	sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]),
aac409c9 TH	63	TYPE_IMX_GPIO);
dde0c4ca	64	}
558df83d JCD	65	}
	66
	67	static void fsl_imx31_realize(DeviceState dev, Error *errp)
	68	{
	69	FslIMX31State *s = FSL_IMX31(dev);
	70	uint16_t i;
	71	Error *err = NULL;
	72
	73	object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
	74	if (err) {
	75	error_propagate(errp, err);
	76	return;
	77	}
	78
	79	object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
	80	if (err) {
	81	error_propagate(errp, err);
	82	return;
	83	}
	84	sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX31_AVIC_ADDR);
	85	sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
	86	qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
	87	sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
	88	qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
	89
	90	object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
	91	if (err) {
	92	error_propagate(errp, err);
	93	return;
	94	}
	95	sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX31_CCM_ADDR);
	96
	97	/* Initialize all UARTS */
	98	for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
	99	static const struct {
	100	hwaddr addr;
	101	unsigned int irq;
	102	} serial_table[FSL_IMX31_NUM_UARTS] = {
	103	{ FSL_IMX31_UART1_ADDR, FSL_IMX31_UART1_IRQ },
	104	{ FSL_IMX31_UART2_ADDR, FSL_IMX31_UART2_IRQ },
	105	};
	106
fc38a112	107	qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
558df83d JCD	108
	109	object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
	110	if (err) {
	111	error_propagate(errp, err);
	112	return;
	113	}
	114
	115	sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
	116	sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
	117	qdev_get_gpio_in(DEVICE(&s->avic),
	118	serial_table[i].irq));
	119	}
	120
cb54d868	121	s->gpt.ccm = IMX_CCM(&s->ccm);
558df83d JCD	122
	123	object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err);
	124	if (err) {
	125	error_propagate(errp, err);
	126	return;
	127	}
	128
	129	sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX31_GPT_ADDR);
	130	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
	131	qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX31_GPT_IRQ));
	132
	133	/* Initialize all EPIT timers */
	134	for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
	135	static const struct {
	136	hwaddr addr;
	137	unsigned int irq;
	138	} epit_table[FSL_IMX31_NUM_EPITS] = {
	139	{ FSL_IMX31_EPIT1_ADDR, FSL_IMX31_EPIT1_IRQ },
	140	{ FSL_IMX31_EPIT2_ADDR, FSL_IMX31_EPIT2_IRQ },
	141	};
	142
cb54d868	143	s->epit[i].ccm = IMX_CCM(&s->ccm);
558df83d JCD	144
	145	object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
	146	if (err) {
	147	error_propagate(errp, err);
	148	return;
	149	}
	150
	151	sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
	152	sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
	153	qdev_get_gpio_in(DEVICE(&s->avic),
	154	epit_table[i].irq));
	155	}
d4e26d10 JCD	156
	157	/* Initialize all I2C */
	158	for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
	159	static const struct {
	160	hwaddr addr;
	161	unsigned int irq;
	162	} i2c_table[FSL_IMX31_NUM_I2CS] = {
	163	{ FSL_IMX31_I2C1_ADDR, FSL_IMX31_I2C1_IRQ },
	164	{ FSL_IMX31_I2C2_ADDR, FSL_IMX31_I2C2_IRQ },
	165	{ FSL_IMX31_I2C3_ADDR, FSL_IMX31_I2C3_IRQ }
	166	};
	167
	168	/* Initialize the I2C */
	169	object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
	170	if (err) {
	171	error_propagate(errp, err);
	172	return;
	173	}
	174	/* Map I2C memory */
	175	sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
	176	/* Connect I2C IRQ to PIC */
	177	sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
	178	qdev_get_gpio_in(DEVICE(&s->avic),
	179	i2c_table[i].irq));
	180	}
dde0c4ca JCD	181
	182	/* Initialize all GPIOs */
	183	for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
	184	static const struct {
	185	hwaddr addr;
	186	unsigned int irq;
	187	} gpio_table[FSL_IMX31_NUM_GPIOS] = {
	188	{ FSL_IMX31_GPIO1_ADDR, FSL_IMX31_GPIO1_IRQ },
	189	{ FSL_IMX31_GPIO2_ADDR, FSL_IMX31_GPIO2_IRQ },
	190	{ FSL_IMX31_GPIO3_ADDR, FSL_IMX31_GPIO3_IRQ }
	191	};
	192
	193	object_property_set_bool(OBJECT(&s->gpio[i]), false, "has-edge-sel",
	194	&error_abort);
	195	object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
	196	if (err) {
	197	error_propagate(errp, err);
	198	return;
	199	}
	200	sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
	201	/* Connect GPIO IRQ to PIC */
	202	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
	203	qdev_get_gpio_in(DEVICE(&s->avic),
	204	gpio_table[i].irq));
	205	}
558df83d JCD	206
558df83d JCD	207	/* On a real system, the first 16k is a `secure boot rom' */
eda40cc1	208	memory_region_init_rom(&s->secure_rom, NULL, "imx31.secure_rom",
a7aeb5f7	209	FSL_IMX31_SECURE_ROM_SIZE, &err);
558df83d JCD	210	if (err) {
	211	error_propagate(errp, err);
	212	return;
	213	}
	214	memory_region_add_subregion(get_system_memory(), FSL_IMX31_SECURE_ROM_ADDR,
	215	&s->secure_rom);
	216
	217	/* There is also a 16k ROM */
eda40cc1	218	memory_region_init_rom(&s->rom, NULL, "imx31.rom",
a7aeb5f7	219	FSL_IMX31_ROM_SIZE, &err);
558df83d JCD	220	if (err) {
	221	error_propagate(errp, err);
	222	return;
	223	}
	224	memory_region_add_subregion(get_system_memory(), FSL_IMX31_ROM_ADDR,
	225	&s->rom);
	226
	227	/* initialize internal RAM (16 KB) */
98a99ce0	228	memory_region_init_ram(&s->iram, NULL, "imx31.iram", FSL_IMX31_IRAM_SIZE,
558df83d JCD	229	&err);
	230	if (err) {
	231	error_propagate(errp, err);
	232	return;
	233	}
	234	memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ADDR,
	235	&s->iram);
558df83d JCD	236
	237	/* internal RAM (16 KB) is aliased over 256 MB - 16 KB */
	238	memory_region_init_alias(&s->iram_alias, NULL, "imx31.iram_alias",
	239	&s->iram, 0, FSL_IMX31_IRAM_ALIAS_SIZE);
	240	memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ALIAS_ADDR,
	241	&s->iram_alias);
	242	}
	243
	244	static void fsl_imx31_class_init(ObjectClass oc, void data)
	245	{
	246	DeviceClass *dc = DEVICE_CLASS(oc);
	247
	248	dc->realize = fsl_imx31_realize;
eccfa35e	249	dc->desc = "i.MX31 SOC";
e4e05b7b TH	250	/*
	251	* Reason: uses serial_hds in realize and the kzm board does not
	252	* support multiple CPUs
	253	*/
	254	dc->user_creatable = false;
558df83d JCD	255	}
	256
	257	static const TypeInfo fsl_imx31_type_info = {
	258	.name = TYPE_FSL_IMX31,
	259	.parent = TYPE_DEVICE,
	260	.instance_size = sizeof(FslIMX31State),
	261	.instance_init = fsl_imx31_init,
	262	.class_init = fsl_imx31_class_init,
	263	};
	264
	265	static void fsl_imx31_register_types(void)
	266	{
	267	type_register_static(&fsl_imx31_type_info);
	268	}
	269
	270	type_init(fsl_imx31_register_types)