[qemu.git] / hw / pc_q35.c

/*
 * Q35 chipset based pc system emulator
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 * Copyright (c) 2009, 2010
 *               Isaku Yamahata <yamahata at valinux co jp>
 *               VA Linux Systems Japan K.K.
 * Copyright (C) 2012 Jason Baron <[email protected]>
 *
 * This is based on pc.c, but heavily modified.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "arch_init.h"
#include "smbus.h"
#include "boards.h"
#include "mc146818rtc.h"
#include "xen.h"
#include "kvm.h"
#include "kvm/clock.h"
#include "q35.h"
#include "exec-memory.h"
#include "ich9.h"
#include "hw/ide/pci.h"
#include "hw/ide/ahci.h"
#include "hw/usb.h"

/* ICH9 AHCI has 6 ports */
#define MAX_SATA_PORTS     6

/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
 *    BIOS will read it and start S3 resume at POST Entry */
static void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
{
    ISADevice *s = opaque;

    if (level) {
        rtc_set_memory(s, 0xF, 0xFE);
    }
}

/* PC hardware initialisation */
static void pc_q35_init(QEMUMachineInitArgs *args)
{
    ram_addr_t ram_size = args->ram_size;
    const char *cpu_model = args->cpu_model;
    const char *kernel_filename = args->kernel_filename;
    const char *kernel_cmdline = args->kernel_cmdline;
    const char *initrd_filename = args->initrd_filename;
    const char *boot_device = args->boot_device;
    ram_addr_t below_4g_mem_size, above_4g_mem_size;
    Q35PCIHost *q35_host;
    PCIBus *host_bus;
    PCIDevice *lpc;
    BusState *idebus[MAX_SATA_PORTS];
    ISADevice *rtc_state;
    ISADevice *floppy;
    MemoryRegion *pci_memory;
    MemoryRegion *rom_memory;
    MemoryRegion *ram_memory;
    GSIState *gsi_state;
    ISABus *isa_bus;
    int pci_enabled = 1;
    qemu_irq *cpu_irq;
    qemu_irq *gsi;
    qemu_irq *i8259;
    int i;
    ICH9LPCState *ich9_lpc;
    PCIDevice *ahci;
    qemu_irq *cmos_s3;

    pc_cpus_init(cpu_model);

    kvmclock_create();

    if (ram_size >= 0xb0000000) {
        above_4g_mem_size = ram_size - 0xb0000000;
        below_4g_mem_size = 0xb0000000;
    } else {
        above_4g_mem_size = 0;
        below_4g_mem_size = ram_size;
    }

    /* pci enabled */
    if (pci_enabled) {
        pci_memory = g_new(MemoryRegion, 1);
        memory_region_init(pci_memory, "pci", INT64_MAX);
        rom_memory = pci_memory;
    } else {
        pci_memory = NULL;
        rom_memory = get_system_memory();
    }

    /* allocate ram and load rom/bios */
    if (!xen_enabled()) {
        pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline,
                       initrd_filename, below_4g_mem_size, above_4g_mem_size,
                       rom_memory, &ram_memory);
    }

    /* irq lines */
    gsi_state = g_malloc0(sizeof(*gsi_state));
    if (kvm_irqchip_in_kernel()) {
        kvm_pc_setup_irq_routing(pci_enabled);
        gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
                                 GSI_NUM_PINS);
    } else {
        gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
    }

    /* create pci host bus */
    q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));

    q35_host->mch.ram_memory = ram_memory;
    q35_host->mch.pci_address_space = pci_memory;
    q35_host->mch.system_memory = get_system_memory();
    q35_host->mch.address_space_io = get_system_io();;
    q35_host->mch.below_4g_mem_size = below_4g_mem_size;
    q35_host->mch.above_4g_mem_size = above_4g_mem_size;
    /* pci */
    qdev_init_nofail(DEVICE(q35_host));
    host_bus = q35_host->host.pci.bus;
    /* create ISA bus */
    lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
                                          ICH9_LPC_FUNC), true,
                                          TYPE_ICH9_LPC_DEVICE);
    ich9_lpc = ICH9_LPC_DEVICE(lpc);
    ich9_lpc->pic = gsi;
    ich9_lpc->ioapic = gsi_state->ioapic_irq;
    pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
                 ICH9_LPC_NB_PIRQS);
    isa_bus = ich9_lpc->isa_bus;

    /*end early*/
    isa_bus_irqs(isa_bus, gsi);

    if (kvm_irqchip_in_kernel()) {
        i8259 = kvm_i8259_init(isa_bus);
    } else if (xen_enabled()) {
        i8259 = xen_interrupt_controller_init();
    } else {
        cpu_irq = pc_allocate_cpu_irq();
        i8259 = i8259_init(isa_bus, cpu_irq[0]);
    }

    for (i = 0; i < ISA_NUM_IRQS; i++) {
        gsi_state->i8259_irq[i] = i8259[i];
    }
    if (pci_enabled) {
        ioapic_init_gsi(gsi_state, NULL);
    }

    pc_register_ferr_irq(gsi[13]);

    /* init basic PC hardware */
    pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false);

    /* connect pm stuff to lpc */
    cmos_s3 = qemu_allocate_irqs(pc_cmos_set_s3_resume, rtc_state, 1);
    ich9_lpc_pm_init(lpc, *cmos_s3);

    /* ahci and SATA device, for q35 1 ahci controller is built-in */
    ahci = pci_create_simple_multifunction(host_bus,
                                           PCI_DEVFN(ICH9_SATA1_DEV,
                                                     ICH9_SATA1_FUNC),
                                           true, "ich9-ahci");
    idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
    idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");

    if (usb_enabled(false)) {
        /* Should we create 6 UHCI according to ich9 spec? */
        ehci_create_ich9_with_companions(host_bus, 0x1d);
    }

    /* TODO: Populate SPD eeprom data.  */
    smbus_eeprom_init(ich9_smb_init(host_bus,
                                    PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
                                    0xb100),
                      8, NULL, 0);

    pc_cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device,
                 floppy, idebus[0], idebus[1], rtc_state);

    /* the rest devices to which pci devfn is automatically assigned */
    pc_vga_init(isa_bus, host_bus);
    audio_init(isa_bus, host_bus);
    pc_nic_init(isa_bus, host_bus);
    if (pci_enabled) {
        pc_pci_device_init(host_bus);
    }
}

static QEMUMachine pc_q35_machine = {
    .name = "q35-next",
    .alias = "q35",
    .desc = "Q35 chipset PC",
    .init = pc_q35_init,
    .max_cpus = 255,
};

static void pc_q35_machine_init(void)
{
    qemu_register_machine(&pc_q35_machine);
}

machine_init(pc_q35_machine_init);
Commit	Line	Data
df2d8b3e IY	1	/*
	2	* Q35 chipset based pc system emulator
	3	*
	4	* Copyright (c) 2003-2004 Fabrice Bellard
	5	* Copyright (c) 2009, 2010
	6	* Isaku Yamahata <yamahata at valinux co jp>
	7	* VA Linux Systems Japan K.K.
	8	* Copyright (C) 2012 Jason Baron <[email protected]>
	9	*
	10	* This is based on pc.c, but heavily modified.
	11	*
	12	* Permission is hereby granted, free of charge, to any person obtaining a copy
	13	* of this software and associated documentation files (the "Software"), to deal
	14	* in the Software without restriction, including without limitation the rights
	15	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	16	* copies of the Software, and to permit persons to whom the Software is
	17	* furnished to do so, subject to the following conditions:
	18	*
	19	* The above copyright notice and this permission notice shall be included in
	20	* all copies or substantial portions of the Software.
	21	*
	22	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	23	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	24	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	25	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	26	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	27	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	28	* THE SOFTWARE.
	29	*/
	30	#include "hw.h"
	31	#include "arch_init.h"
	32	#include "smbus.h"
	33	#include "boards.h"
	34	#include "mc146818rtc.h"
	35	#include "xen.h"
	36	#include "kvm.h"
21022c92	37	#include "kvm/clock.h"
df2d8b3e IY	38	#include "q35.h"
	39	#include "exec-memory.h"
	40	#include "ich9.h"
	41	#include "hw/ide/pci.h"
	42	#include "hw/ide/ahci.h"
	43	#include "hw/usb.h"
	44
	45	/* ICH9 AHCI has 6 ports */
	46	#define MAX_SATA_PORTS 6
	47
	48	/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
	49	* BIOS will read it and start S3 resume at POST Entry */
	50	static void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
	51	{
	52	ISADevice *s = opaque;
	53
	54	if (level) {
	55	rtc_set_memory(s, 0xF, 0xFE);
	56	}
	57	}
	58
	59	/* PC hardware initialisation */
	60	static void pc_q35_init(QEMUMachineInitArgs *args)
	61	{
	62	ram_addr_t ram_size = args->ram_size;
	63	const char *cpu_model = args->cpu_model;
	64	const char *kernel_filename = args->kernel_filename;
	65	const char *kernel_cmdline = args->kernel_cmdline;
	66	const char *initrd_filename = args->initrd_filename;
	67	const char *boot_device = args->boot_device;
	68	ram_addr_t below_4g_mem_size, above_4g_mem_size;
	69	Q35PCIHost *q35_host;
	70	PCIBus *host_bus;
	71	PCIDevice *lpc;
	72	BusState *idebus[MAX_SATA_PORTS];
	73	ISADevice *rtc_state;
	74	ISADevice *floppy;
	75	MemoryRegion *pci_memory;
	76	MemoryRegion *rom_memory;
	77	MemoryRegion *ram_memory;
	78	GSIState *gsi_state;
	79	ISABus *isa_bus;
	80	int pci_enabled = 1;
	81	qemu_irq *cpu_irq;
	82	qemu_irq *gsi;
	83	qemu_irq *i8259;
	84	int i;
	85	ICH9LPCState *ich9_lpc;
	86	PCIDevice *ahci;
	87	qemu_irq *cmos_s3;
	88
	89	pc_cpus_init(cpu_model);
	90
21022c92 JK	91	kvmclock_create();
21022c92 JK	92
df2d8b3e IY	93	if (ram_size >= 0xb0000000) {
	94	above_4g_mem_size = ram_size - 0xb0000000;
	95	below_4g_mem_size = 0xb0000000;
	96	} else {
	97	above_4g_mem_size = 0;
	98	below_4g_mem_size = ram_size;
	99	}
	100
	101	/* pci enabled */
	102	if (pci_enabled) {
	103	pci_memory = g_new(MemoryRegion, 1);
	104	memory_region_init(pci_memory, "pci", INT64_MAX);
	105	rom_memory = pci_memory;
	106	} else {
	107	pci_memory = NULL;
	108	rom_memory = get_system_memory();
	109	}
	110
	111	/* allocate ram and load rom/bios */
	112	if (!xen_enabled()) {
	113	pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline,
	114	initrd_filename, below_4g_mem_size, above_4g_mem_size,
	115	rom_memory, &ram_memory);
	116	}
	117
	118	/* irq lines */
	119	gsi_state = g_malloc0(sizeof(*gsi_state));
	120	if (kvm_irqchip_in_kernel()) {
	121	kvm_pc_setup_irq_routing(pci_enabled);
	122	gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
	123	GSI_NUM_PINS);
	124	} else {
	125	gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
	126	}
	127
	128	/* create pci host bus */
	129	q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
	130
	131	q35_host->mch.ram_memory = ram_memory;
	132	q35_host->mch.pci_address_space = pci_memory;
	133	q35_host->mch.system_memory = get_system_memory();
	134	q35_host->mch.address_space_io = get_system_io();;
	135	q35_host->mch.below_4g_mem_size = below_4g_mem_size;
	136	q35_host->mch.above_4g_mem_size = above_4g_mem_size;
	137	/* pci */
	138	qdev_init_nofail(DEVICE(q35_host));
	139	host_bus = q35_host->host.pci.bus;
	140	/* create ISA bus */
	141	lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
	142	ICH9_LPC_FUNC), true,
	143	TYPE_ICH9_LPC_DEVICE);
	144	ich9_lpc = ICH9_LPC_DEVICE(lpc);
	145	ich9_lpc->pic = gsi;
	146	ich9_lpc->ioapic = gsi_state->ioapic_irq;
	147	pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
	148	ICH9_LPC_NB_PIRQS);
	149	isa_bus = ich9_lpc->isa_bus;
	150
	151	/end early/
	152	isa_bus_irqs(isa_bus, gsi);
	153
	154	if (kvm_irqchip_in_kernel()) {
	155	i8259 = kvm_i8259_init(isa_bus);
	156	} else if (xen_enabled()) {
157	i8259 = xen_interrupt_controller_init();
158	} else {
159	cpu_irq = pc_allocate_cpu_irq();
160	i8259 = i8259_init(isa_bus, cpu_irq[0]);
161	}
162
163	for (i = 0; i < ISA_NUM_IRQS; i++) {
164	gsi_state->i8259_irq[i] = i8259[i];
165	}
166	if (pci_enabled) {
167	ioapic_init_gsi(gsi_state, NULL);
168	}
169
170	pc_register_ferr_irq(gsi[13]);
171
172	/* init basic PC hardware */
173	pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false);
174
175	/* connect pm stuff to lpc */
176	cmos_s3 = qemu_allocate_irqs(pc_cmos_set_s3_resume, rtc_state, 1);
177	ich9_lpc_pm_init(lpc, *cmos_s3);
178
179	/* ahci and SATA device, for q35 1 ahci controller is built-in */
180	ahci = pci_create_simple_multifunction(host_bus,
181	PCI_DEVFN(ICH9_SATA1_DEV,
182	ICH9_SATA1_FUNC),
183	true, "ich9-ahci");
184	idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
185	idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
186
187	if (usb_enabled(false)) {
188	/* Should we create 6 UHCI according to ich9 spec? */
189	ehci_create_ich9_with_companions(host_bus, 0x1d);
190	}
191
192	/* TODO: Populate SPD eeprom data. */
193	smbus_eeprom_init(ich9_smb_init(host_bus,
194	PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
195	0xb100),
196	8, NULL, 0);
197
198	pc_cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device,
199	floppy, idebus[0], idebus[1], rtc_state);
200
201	/* the rest devices to which pci devfn is automatically assigned */
202	pc_vga_init(isa_bus, host_bus);
203	audio_init(isa_bus, host_bus);
204	pc_nic_init(isa_bus, host_bus);
205	if (pci_enabled) {
206	pc_pci_device_init(host_bus);
207	}
208	}
209
210	static QEMUMachine pc_q35_machine = {
211	.name = "q35-next",
212	.alias = "q35",
213	.desc = "Q35 chipset PC",
214	.init = pc_q35_init,
215	.max_cpus = 255,
216	};
217
218	static void pc_q35_machine_init(void)
219	{
220	qemu_register_machine(&pc_q35_machine);
221	}
222
223	machine_init(pc_q35_machine_init);