]>
Commit | Line | Data |
---|---|---|
94e1a912 GH |
1 | #define PCNET_IOPORT_SIZE 0x20 |
2 | #define PCNET_PNPMMIO_SIZE 0x20 | |
3 | ||
4 | #define PCNET_LOOPTEST_CRC 1 | |
5 | #define PCNET_LOOPTEST_NOCRC 2 | |
6 | ||
7 | ||
8 | typedef struct PCNetState_st PCNetState; | |
9 | ||
10 | struct PCNetState_st { | |
1fa51482 | 11 | NICState *nic; |
94e1a912 GH |
12 | NICConf conf; |
13 | QEMUTimer *poll_timer; | |
14 | int rap, isr, lnkst; | |
15 | uint32_t rdra, tdra; | |
16 | uint8_t prom[16]; | |
17 | uint16_t csr[128]; | |
18 | uint16_t bcr[32]; | |
19 | uint64_t timer; | |
20 | int mmio_index, xmit_pos; | |
21 | uint8_t buffer[4096]; | |
22 | int tx_busy; | |
23 | qemu_irq irq; | |
24 | void (*phys_mem_read)(void *dma_opaque, target_phys_addr_t addr, | |
25 | uint8_t *buf, int len, int do_bswap); | |
26 | void (*phys_mem_write)(void *dma_opaque, target_phys_addr_t addr, | |
27 | uint8_t *buf, int len, int do_bswap); | |
28 | void *dma_opaque; | |
29 | int looptest; | |
30 | }; | |
31 | ||
32 | void pcnet_h_reset(void *opaque); | |
33 | void pcnet_ioport_writew(void *opaque, uint32_t addr, uint32_t val); | |
34 | uint32_t pcnet_ioport_readw(void *opaque, uint32_t addr); | |
a4c75a21 PB |
35 | void pcnet_ioport_writel(void *opaque, uint32_t addr, uint32_t val); |
36 | uint32_t pcnet_ioport_readl(void *opaque, uint32_t addr); | |
37 | uint32_t pcnet_bcr_readw(PCNetState *s, uint32_t rap); | |
1fa51482 MM |
38 | int pcnet_can_receive(VLANClientState *nc); |
39 | ssize_t pcnet_receive(VLANClientState *nc, const uint8_t *buf, size_t size_); | |
94e1a912 | 40 | void pcnet_common_cleanup(PCNetState *d); |
1fa51482 | 41 | int pcnet_common_init(DeviceState *dev, PCNetState *s, NetClientInfo *info); |
3d865059 | 42 | extern const VMStateDescription vmstate_pcnet; |