[qemu.git] / hw / zaurus.c

/*
 * Copyright (c) 2006-2008 Openedhand Ltd.
 * Written by Andrzej Zaborowski <[email protected]>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 or
 * (at your option) version 3 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */
#include "hw.h"
#include "pxa.h"
#include "sharpsl.h"

#undef REG_FMT
#define REG_FMT			"0x%02lx"

/* SCOOP devices */

struct ScoopInfo {
    qemu_irq handler[16];
    qemu_irq *in;
    uint16_t status;
    uint16_t power;
    uint32_t gpio_level;
    uint32_t gpio_dir;
    uint32_t prev_level;

    uint16_t mcr;
    uint16_t cdr;
    uint16_t ccr;
    uint16_t irr;
    uint16_t imr;
    uint16_t isr;
};

#define SCOOP_MCR	0x00
#define SCOOP_CDR	0x04
#define SCOOP_CSR	0x08
#define SCOOP_CPR	0x0c
#define SCOOP_CCR	0x10
#define SCOOP_IRR_IRM	0x14
#define SCOOP_IMR	0x18
#define SCOOP_ISR	0x1c
#define SCOOP_GPCR	0x20
#define SCOOP_GPWR	0x24
#define SCOOP_GPRR	0x28

static inline void scoop_gpio_handler_update(ScoopInfo *s) {
    uint32_t level, diff;
    int bit;
    level = s->gpio_level & s->gpio_dir;

    for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
        bit = ffs(diff) - 1;
        qemu_set_irq(s->handler[bit], (level >> bit) & 1);
    }

    s->prev_level = level;
}

static uint32_t scoop_readb(void *opaque, target_phys_addr_t addr)
{
    ScoopInfo *s = (ScoopInfo *) opaque;

    switch (addr) {
    case SCOOP_MCR:
        return s->mcr;
    case SCOOP_CDR:
        return s->cdr;
    case SCOOP_CSR:
        return s->status;
    case SCOOP_CPR:
        return s->power;
    case SCOOP_CCR:
        return s->ccr;
    case SCOOP_IRR_IRM:
        return s->irr;
    case SCOOP_IMR:
        return s->imr;
    case SCOOP_ISR:
        return s->isr;
    case SCOOP_GPCR:
        return s->gpio_dir;
    case SCOOP_GPWR:
    case SCOOP_GPRR:
        return s->gpio_level;
    default:
        zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
    }

    return 0;
}

static void scoop_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
{
    ScoopInfo *s = (ScoopInfo *) opaque;
    value &= 0xffff;

    switch (addr) {
    case SCOOP_MCR:
        s->mcr = value;
        break;
    case SCOOP_CDR:
        s->cdr = value;
        break;
    case SCOOP_CPR:
        s->power = value;
        if (value & 0x80)
            s->power |= 0x8040;
        break;
    case SCOOP_CCR:
        s->ccr = value;
        break;
    case SCOOP_IRR_IRM:
        s->irr = value;
        break;
    case SCOOP_IMR:
        s->imr = value;
        break;
    case SCOOP_ISR:
        s->isr = value;
        break;
    case SCOOP_GPCR:
        s->gpio_dir = value;
        scoop_gpio_handler_update(s);
        break;
    case SCOOP_GPWR:
    case SCOOP_GPRR:	/* GPRR is probably R/O in real HW */
        s->gpio_level = value & s->gpio_dir;
        scoop_gpio_handler_update(s);
        break;
    default:
        zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
    }
}

static CPUReadMemoryFunc * const scoop_readfn[] = {
    scoop_readb,
    scoop_readb,
    scoop_readb,
};
static CPUWriteMemoryFunc * const scoop_writefn[] = {
    scoop_writeb,
    scoop_writeb,
    scoop_writeb,
};

void scoop_gpio_set(void *opaque, int line, int level)
{
    ScoopInfo *s = (ScoopInfo *) opaque;

    if (level)
        s->gpio_level |= (1 << line);
    else
        s->gpio_level &= ~(1 << line);
}

qemu_irq *scoop_gpio_in_get(ScoopInfo *s)
{
    return s->in;
}

void scoop_gpio_out_set(ScoopInfo *s, int line,
                qemu_irq handler) {
    if (line >= 16) {
        fprintf(stderr, "No GPIO pin %i\n", line);
        exit(-1);
    }

    s->handler[line] = handler;
}

static void scoop_save(QEMUFile *f, void *opaque)
{
    ScoopInfo *s = (ScoopInfo *) opaque;
    qemu_put_be16s(f, &s->status);
    qemu_put_be16s(f, &s->power);
    qemu_put_be32s(f, &s->gpio_level);
    qemu_put_be32s(f, &s->gpio_dir);
    qemu_put_be32s(f, &s->prev_level);
    qemu_put_be16s(f, &s->mcr);
    qemu_put_be16s(f, &s->cdr);
    qemu_put_be16s(f, &s->ccr);
    qemu_put_be16s(f, &s->irr);
    qemu_put_be16s(f, &s->imr);
    qemu_put_be16s(f, &s->isr);
}

static int scoop_load(QEMUFile *f, void *opaque, int version_id)
{
    uint16_t dummy;
    ScoopInfo *s = (ScoopInfo *) opaque;
    qemu_get_be16s(f, &s->status);
    qemu_get_be16s(f, &s->power);
    qemu_get_be32s(f, &s->gpio_level);
    qemu_get_be32s(f, &s->gpio_dir);
    qemu_get_be32s(f, &s->prev_level);
    qemu_get_be16s(f, &s->mcr);
    qemu_get_be16s(f, &s->cdr);
    qemu_get_be16s(f, &s->ccr);
    qemu_get_be16s(f, &s->irr);
    qemu_get_be16s(f, &s->imr);
    qemu_get_be16s(f, &s->isr);
    if (version_id < 1)
	    qemu_get_be16s(f, &dummy);

    return 0;
}

ScoopInfo *scoop_init(PXA2xxState *cpu,
		int instance,
		target_phys_addr_t target_base) {
    int iomemtype;
    ScoopInfo *s;

    s = (ScoopInfo *)
            qemu_mallocz(sizeof(ScoopInfo));
    memset(s, 0, sizeof(ScoopInfo));

    s->status = 0x02;
    s->in = qemu_allocate_irqs(scoop_gpio_set, s, 16);
    iomemtype = cpu_register_io_memory(scoop_readfn,
                    scoop_writefn, s);
    cpu_register_physical_memory(target_base, 0x1000, iomemtype);
    register_savevm("scoop", instance, 1, scoop_save, scoop_load, s);

    return s;
}

/* Write the bootloader parameters memory area.  */

#define MAGIC_CHG(a, b, c, d)	((d << 24) | (c << 16) | (b << 8) | a)

static struct __attribute__ ((__packed__)) sl_param_info {
    uint32_t comadj_keyword;
    int32_t comadj;

    uint32_t uuid_keyword;
    char uuid[16];

    uint32_t touch_keyword;
    int32_t touch_xp;
    int32_t touch_yp;
    int32_t touch_xd;
    int32_t touch_yd;

    uint32_t adadj_keyword;
    int32_t adadj;

    uint32_t phad_keyword;
    int32_t phadadj;
} zaurus_bootparam = {
    .comadj_keyword	= MAGIC_CHG('C', 'M', 'A', 'D'),
    .comadj		= 125,
    .uuid_keyword	= MAGIC_CHG('U', 'U', 'I', 'D'),
    .uuid		= { -1 },
    .touch_keyword	= MAGIC_CHG('T', 'U', 'C', 'H'),
    .touch_xp		= -1,
    .adadj_keyword	= MAGIC_CHG('B', 'V', 'A', 'D'),
    .adadj		= -1,
    .phad_keyword	= MAGIC_CHG('P', 'H', 'A', 'D'),
    .phadadj		= 0x01,
};

void sl_bootparam_write(target_phys_addr_t ptr)
{
    cpu_physical_memory_write(ptr, (void *)&zaurus_bootparam,
                              sizeof(struct sl_param_info));
}
Commit	Line	Data
e33d8cdb AZ	1	/*
	2	* Copyright (c) 2006-2008 Openedhand Ltd.
	3	* Written by Andrzej Zaborowski <[email protected]>
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License as
	7	* published by the Free Software Foundation; either version 2 or
	8	* (at your option) version 3 of the License.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
fad6cb1a	15	* You should have received a copy of the GNU General Public License along
8167ee88	16	* with this program; if not, see <http://www.gnu.org/licenses/>.
e33d8cdb AZ	17	*/
	18	#include "hw.h"
	19	#include "pxa.h"
	20	#include "sharpsl.h"
	21
e33d8cdb	22	#undef REG_FMT
e33d8cdb	23	#define REG_FMT "0x%02lx"
e33d8cdb AZ	24
	25	/* SCOOP devices */
	26
bc24a225	27	struct ScoopInfo {
e33d8cdb AZ	28	qemu_irq handler[16];
	29	qemu_irq *in;
	30	uint16_t status;
	31	uint16_t power;
	32	uint32_t gpio_level;
	33	uint32_t gpio_dir;
	34	uint32_t prev_level;
	35
	36	uint16_t mcr;
	37	uint16_t cdr;
	38	uint16_t ccr;
	39	uint16_t irr;
	40	uint16_t imr;
	41	uint16_t isr;
e33d8cdb AZ	42	};
	43
	44	#define SCOOP_MCR 0x00
	45	#define SCOOP_CDR 0x04
	46	#define SCOOP_CSR 0x08
	47	#define SCOOP_CPR 0x0c
	48	#define SCOOP_CCR 0x10
	49	#define SCOOP_IRR_IRM 0x14
	50	#define SCOOP_IMR 0x18
	51	#define SCOOP_ISR 0x1c
	52	#define SCOOP_GPCR 0x20
	53	#define SCOOP_GPWR 0x24
	54	#define SCOOP_GPRR 0x28
	55
bc24a225	56	static inline void scoop_gpio_handler_update(ScoopInfo *s) {
e33d8cdb AZ	57	uint32_t level, diff;
	58	int bit;
	59	level = s->gpio_level & s->gpio_dir;
	60
	61	for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
	62	bit = ffs(diff) - 1;
	63	qemu_set_irq(s->handler[bit], (level >> bit) & 1);
	64	}
	65
	66	s->prev_level = level;
	67	}
	68
c227f099	69	static uint32_t scoop_readb(void *opaque, target_phys_addr_t addr)
e33d8cdb	70	{
bc24a225	71	ScoopInfo s = (ScoopInfo ) opaque;
e33d8cdb AZ	72
	73	switch (addr) {
	74	case SCOOP_MCR:
	75	return s->mcr;
	76	case SCOOP_CDR:
	77	return s->cdr;
	78	case SCOOP_CSR:
	79	return s->status;
	80	case SCOOP_CPR:
	81	return s->power;
	82	case SCOOP_CCR:
	83	return s->ccr;
	84	case SCOOP_IRR_IRM:
	85	return s->irr;
	86	case SCOOP_IMR:
	87	return s->imr;
	88	case SCOOP_ISR:
	89	return s->isr;
	90	case SCOOP_GPCR:
	91	return s->gpio_dir;
	92	case SCOOP_GPWR:
e33d8cdb	93	case SCOOP_GPRR:
1f163b14	94	return s->gpio_level;
e33d8cdb	95	default:
a8b7063b	96	zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
e33d8cdb AZ	97	}
	98
	99	return 0;
	100	}
	101
c227f099	102	static void scoop_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
e33d8cdb	103	{
bc24a225	104	ScoopInfo s = (ScoopInfo ) opaque;
e33d8cdb AZ	105	value &= 0xffff;
	106
	107	switch (addr) {
	108	case SCOOP_MCR:
	109	s->mcr = value;
	110	break;
	111	case SCOOP_CDR:
	112	s->cdr = value;
	113	break;
	114	case SCOOP_CPR:
	115	s->power = value;
	116	if (value & 0x80)
	117	s->power \|= 0x8040;
	118	break;
	119	case SCOOP_CCR:
	120	s->ccr = value;
	121	break;
	122	case SCOOP_IRR_IRM:
	123	s->irr = value;
	124	break;
	125	case SCOOP_IMR:
	126	s->imr = value;
	127	break;
	128	case SCOOP_ISR:
	129	s->isr = value;
	130	break;
	131	case SCOOP_GPCR:
	132	s->gpio_dir = value;
	133	scoop_gpio_handler_update(s);
	134	break;
	135	case SCOOP_GPWR:
1f163b14	136	case SCOOP_GPRR: /* GPRR is probably R/O in real HW */
e33d8cdb AZ	137	s->gpio_level = value & s->gpio_dir;
	138	scoop_gpio_handler_update(s);
	139	break;
e33d8cdb	140	default:
a8b7063b	141	zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
e33d8cdb AZ	142	}
	143	}
	144
d60efc6b	145	static CPUReadMemoryFunc * const scoop_readfn[] = {
e33d8cdb AZ	146	scoop_readb,
	147	scoop_readb,
	148	scoop_readb,
	149	};
d60efc6b	150	static CPUWriteMemoryFunc * const scoop_writefn[] = {
e33d8cdb AZ	151	scoop_writeb,
	152	scoop_writeb,
	153	scoop_writeb,
	154	};
	155
	156	void scoop_gpio_set(void *opaque, int line, int level)
	157	{
8d30b794	158	ScoopInfo s = (ScoopInfo ) opaque;
e33d8cdb AZ	159
	160	if (level)
	161	s->gpio_level \|= (1 << line);
	162	else
	163	s->gpio_level &= ~(1 << line);
	164	}
	165
bc24a225	166	qemu_irq scoop_gpio_in_get(ScoopInfo s)
e33d8cdb AZ	167	{
	168	return s->in;
	169	}
	170
bc24a225	171	void scoop_gpio_out_set(ScoopInfo *s, int line,
e33d8cdb AZ	172	qemu_irq handler) {
	173	if (line >= 16) {
	174	fprintf(stderr, "No GPIO pin %i\n", line);
	175	exit(-1);
	176	}
	177
	178	s->handler[line] = handler;
	179	}
	180
	181	static void scoop_save(QEMUFile f, void opaque)
	182	{
bc24a225	183	ScoopInfo s = (ScoopInfo ) opaque;
e33d8cdb AZ	184	qemu_put_be16s(f, &s->status);
	185	qemu_put_be16s(f, &s->power);
	186	qemu_put_be32s(f, &s->gpio_level);
	187	qemu_put_be32s(f, &s->gpio_dir);
	188	qemu_put_be32s(f, &s->prev_level);
	189	qemu_put_be16s(f, &s->mcr);
	190	qemu_put_be16s(f, &s->cdr);
	191	qemu_put_be16s(f, &s->ccr);
	192	qemu_put_be16s(f, &s->irr);
	193	qemu_put_be16s(f, &s->imr);
	194	qemu_put_be16s(f, &s->isr);
e33d8cdb AZ	195	}
	196
	197	static int scoop_load(QEMUFile f, void opaque, int version_id)
	198	{
1f163b14	199	uint16_t dummy;
bc24a225	200	ScoopInfo s = (ScoopInfo ) opaque;
e33d8cdb AZ	201	qemu_get_be16s(f, &s->status);
	202	qemu_get_be16s(f, &s->power);
	203	qemu_get_be32s(f, &s->gpio_level);
	204	qemu_get_be32s(f, &s->gpio_dir);
	205	qemu_get_be32s(f, &s->prev_level);
	206	qemu_get_be16s(f, &s->mcr);
	207	qemu_get_be16s(f, &s->cdr);
	208	qemu_get_be16s(f, &s->ccr);
	209	qemu_get_be16s(f, &s->irr);
	210	qemu_get_be16s(f, &s->imr);
	211	qemu_get_be16s(f, &s->isr);
1f163b14 AZ	212	if (version_id < 1)
1f163b14 AZ	213	qemu_get_be16s(f, &dummy);
e33d8cdb AZ	214
	215	return 0;
	216	}
	217
bc24a225	218	ScoopInfo scoop_init(PXA2xxState cpu,
e33d8cdb	219	int instance,
c227f099	220	target_phys_addr_t target_base) {
e33d8cdb	221	int iomemtype;
bc24a225	222	ScoopInfo *s;
e33d8cdb	223
bc24a225 PB	224	s = (ScoopInfo *)
	225	qemu_mallocz(sizeof(ScoopInfo));
	226	memset(s, 0, sizeof(ScoopInfo));
e33d8cdb	227
e33d8cdb AZ	228	s->status = 0x02;
e33d8cdb AZ	229	s->in = qemu_allocate_irqs(scoop_gpio_set, s, 16);
1eed09cb	230	iomemtype = cpu_register_io_memory(scoop_readfn,
e33d8cdb	231	scoop_writefn, s);
8da3ff18	232	cpu_register_physical_memory(target_base, 0x1000, iomemtype);
1f163b14	233	register_savevm("scoop", instance, 1, scoop_save, scoop_load, s);
e33d8cdb AZ	234
	235	return s;
	236	}
	237
	238	/* Write the bootloader parameters memory area. */
	239
	240	#define MAGIC_CHG(a, b, c, d) ((d << 24) \| (c << 16) \| (b << 8) \| a)
	241
b1d8e52e	242	static struct __attribute__ ((__packed__)) sl_param_info {
e33d8cdb AZ	243	uint32_t comadj_keyword;
	244	int32_t comadj;
	245
	246	uint32_t uuid_keyword;
	247	char uuid[16];
	248
	249	uint32_t touch_keyword;
	250	int32_t touch_xp;
	251	int32_t touch_yp;
	252	int32_t touch_xd;
	253	int32_t touch_yd;
	254
	255	uint32_t adadj_keyword;
	256	int32_t adadj;
	257
	258	uint32_t phad_keyword;
	259	int32_t phadadj;
	260	} zaurus_bootparam = {
	261	.comadj_keyword = MAGIC_CHG('C', 'M', 'A', 'D'),
	262	.comadj = 125,
	263	.uuid_keyword = MAGIC_CHG('U', 'U', 'I', 'D'),
	264	.uuid = { -1 },
	265	.touch_keyword = MAGIC_CHG('T', 'U', 'C', 'H'),
	266	.touch_xp = -1,
	267	.adadj_keyword = MAGIC_CHG('B', 'V', 'A', 'D'),
	268	.adadj = -1,
	269	.phad_keyword = MAGIC_CHG('P', 'H', 'A', 'D'),
	270	.phadadj = 0x01,
	271	};
	272
c227f099	273	void sl_bootparam_write(target_phys_addr_t ptr)
e33d8cdb	274	{
f78630ab PB	275	cpu_physical_memory_write(ptr, (void *)&zaurus_bootparam,
f78630ab PB	276	sizeof(struct sl_param_info));
e33d8cdb	277	}