[qemu.git] / target-sparc / win_helper.c

/*
 * Helpers for CWP and PSTATE handling
 *
 *  Copyright (c) 2003-2005 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/helper-proto.h"
#include "trace.h"

static inline void memcpy32(target_ulong *dst, const target_ulong *src)
{
    dst[0] = src[0];
    dst[1] = src[1];
    dst[2] = src[2];
    dst[3] = src[3];
    dst[4] = src[4];
    dst[5] = src[5];
    dst[6] = src[6];
    dst[7] = src[7];
}

void cpu_set_cwp(CPUSPARCState *env, int new_cwp)
{
    /* put the modified wrap registers at their proper location */
    if (env->cwp == env->nwindows - 1) {
        memcpy32(env->regbase, env->regbase + env->nwindows * 16);
    }
    env->cwp = new_cwp;

    /* put the wrap registers at their temporary location */
    if (new_cwp == env->nwindows - 1) {
        memcpy32(env->regbase + env->nwindows * 16, env->regbase);
    }
    env->regwptr = env->regbase + (new_cwp * 16);
}

target_ulong cpu_get_psr(CPUSPARCState *env)
{
    helper_compute_psr(env);

#if !defined(TARGET_SPARC64)
    return env->version | (env->psr & PSR_ICC) |
        (env->psref ? PSR_EF : 0) |
        (env->psrpil << 8) |
        (env->psrs ? PSR_S : 0) |
        (env->psrps ? PSR_PS : 0) |
        (env->psret ? PSR_ET : 0) | env->cwp;
#else
    return env->psr & PSR_ICC;
#endif
}

void cpu_put_psr_raw(CPUSPARCState *env, target_ulong val)
{
    env->psr = val & PSR_ICC;
#if !defined(TARGET_SPARC64)
    env->psref = (val & PSR_EF) ? 1 : 0;
    env->psrpil = (val & PSR_PIL) >> 8;
    env->psrs = (val & PSR_S) ? 1 : 0;
    env->psrps = (val & PSR_PS) ? 1 : 0;
    env->psret = (val & PSR_ET) ? 1 : 0;
#endif
    env->cc_op = CC_OP_FLAGS;
#if !defined(TARGET_SPARC64)
    cpu_set_cwp(env, val & PSR_CWP);
#endif
}

void cpu_put_psr(CPUSPARCState *env, target_ulong val)
{
    cpu_put_psr_raw(env, val);
#if ((!defined(TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
    cpu_check_irqs(env);
#endif
}

int cpu_cwp_inc(CPUSPARCState *env, int cwp)
{
    if (unlikely(cwp >= env->nwindows)) {
        cwp -= env->nwindows;
    }
    return cwp;
}

int cpu_cwp_dec(CPUSPARCState *env, int cwp)
{
    if (unlikely(cwp < 0)) {
        cwp += env->nwindows;
    }
    return cwp;
}

#ifndef TARGET_SPARC64
void helper_rett(CPUSPARCState *env)
{
    unsigned int cwp;

    if (env->psret == 1) {
        helper_raise_exception(env, TT_ILL_INSN);
    }

    env->psret = 1;
    cwp = cpu_cwp_inc(env, env->cwp + 1) ;
    if (env->wim & (1 << cwp)) {
        helper_raise_exception(env, TT_WIN_UNF);
    }
    cpu_set_cwp(env, cwp);
    env->psrs = env->psrps;
}

/* XXX: use another pointer for %iN registers to avoid slow wrapping
   handling ? */
void helper_save(CPUSPARCState *env)
{
    uint32_t cwp;

    cwp = cpu_cwp_dec(env, env->cwp - 1);
    if (env->wim & (1 << cwp)) {
        helper_raise_exception(env, TT_WIN_OVF);
    }
    cpu_set_cwp(env, cwp);
}

void helper_restore(CPUSPARCState *env)
{
    uint32_t cwp;

    cwp = cpu_cwp_inc(env, env->cwp + 1);
    if (env->wim & (1 << cwp)) {
        helper_raise_exception(env, TT_WIN_UNF);
    }
    cpu_set_cwp(env, cwp);
}

void helper_wrpsr(CPUSPARCState *env, target_ulong new_psr)
{
    if ((new_psr & PSR_CWP) >= env->nwindows) {
        helper_raise_exception(env, TT_ILL_INSN);
    } else {
        cpu_put_psr(env, new_psr);
    }
}

target_ulong helper_rdpsr(CPUSPARCState *env)
{
    return cpu_get_psr(env);
}

#else
/* XXX: use another pointer for %iN registers to avoid slow wrapping
   handling ? */
void helper_save(CPUSPARCState *env)
{
    uint32_t cwp;

    cwp = cpu_cwp_dec(env, env->cwp - 1);
    if (env->cansave == 0) {
        helper_raise_exception(env, TT_SPILL | (env->otherwin != 0 ?
                                                (TT_WOTHER |
                                                 ((env->wstate & 0x38) >> 1)) :
                                                ((env->wstate & 0x7) << 2)));
    } else {
        if (env->cleanwin - env->canrestore == 0) {
            /* XXX Clean windows without trap */
            helper_raise_exception(env, TT_CLRWIN);
        } else {
            env->cansave--;
            env->canrestore++;
            cpu_set_cwp(env, cwp);
        }
    }
}

void helper_restore(CPUSPARCState *env)
{
    uint32_t cwp;

    cwp = cpu_cwp_inc(env, env->cwp + 1);
    if (env->canrestore == 0) {
        helper_raise_exception(env, TT_FILL | (env->otherwin != 0 ?
                                               (TT_WOTHER |
                                                ((env->wstate & 0x38) >> 1)) :
                                               ((env->wstate & 0x7) << 2)));
    } else {
        env->cansave++;
        env->canrestore--;
        cpu_set_cwp(env, cwp);
    }
}

void helper_flushw(CPUSPARCState *env)
{
    if (env->cansave != env->nwindows - 2) {
        helper_raise_exception(env, TT_SPILL | (env->otherwin != 0 ?
                                                (TT_WOTHER |
                                                 ((env->wstate & 0x38) >> 1)) :
                                                ((env->wstate & 0x7) << 2)));
    }
}

void helper_saved(CPUSPARCState *env)
{
    env->cansave++;
    if (env->otherwin == 0) {
        env->canrestore--;
    } else {
        env->otherwin--;
    }
}

void helper_restored(CPUSPARCState *env)
{
    env->canrestore++;
    if (env->cleanwin < env->nwindows - 1) {
        env->cleanwin++;
    }
    if (env->otherwin == 0) {
        env->cansave--;
    } else {
        env->otherwin--;
    }
}

target_ulong cpu_get_ccr(CPUSPARCState *env)
{
    target_ulong psr;

    psr = cpu_get_psr(env);

    return ((env->xcc >> 20) << 4) | ((psr & PSR_ICC) >> 20);
}

void cpu_put_ccr(CPUSPARCState *env, target_ulong val)
{
    env->xcc = (val >> 4) << 20;
    env->psr = (val & 0xf) << 20;
    CC_OP = CC_OP_FLAGS;
}

target_ulong cpu_get_cwp64(CPUSPARCState *env)
{
    return env->nwindows - 1 - env->cwp;
}

void cpu_put_cwp64(CPUSPARCState *env, int cwp)
{
    if (unlikely(cwp >= env->nwindows || cwp < 0)) {
        cwp %= env->nwindows;
    }
    cpu_set_cwp(env, env->nwindows - 1 - cwp);
}

target_ulong helper_rdccr(CPUSPARCState *env)
{
    return cpu_get_ccr(env);
}

void helper_wrccr(CPUSPARCState *env, target_ulong new_ccr)
{
    cpu_put_ccr(env, new_ccr);
}

/* CWP handling is reversed in V9, but we still use the V8 register
   order. */
target_ulong helper_rdcwp(CPUSPARCState *env)
{
    return cpu_get_cwp64(env);
}

void helper_wrcwp(CPUSPARCState *env, target_ulong new_cwp)
{
    cpu_put_cwp64(env, new_cwp);
}

static inline uint64_t *get_gregset(CPUSPARCState *env, uint32_t pstate)
{
    switch (pstate) {
    default:
        trace_win_helper_gregset_error(pstate);
        /* pass through to normal set of global registers */
    case 0:
        return env->bgregs;
    case PS_AG:
        return env->agregs;
    case PS_MG:
        return env->mgregs;
    case PS_IG:
        return env->igregs;
    }
}

void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
{
    uint32_t pstate_regs, new_pstate_regs;
    uint64_t *src, *dst;

    if (env->def->features & CPU_FEATURE_GL) {
        /* PS_AG is not implemented in this case */
        new_pstate &= ~PS_AG;
    }

    pstate_regs = env->pstate & 0xc01;
    new_pstate_regs = new_pstate & 0xc01;

    if (new_pstate_regs != pstate_regs) {
        trace_win_helper_switch_pstate(pstate_regs, new_pstate_regs);

        /* Switch global register bank */
        src = get_gregset(env, new_pstate_regs);
        dst = get_gregset(env, pstate_regs);
        memcpy32(dst, env->gregs);
        memcpy32(env->gregs, src);
    } else {
        trace_win_helper_no_switch_pstate(new_pstate_regs);
    }
    env->pstate = new_pstate;
}

void helper_wrpstate(CPUSPARCState *env, target_ulong new_state)
{
    cpu_change_pstate(env, new_state & 0xf3f);

#if !defined(CONFIG_USER_ONLY)
    if (cpu_interrupts_enabled(env)) {
        cpu_check_irqs(env);
    }
#endif
}

void helper_wrpil(CPUSPARCState *env, target_ulong new_pil)
{
#if !defined(CONFIG_USER_ONLY)
    trace_win_helper_wrpil(env->psrpil, (uint32_t)new_pil);

    env->psrpil = new_pil;

    if (cpu_interrupts_enabled(env)) {
        cpu_check_irqs(env);
    }
#endif
}

void helper_done(CPUSPARCState *env)
{
    trap_state *tsptr = cpu_tsptr(env);

    env->pc = tsptr->tnpc;
    env->npc = tsptr->tnpc + 4;
    cpu_put_ccr(env, tsptr->tstate >> 32);
    env->asi = (tsptr->tstate >> 24) & 0xff;
    cpu_change_pstate(env, (tsptr->tstate >> 8) & 0xf3f);
    cpu_put_cwp64(env, tsptr->tstate & 0xff);
    env->tl--;

    trace_win_helper_done(env->tl);

#if !defined(CONFIG_USER_ONLY)
    if (cpu_interrupts_enabled(env)) {
        cpu_check_irqs(env);
    }
#endif
}

void helper_retry(CPUSPARCState *env)
{
    trap_state *tsptr = cpu_tsptr(env);

    env->pc = tsptr->tpc;
    env->npc = tsptr->tnpc;
    cpu_put_ccr(env, tsptr->tstate >> 32);
    env->asi = (tsptr->tstate >> 24) & 0xff;
    cpu_change_pstate(env, (tsptr->tstate >> 8) & 0xf3f);
    cpu_put_cwp64(env, tsptr->tstate & 0xff);
    env->tl--;

    trace_win_helper_retry(env->tl);

#if !defined(CONFIG_USER_ONLY)
    if (cpu_interrupts_enabled(env)) {
        cpu_check_irqs(env);
    }
#endif
}
#endif
Commit	Line	Data
070af384 BS	1	/*
	2	* Helpers for CWP and PSTATE handling
	3	*
	4	* Copyright (c) 2003-2005 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
db5ebe5f	20	#include "qemu/osdep.h"
070af384	21	#include "cpu.h"
2ef6175a	22	#include "exec/helper-proto.h"
870be6ad	23	#include "trace.h"
070af384 BS	24
	25	static inline void memcpy32(target_ulong dst, const target_ulong src)
	26	{
	27	dst[0] = src[0];
	28	dst[1] = src[1];
	29	dst[2] = src[2];
	30	dst[3] = src[3];
	31	dst[4] = src[4];
	32	dst[5] = src[5];
	33	dst[6] = src[6];
	34	dst[7] = src[7];
	35	}
	36
c5f9864e	37	void cpu_set_cwp(CPUSPARCState *env, int new_cwp)
070af384 BS	38	{
	39	/* put the modified wrap registers at their proper location */
	40	if (env->cwp == env->nwindows - 1) {
	41	memcpy32(env->regbase, env->regbase + env->nwindows * 16);
	42	}
	43	env->cwp = new_cwp;
	44
	45	/* put the wrap registers at their temporary location */
	46	if (new_cwp == env->nwindows - 1) {
	47	memcpy32(env->regbase + env->nwindows * 16, env->regbase);
	48	}
	49	env->regwptr = env->regbase + (new_cwp * 16);
	50	}
	51
c5f9864e	52	target_ulong cpu_get_psr(CPUSPARCState *env)
070af384 BS	53	{
	54	helper_compute_psr(env);
	55
	56	#if !defined(TARGET_SPARC64)
	57	return env->version \| (env->psr & PSR_ICC) \|
	58	(env->psref ? PSR_EF : 0) \|
	59	(env->psrpil << 8) \|
	60	(env->psrs ? PSR_S : 0) \|
	61	(env->psrps ? PSR_PS : 0) \|
	62	(env->psret ? PSR_ET : 0) \| env->cwp;
	63	#else
	64	return env->psr & PSR_ICC;
	65	#endif
	66	}
	67
4552a09d	68	void cpu_put_psr_raw(CPUSPARCState *env, target_ulong val)
070af384 BS	69	{
	70	env->psr = val & PSR_ICC;
	71	#if !defined(TARGET_SPARC64)
	72	env->psref = (val & PSR_EF) ? 1 : 0;
	73	env->psrpil = (val & PSR_PIL) >> 8;
070af384 BS	74	env->psrs = (val & PSR_S) ? 1 : 0;
	75	env->psrps = (val & PSR_PS) ? 1 : 0;
	76	env->psret = (val & PSR_ET) ? 1 : 0;
070af384 BS	77	#endif
070af384 BS	78	env->cc_op = CC_OP_FLAGS;
4552a09d PM	79	#if !defined(TARGET_SPARC64)
	80	cpu_set_cwp(env, val & PSR_CWP);
	81	#endif
	82	}
	83
	84	void cpu_put_psr(CPUSPARCState *env, target_ulong val)
	85	{
	86	cpu_put_psr_raw(env, val);
	87	#if ((!defined(TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
	88	cpu_check_irqs(env);
	89	#endif
070af384 BS	90	}
070af384 BS	91
c5f9864e	92	int cpu_cwp_inc(CPUSPARCState *env, int cwp)
070af384 BS	93	{
	94	if (unlikely(cwp >= env->nwindows)) {
	95	cwp -= env->nwindows;
	96	}
	97	return cwp;
	98	}
	99
c5f9864e	100	int cpu_cwp_dec(CPUSPARCState *env, int cwp)
070af384 BS	101	{
	102	if (unlikely(cwp < 0)) {
	103	cwp += env->nwindows;
	104	}
	105	return cwp;
	106	}
	107
070af384	108	#ifndef TARGET_SPARC64
c5f9864e	109	void helper_rett(CPUSPARCState *env)
070af384 BS	110	{
	111	unsigned int cwp;
	112
	113	if (env->psret == 1) {
	114	helper_raise_exception(env, TT_ILL_INSN);
	115	}
	116
	117	env->psret = 1;
063c3675	118	cwp = cpu_cwp_inc(env, env->cwp + 1) ;
070af384 BS	119	if (env->wim & (1 << cwp)) {
	120	helper_raise_exception(env, TT_WIN_UNF);
	121	}
063c3675	122	cpu_set_cwp(env, cwp);
070af384 BS	123	env->psrs = env->psrps;
	124	}
	125
	126	/* XXX: use another pointer for %iN registers to avoid slow wrapping
	127	handling ? */
c5f9864e	128	void helper_save(CPUSPARCState *env)
070af384 BS	129	{
	130	uint32_t cwp;
	131
063c3675	132	cwp = cpu_cwp_dec(env, env->cwp - 1);
070af384 BS	133	if (env->wim & (1 << cwp)) {
	134	helper_raise_exception(env, TT_WIN_OVF);
	135	}
063c3675	136	cpu_set_cwp(env, cwp);
070af384 BS	137	}
070af384 BS	138
c5f9864e	139	void helper_restore(CPUSPARCState *env)
070af384 BS	140	{
	141	uint32_t cwp;
	142
063c3675	143	cwp = cpu_cwp_inc(env, env->cwp + 1);
070af384 BS	144	if (env->wim & (1 << cwp)) {
	145	helper_raise_exception(env, TT_WIN_UNF);
	146	}
063c3675	147	cpu_set_cwp(env, cwp);
070af384 BS	148	}
070af384 BS	149
c5f9864e	150	void helper_wrpsr(CPUSPARCState *env, target_ulong new_psr)
070af384 BS	151	{
	152	if ((new_psr & PSR_CWP) >= env->nwindows) {
	153	helper_raise_exception(env, TT_ILL_INSN);
	154	} else {
	155	cpu_put_psr(env, new_psr);
	156	}
	157	}
	158
c5f9864e	159	target_ulong helper_rdpsr(CPUSPARCState *env)
070af384	160	{
063c3675	161	return cpu_get_psr(env);
070af384 BS	162	}
	163
	164	#else
	165	/* XXX: use another pointer for %iN registers to avoid slow wrapping
	166	handling ? */
c5f9864e	167	void helper_save(CPUSPARCState *env)
070af384 BS	168	{
	169	uint32_t cwp;
	170
063c3675	171	cwp = cpu_cwp_dec(env, env->cwp - 1);
070af384 BS	172	if (env->cansave == 0) {
	173	helper_raise_exception(env, TT_SPILL \| (env->otherwin != 0 ?
	174	(TT_WOTHER \|
	175	((env->wstate & 0x38) >> 1)) :
	176	((env->wstate & 0x7) << 2)));
	177	} else {
	178	if (env->cleanwin - env->canrestore == 0) {
	179	/* XXX Clean windows without trap */
	180	helper_raise_exception(env, TT_CLRWIN);
	181	} else {
	182	env->cansave--;
	183	env->canrestore++;
063c3675	184	cpu_set_cwp(env, cwp);
070af384 BS	185	}
	186	}
	187	}
	188
c5f9864e	189	void helper_restore(CPUSPARCState *env)
070af384 BS	190	{
	191	uint32_t cwp;
	192
063c3675	193	cwp = cpu_cwp_inc(env, env->cwp + 1);
070af384 BS	194	if (env->canrestore == 0) {
	195	helper_raise_exception(env, TT_FILL \| (env->otherwin != 0 ?
	196	(TT_WOTHER \|
	197	((env->wstate & 0x38) >> 1)) :
	198	((env->wstate & 0x7) << 2)));
	199	} else {
	200	env->cansave++;
	201	env->canrestore--;
063c3675	202	cpu_set_cwp(env, cwp);
070af384 BS	203	}
	204	}
	205
c5f9864e	206	void helper_flushw(CPUSPARCState *env)
070af384 BS	207	{
	208	if (env->cansave != env->nwindows - 2) {
	209	helper_raise_exception(env, TT_SPILL \| (env->otherwin != 0 ?
	210	(TT_WOTHER \|
	211	((env->wstate & 0x38) >> 1)) :
	212	((env->wstate & 0x7) << 2)));
	213	}
	214	}
	215
c5f9864e	216	void helper_saved(CPUSPARCState *env)
070af384 BS	217	{
	218	env->cansave++;
	219	if (env->otherwin == 0) {
	220	env->canrestore--;
	221	} else {
	222	env->otherwin--;
	223	}
	224	}
	225
c5f9864e	226	void helper_restored(CPUSPARCState *env)
070af384 BS	227	{
	228	env->canrestore++;
	229	if (env->cleanwin < env->nwindows - 1) {
	230	env->cleanwin++;
	231	}
	232	if (env->otherwin == 0) {
	233	env->cansave--;
	234	} else {
	235	env->otherwin--;
	236	}
	237	}
	238
c5f9864e	239	target_ulong cpu_get_ccr(CPUSPARCState *env)
070af384 BS	240	{
	241	target_ulong psr;
	242
063c3675	243	psr = cpu_get_psr(env);
070af384 BS	244
	245	return ((env->xcc >> 20) << 4) \| ((psr & PSR_ICC) >> 20);
	246	}
	247
c5f9864e	248	void cpu_put_ccr(CPUSPARCState *env, target_ulong val)
070af384 BS	249	{
	250	env->xcc = (val >> 4) << 20;
	251	env->psr = (val & 0xf) << 20;
	252	CC_OP = CC_OP_FLAGS;
	253	}
	254
c5f9864e	255	target_ulong cpu_get_cwp64(CPUSPARCState *env)
070af384 BS	256	{
	257	return env->nwindows - 1 - env->cwp;
	258	}
	259
c5f9864e	260	void cpu_put_cwp64(CPUSPARCState *env, int cwp)
070af384 BS	261	{
	262	if (unlikely(cwp >= env->nwindows \|\| cwp < 0)) {
	263	cwp %= env->nwindows;
	264	}
063c3675	265	cpu_set_cwp(env, env->nwindows - 1 - cwp);
070af384 BS	266	}
070af384 BS	267
c5f9864e	268	target_ulong helper_rdccr(CPUSPARCState *env)
070af384	269	{
063c3675	270	return cpu_get_ccr(env);
070af384 BS	271	}
070af384 BS	272
c5f9864e	273	void helper_wrccr(CPUSPARCState *env, target_ulong new_ccr)
070af384	274	{
063c3675	275	cpu_put_ccr(env, new_ccr);
070af384 BS	276	}
	277
	278	/* CWP handling is reversed in V9, but we still use the V8 register
	279	order. */
c5f9864e	280	target_ulong helper_rdcwp(CPUSPARCState *env)
070af384	281	{
063c3675	282	return cpu_get_cwp64(env);
070af384 BS	283	}
070af384 BS	284
c5f9864e	285	void helper_wrcwp(CPUSPARCState *env, target_ulong new_cwp)
070af384	286	{
063c3675	287	cpu_put_cwp64(env, new_cwp);
070af384 BS	288	}
070af384 BS	289
c5f9864e	290	static inline uint64_t get_gregset(CPUSPARCState env, uint32_t pstate)
070af384 BS	291	{
	292	switch (pstate) {
	293	default:
870be6ad	294	trace_win_helper_gregset_error(pstate);
070af384 BS	295	/* pass through to normal set of global registers */
	296	case 0:
	297	return env->bgregs;
	298	case PS_AG:
	299	return env->agregs;
	300	case PS_MG:
	301	return env->mgregs;
	302	case PS_IG:
	303	return env->igregs;
	304	}
	305	}
	306
c5f9864e	307	void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
070af384 BS	308	{
	309	uint32_t pstate_regs, new_pstate_regs;
	310	uint64_t src, dst;
	311
	312	if (env->def->features & CPU_FEATURE_GL) {
	313	/* PS_AG is not implemented in this case */
	314	new_pstate &= ~PS_AG;
	315	}
	316
	317	pstate_regs = env->pstate & 0xc01;
	318	new_pstate_regs = new_pstate & 0xc01;
	319
	320	if (new_pstate_regs != pstate_regs) {
870be6ad BS	321	trace_win_helper_switch_pstate(pstate_regs, new_pstate_regs);
870be6ad BS	322
070af384	323	/* Switch global register bank */
063c3675 BS	324	src = get_gregset(env, new_pstate_regs);
063c3675 BS	325	dst = get_gregset(env, pstate_regs);
070af384 BS	326	memcpy32(dst, env->gregs);
	327	memcpy32(env->gregs, src);
	328	} else {
870be6ad	329	trace_win_helper_no_switch_pstate(new_pstate_regs);
070af384 BS	330	}
	331	env->pstate = new_pstate;
	332	}
	333
c5f9864e	334	void helper_wrpstate(CPUSPARCState *env, target_ulong new_state)
070af384	335	{
063c3675	336	cpu_change_pstate(env, new_state & 0xf3f);
070af384 BS	337
	338	#if !defined(CONFIG_USER_ONLY)
	339	if (cpu_interrupts_enabled(env)) {
	340	cpu_check_irqs(env);
	341	}
	342	#endif
	343	}
	344
c5f9864e	345	void helper_wrpil(CPUSPARCState *env, target_ulong new_pil)
070af384 BS	346	{
070af384 BS	347	#if !defined(CONFIG_USER_ONLY)
870be6ad	348	trace_win_helper_wrpil(env->psrpil, (uint32_t)new_pil);
070af384 BS	349
	350	env->psrpil = new_pil;
	351
	352	if (cpu_interrupts_enabled(env)) {
	353	cpu_check_irqs(env);
	354	}
	355	#endif
	356	}
	357
c5f9864e	358	void helper_done(CPUSPARCState *env)
070af384 BS	359	{
	360	trap_state *tsptr = cpu_tsptr(env);
	361
	362	env->pc = tsptr->tnpc;
	363	env->npc = tsptr->tnpc + 4;
063c3675	364	cpu_put_ccr(env, tsptr->tstate >> 32);
070af384	365	env->asi = (tsptr->tstate >> 24) & 0xff;
063c3675 BS	366	cpu_change_pstate(env, (tsptr->tstate >> 8) & 0xf3f);
063c3675 BS	367	cpu_put_cwp64(env, tsptr->tstate & 0xff);
070af384 BS	368	env->tl--;
070af384 BS	369
870be6ad	370	trace_win_helper_done(env->tl);
070af384 BS	371
	372	#if !defined(CONFIG_USER_ONLY)
	373	if (cpu_interrupts_enabled(env)) {
	374	cpu_check_irqs(env);
	375	}
	376	#endif
	377	}
	378
c5f9864e	379	void helper_retry(CPUSPARCState *env)
070af384 BS	380	{
	381	trap_state *tsptr = cpu_tsptr(env);
	382
	383	env->pc = tsptr->tpc;
	384	env->npc = tsptr->tnpc;
063c3675	385	cpu_put_ccr(env, tsptr->tstate >> 32);
070af384	386	env->asi = (tsptr->tstate >> 24) & 0xff;
063c3675 BS	387	cpu_change_pstate(env, (tsptr->tstate >> 8) & 0xf3f);
063c3675 BS	388	cpu_put_cwp64(env, tsptr->tstate & 0xff);
070af384 BS	389	env->tl--;
070af384 BS	390
870be6ad	391	trace_win_helper_retry(env->tl);
070af384 BS	392
	393	#if !defined(CONFIG_USER_ONLY)
	394	if (cpu_interrupts_enabled(env)) {
	395	cpu_check_irqs(env);
	396	}
	397	#endif
	398	}
	399	#endif