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Remove io_index argument from cpu_register_io_memory()
[qemu.git] / hw / lsi53c895a.c
CommitLineData
5fafdf24 1/*
7d8406be
PB		 2 * QEMU LSI53C895A SCSI Host Bus Adapter emulation
3 *
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
6 *
7 * This code is licenced under the LGPL.
8 */
9
10/* ??? Need to check if the {read,write}[wl] routines work properly on
11 big-endian targets. */
12
87ecb68b
PB		 13#include "hw.h"
14#include "pci.h"
15#include "scsi-disk.h"
b0a7b120 16#include "block_int.h"
7d8406be
PB		 17
18//#define DEBUG_LSI
19//#define DEBUG_LSI_REG
20
21#ifdef DEBUG_LSI
001faf32
BS		 22#define DPRINTF(fmt, ...) \
23do { printf("lsi_scsi: " fmt , ## __VA_ARGS__); } while (0)
24#define BADF(fmt, ...) \
25do { fprintf(stderr, "lsi_scsi: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
7d8406be 26#else
001faf32
BS		 27#define DPRINTF(fmt, ...) do {} while(0)
28#define BADF(fmt, ...) \
29do { fprintf(stderr, "lsi_scsi: error: " fmt , ## __VA_ARGS__);} while (0)
7d8406be
PB		 30#endif
31
32#define LSI_SCNTL0_TRG 0x01
33#define LSI_SCNTL0_AAP 0x02
34#define LSI_SCNTL0_EPC 0x08
35#define LSI_SCNTL0_WATN 0x10
36#define LSI_SCNTL0_START 0x20
37
38#define LSI_SCNTL1_SST 0x01
39#define LSI_SCNTL1_IARB 0x02
40#define LSI_SCNTL1_AESP 0x04
41#define LSI_SCNTL1_RST 0x08
42#define LSI_SCNTL1_CON 0x10
43#define LSI_SCNTL1_DHP 0x20
44#define LSI_SCNTL1_ADB 0x40
45#define LSI_SCNTL1_EXC 0x80
46
47#define LSI_SCNTL2_WSR 0x01
48#define LSI_SCNTL2_VUE0 0x02
49#define LSI_SCNTL2_VUE1 0x04
50#define LSI_SCNTL2_WSS 0x08
51#define LSI_SCNTL2_SLPHBEN 0x10
52#define LSI_SCNTL2_SLPMD 0x20
53#define LSI_SCNTL2_CHM 0x40
54#define LSI_SCNTL2_SDU 0x80
55
56#define LSI_ISTAT0_DIP 0x01
57#define LSI_ISTAT0_SIP 0x02
58#define LSI_ISTAT0_INTF 0x04
59#define LSI_ISTAT0_CON 0x08
60#define LSI_ISTAT0_SEM 0x10
61#define LSI_ISTAT0_SIGP 0x20
62#define LSI_ISTAT0_SRST 0x40
63#define LSI_ISTAT0_ABRT 0x80
64
65#define LSI_ISTAT1_SI 0x01
66#define LSI_ISTAT1_SRUN 0x02
67#define LSI_ISTAT1_FLSH 0x04
68
69#define LSI_SSTAT0_SDP0 0x01
70#define LSI_SSTAT0_RST 0x02
71#define LSI_SSTAT0_WOA 0x04
72#define LSI_SSTAT0_LOA 0x08
73#define LSI_SSTAT0_AIP 0x10
74#define LSI_SSTAT0_OLF 0x20
75#define LSI_SSTAT0_ORF 0x40
76#define LSI_SSTAT0_ILF 0x80
77
78#define LSI_SIST0_PAR 0x01
79#define LSI_SIST0_RST 0x02
80#define LSI_SIST0_UDC 0x04
81#define LSI_SIST0_SGE 0x08
82#define LSI_SIST0_RSL 0x10
83#define LSI_SIST0_SEL 0x20
84#define LSI_SIST0_CMP 0x40
85#define LSI_SIST0_MA 0x80
86
87#define LSI_SIST1_HTH 0x01
88#define LSI_SIST1_GEN 0x02
89#define LSI_SIST1_STO 0x04
90#define LSI_SIST1_SBMC 0x10
91
92#define LSI_SOCL_IO 0x01
93#define LSI_SOCL_CD 0x02
94#define LSI_SOCL_MSG 0x04
95#define LSI_SOCL_ATN 0x08
96#define LSI_SOCL_SEL 0x10
97#define LSI_SOCL_BSY 0x20
98#define LSI_SOCL_ACK 0x40
99#define LSI_SOCL_REQ 0x80
100
101#define LSI_DSTAT_IID 0x01
102#define LSI_DSTAT_SIR 0x04
103#define LSI_DSTAT_SSI 0x08
104#define LSI_DSTAT_ABRT 0x10
105#define LSI_DSTAT_BF 0x20
106#define LSI_DSTAT_MDPE 0x40
107#define LSI_DSTAT_DFE 0x80
108
109#define LSI_DCNTL_COM 0x01
110#define LSI_DCNTL_IRQD 0x02
111#define LSI_DCNTL_STD 0x04
112#define LSI_DCNTL_IRQM 0x08
113#define LSI_DCNTL_SSM 0x10
114#define LSI_DCNTL_PFEN 0x20
115#define LSI_DCNTL_PFF 0x40
116#define LSI_DCNTL_CLSE 0x80
117
118#define LSI_DMODE_MAN 0x01
119#define LSI_DMODE_BOF 0x02
120#define LSI_DMODE_ERMP 0x04
121#define LSI_DMODE_ERL 0x08
122#define LSI_DMODE_DIOM 0x10
123#define LSI_DMODE_SIOM 0x20
124
125#define LSI_CTEST2_DACK 0x01
126#define LSI_CTEST2_DREQ 0x02
127#define LSI_CTEST2_TEOP 0x04
128#define LSI_CTEST2_PCICIE 0x08
129#define LSI_CTEST2_CM 0x10
130#define LSI_CTEST2_CIO 0x20
131#define LSI_CTEST2_SIGP 0x40
132#define LSI_CTEST2_DDIR 0x80
133
134#define LSI_CTEST5_BL2 0x04
135#define LSI_CTEST5_DDIR 0x08
136#define LSI_CTEST5_MASR 0x10
137#define LSI_CTEST5_DFSN 0x20
138#define LSI_CTEST5_BBCK 0x40
139#define LSI_CTEST5_ADCK 0x80
140
141#define LSI_CCNTL0_DILS 0x01
142#define LSI_CCNTL0_DISFC 0x10
143#define LSI_CCNTL0_ENNDJ 0x20
144#define LSI_CCNTL0_PMJCTL 0x40
145#define LSI_CCNTL0_ENPMJ 0x80
146
b25cf589
AL		 147#define LSI_CCNTL1_EN64DBMV 0x01
148#define LSI_CCNTL1_EN64TIBMV 0x02
149#define LSI_CCNTL1_64TIMOD 0x04
150#define LSI_CCNTL1_DDAC 0x08
151#define LSI_CCNTL1_ZMOD 0x80
152
153#define LSI_CCNTL1_40BIT (LSI_CCNTL1_EN64TIBMV|LSI_CCNTL1_64TIMOD)
154
7d8406be
PB		 155#define PHASE_DO 0
156#define PHASE_DI 1
157#define PHASE_CMD 2
158#define PHASE_ST 3
159#define PHASE_MO 6
160#define PHASE_MI 7
161#define PHASE_MASK 7
162
a917d384
PB		 163/* Maximum length of MSG IN data. */
164#define LSI_MAX_MSGIN_LEN 8
165
166/* Flag set if this is a tagged command. */
167#define LSI_TAG_VALID (1 << 16)
168
169typedef struct {
170 uint32_t tag;
171 uint32_t pending;
172 int out;
173} lsi_queue;
4d611c9a 174
7d8406be
PB		 175typedef struct {
176 PCIDevice pci_dev;
177 int mmio_io_addr;
178 int ram_io_addr;
179 uint32_t script_ram_base;
7d8406be
PB		 180
181 int carry; /* ??? Should this be an a visible register somewhere? */
182 int sense;
a917d384
PB		 183 /* Action to take at the end of a MSG IN phase.
184 0 = COMMAND, 1 = disconect, 2 = DATA OUT, 3 = DATA IN. */
185 int msg_action;
186 int msg_len;
187 uint8_t msg[LSI_MAX_MSGIN_LEN];
4d611c9a
PB		 188 /* 0 if SCRIPTS are running or stopped.
189 * 1 if a Wait Reselect instruction has been issued.
a917d384
PB		 190 * 2 if processing DMA from lsi_execute_script.
191 * 3 if a DMA operation is in progress. */
7d8406be
PB		 192 int waiting;
193 SCSIDevice *scsi_dev[LSI_MAX_DEVS];
194 SCSIDevice *current_dev;
195 int current_lun;
a917d384
PB		 196 /* The tag is a combination of the device ID and the SCSI tag. */
197 uint32_t current_tag;
198 uint32_t current_dma_len;
8ccc2ace 199 int command_complete;
a917d384
PB		 200 uint8_t *dma_buf;
201 lsi_queue *queue;
202 int queue_len;
203 int active_commands;
7d8406be
PB		 204
205 uint32_t dsa;
206 uint32_t temp;
207 uint32_t dnad;
208 uint32_t dbc;
209 uint8_t istat0;
210 uint8_t istat1;
211 uint8_t dcmd;
212 uint8_t dstat;
213 uint8_t dien;
214 uint8_t sist0;
215 uint8_t sist1;
216 uint8_t sien0;
217 uint8_t sien1;
218 uint8_t mbox0;
219 uint8_t mbox1;
220 uint8_t dfifo;
9167a69a 221 uint8_t ctest2;
7d8406be
PB		 222 uint8_t ctest3;
223 uint8_t ctest4;
224 uint8_t ctest5;
225 uint8_t ccntl0;
226 uint8_t ccntl1;
227 uint32_t dsp;
228 uint32_t dsps;
229 uint8_t dmode;
230 uint8_t dcntl;
231 uint8_t scntl0;
232 uint8_t scntl1;
233 uint8_t scntl2;
234 uint8_t scntl3;
235 uint8_t sstat0;
236 uint8_t sstat1;
237 uint8_t scid;
238 uint8_t sxfer;
239 uint8_t socl;
240 uint8_t sdid;
a917d384 241 uint8_t ssid;
7d8406be
PB		 242 uint8_t sfbr;
243 uint8_t stest1;
244 uint8_t stest2;
245 uint8_t stest3;
a917d384 246 uint8_t sidl;
7d8406be
PB		 247 uint8_t stime0;
248 uint8_t respid0;
249 uint8_t respid1;
250 uint32_t mmrs;
251 uint32_t mmws;
252 uint32_t sfs;
253 uint32_t drs;
254 uint32_t sbms;
ab57d967 255 uint32_t dbms;
7d8406be
PB		 256 uint32_t dnad64;
257 uint32_t pmjad1;
258 uint32_t pmjad2;
259 uint32_t rbc;
260 uint32_t ua;
261 uint32_t ia;
262 uint32_t sbc;
263 uint32_t csbc;
dcfb9014 264 uint32_t scratch[18]; /* SCRATCHA-SCRATCHR */
7d8406be
PB		 265
266 /* Script ram is stored as 32-bit words in host byteorder. */
267 uint32_t script_ram[2048];
268} LSIState;
269
270static void lsi_soft_reset(LSIState *s)
271{
272 DPRINTF("Reset\n");
273 s->carry = 0;
274
275 s->waiting = 0;
276 s->dsa = 0;
277 s->dnad = 0;
278 s->dbc = 0;
279 s->temp = 0;
280 memset(s->scratch, 0, sizeof(s->scratch));
281 s->istat0 = 0;
282 s->istat1 = 0;
283 s->dcmd = 0;
284 s->dstat = 0;
285 s->dien = 0;
286 s->sist0 = 0;
287 s->sist1 = 0;
288 s->sien0 = 0;
289 s->sien1 = 0;
290 s->mbox0 = 0;
291 s->mbox1 = 0;
292 s->dfifo = 0;
9167a69a 293 s->ctest2 = 0;
7d8406be
PB		 294 s->ctest3 = 0;
295 s->ctest4 = 0;
296 s->ctest5 = 0;
297 s->ccntl0 = 0;
298 s->ccntl1 = 0;
299 s->dsp = 0;
300 s->dsps = 0;
301 s->dmode = 0;
302 s->dcntl = 0;
303 s->scntl0 = 0xc0;
304 s->scntl1 = 0;
305 s->scntl2 = 0;
306 s->scntl3 = 0;
307 s->sstat0 = 0;
308 s->sstat1 = 0;
309 s->scid = 7;
310 s->sxfer = 0;
311 s->socl = 0;
312 s->stest1 = 0;
313 s->stest2 = 0;
314 s->stest3 = 0;
a917d384 315 s->sidl = 0;
7d8406be
PB		 316 s->stime0 = 0;
317 s->respid0 = 0x80;
318 s->respid1 = 0;
319 s->mmrs = 0;
320 s->mmws = 0;
321 s->sfs = 0;
322 s->drs = 0;
323 s->sbms = 0;
ab57d967 324 s->dbms = 0;
7d8406be
PB		 325 s->dnad64 = 0;
326 s->pmjad1 = 0;
327 s->pmjad2 = 0;
328 s->rbc = 0;
329 s->ua = 0;
330 s->ia = 0;
331 s->sbc = 0;
332 s->csbc = 0;
333}
334
b25cf589
AL		 335static int lsi_dma_40bit(LSIState *s)
336{
337 if ((s->ccntl1 & LSI_CCNTL1_40BIT) == LSI_CCNTL1_40BIT)
338 return 1;
339 return 0;
340}
341
dd8edf01
AL		 342static int lsi_dma_ti64bit(LSIState *s)
343{
344 if ((s->ccntl1 & LSI_CCNTL1_EN64TIBMV) == LSI_CCNTL1_EN64TIBMV)
345 return 1;
346 return 0;
347}
348
349static int lsi_dma_64bit(LSIState *s)
350{
351 if ((s->ccntl1 & LSI_CCNTL1_EN64DBMV) == LSI_CCNTL1_EN64DBMV)
352 return 1;
353 return 0;
354}
355
7d8406be
PB		 356static uint8_t lsi_reg_readb(LSIState *s, int offset);
357static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val);
4d611c9a 358static void lsi_execute_script(LSIState *s);
7d8406be
PB		 359
360static inline uint32_t read_dword(LSIState *s, uint32_t addr)
361{
362 uint32_t buf;
363
364 /* Optimize reading from SCRIPTS RAM. */
365 if ((addr & 0xffffe000) == s->script_ram_base) {
366 return s->script_ram[(addr & 0x1fff) >> 2];
367 }
368 cpu_physical_memory_read(addr, (uint8_t *)&buf, 4);
369 return cpu_to_le32(buf);
370}
371
372static void lsi_stop_script(LSIState *s)
373{
374 s->istat1 &= ~LSI_ISTAT1_SRUN;
375}
376
377static void lsi_update_irq(LSIState *s)
378{
379 int level;
380 static int last_level;
381
382 /* It's unclear whether the DIP/SIP bits should be cleared when the
383 Interrupt Status Registers are cleared or when istat0 is read.
384 We currently do the formwer, which seems to work. */
385 level = 0;
386 if (s->dstat) {
387 if (s->dstat & s->dien)
388 level = 1;
389 s->istat0 |= LSI_ISTAT0_DIP;
390 } else {
391 s->istat0 &= ~LSI_ISTAT0_DIP;
392 }
393
394 if (s->sist0 || s->sist1) {
395 if ((s->sist0 & s->sien0) || (s->sist1 & s->sien1))
396 level = 1;
397 s->istat0 |= LSI_ISTAT0_SIP;
398 } else {
399 s->istat0 &= ~LSI_ISTAT0_SIP;
400 }
401 if (s->istat0 & LSI_ISTAT0_INTF)
402 level = 1;
403
404 if (level != last_level) {
405 DPRINTF("Update IRQ level %d dstat %02x sist %02x%02x\n",
406 level, s->dstat, s->sist1, s->sist0);
407 last_level = level;
408 }
d537cf6c 409 qemu_set_irq(s->pci_dev.irq[0], level);
7d8406be
PB		 410}
411
412/* Stop SCRIPTS execution and raise a SCSI interrupt. */
413static void lsi_script_scsi_interrupt(LSIState *s, int stat0, int stat1)
414{
415 uint32_t mask0;
416 uint32_t mask1;
417
418 DPRINTF("SCSI Interrupt 0x%02x%02x prev 0x%02x%02x\n",
419 stat1, stat0, s->sist1, s->sist0);
420 s->sist0 |= stat0;
421 s->sist1 |= stat1;
422 /* Stop processor on fatal or unmasked interrupt. As a special hack
423 we don't stop processing when raising STO. Instead continue
424 execution and stop at the next insn that accesses the SCSI bus. */
425 mask0 = s->sien0 | ~(LSI_SIST0_CMP | LSI_SIST0_SEL | LSI_SIST0_RSL);
426 mask1 = s->sien1 | ~(LSI_SIST1_GEN | LSI_SIST1_HTH);
427 mask1 &= ~LSI_SIST1_STO;
428 if (s->sist0 & mask0 || s->sist1 & mask1) {
429 lsi_stop_script(s);
430 }
431 lsi_update_irq(s);
432}
433
434/* Stop SCRIPTS execution and raise a DMA interrupt. */
435static void lsi_script_dma_interrupt(LSIState *s, int stat)
436{
437 DPRINTF("DMA Interrupt 0x%x prev 0x%x\n", stat, s->dstat);
438 s->dstat |= stat;
439 lsi_update_irq(s);
440 lsi_stop_script(s);
441}
442
443static inline void lsi_set_phase(LSIState *s, int phase)
444{
445 s->sstat1 = (s->sstat1 & ~PHASE_MASK) | phase;
446}
447
448static void lsi_bad_phase(LSIState *s, int out, int new_phase)
449{
450 /* Trigger a phase mismatch. */
451 if (s->ccntl0 & LSI_CCNTL0_ENPMJ) {
452 if ((s->ccntl0 & LSI_CCNTL0_PMJCTL) || out) {
453 s->dsp = s->pmjad1;
454 } else {
455 s->dsp = s->pmjad2;
456 }
457 DPRINTF("Data phase mismatch jump to %08x\n", s->dsp);
458 } else {
459 DPRINTF("Phase mismatch interrupt\n");
460 lsi_script_scsi_interrupt(s, LSI_SIST0_MA, 0);
461 lsi_stop_script(s);
462 }
463 lsi_set_phase(s, new_phase);
464}
465
a917d384
PB		 466
467/* Resume SCRIPTS execution after a DMA operation. */
468static void lsi_resume_script(LSIState *s)
469{
470 if (s->waiting != 2) {
471 s->waiting = 0;
472 lsi_execute_script(s);
473 } else {
474 s->waiting = 0;
475 }
476}
477
4d611c9a 478/* Initiate a SCSI layer data transfer. */
7d8406be
PB		 479static void lsi_do_dma(LSIState *s, int out)
480{
7d8406be 481 uint32_t count;
b25cf589 482 target_phys_addr_t addr;
7d8406be 483
a917d384
PB		 484 if (!s->current_dma_len) {
485 /* Wait until data is available. */
486 DPRINTF("DMA no data available\n");
487 return;
7d8406be
PB		 488 }
489
a917d384
PB		 490 count = s->dbc;
491 if (count > s->current_dma_len)
492 count = s->current_dma_len;
a917d384
PB		 493
494 addr = s->dnad;
dd8edf01
AL		 495 /* both 40 and Table Indirect 64-bit DMAs store upper bits in dnad64 */
496 if (lsi_dma_40bit(s) || lsi_dma_ti64bit(s))
b25cf589 497 addr |= ((uint64_t)s->dnad64 << 32);
dd8edf01
AL		 498 else if (s->dbms)
499 addr |= ((uint64_t)s->dbms << 32);
b25cf589
AL		 500 else if (s->sbms)
501 addr |= ((uint64_t)s->sbms << 32);
502
3adae656 503 DPRINTF("DMA addr=0x" TARGET_FMT_plx " len=%d\n", addr, count);
7d8406be 504 s->csbc += count;
a917d384
PB		 505 s->dnad += count;
506 s->dbc -= count;
507
508 if (s->dma_buf == NULL) {
8ccc2ace
TS		 509 s->dma_buf = s->current_dev->get_buf(s->current_dev,
510 s->current_tag);
a917d384 511 }
7d8406be
PB		 512
513 /* ??? Set SFBR to first data byte. */
a917d384
PB		 514 if (out) {
515 cpu_physical_memory_read(addr, s->dma_buf, count);
516 } else {
517 cpu_physical_memory_write(addr, s->dma_buf, count);
518 }
519 s->current_dma_len -= count;
520 if (s->current_dma_len == 0) {
521 s->dma_buf = NULL;
522 if (out) {
523 /* Write the data. */
8ccc2ace 524 s->current_dev->write_data(s->current_dev, s->current_tag);
a917d384
PB		 525 } else {
526 /* Request any remaining data. */
8ccc2ace 527 s->current_dev->read_data(s->current_dev, s->current_tag);
a917d384
PB		 528 }
529 } else {
530 s->dma_buf += count;
531 lsi_resume_script(s);
532 }
533}
534
535
536/* Add a command to the queue. */
537static void lsi_queue_command(LSIState *s)
538{
539 lsi_queue *p;
540
541 DPRINTF("Queueing tag=0x%x\n", s->current_tag);
542 if (s->queue_len == s->active_commands) {
543 s->queue_len++;
2137b4cc 544 s->queue = qemu_realloc(s->queue, s->queue_len * sizeof(lsi_queue));
a917d384
PB		 545 }
546 p = &s->queue[s->active_commands++];
547 p->tag = s->current_tag;
548 p->pending = 0;
549 p->out = (s->sstat1 & PHASE_MASK) == PHASE_DO;
550}
551
552/* Queue a byte for a MSG IN phase. */
553static void lsi_add_msg_byte(LSIState *s, uint8_t data)
554{
555 if (s->msg_len >= LSI_MAX_MSGIN_LEN) {
556 BADF("MSG IN data too long\n");
4d611c9a 557 } else {
a917d384
PB		 558 DPRINTF("MSG IN 0x%02x\n", data);
559 s->msg[s->msg_len++] = data;
7d8406be 560 }
a917d384
PB		 561}
562
563/* Perform reselection to continue a command. */
564static void lsi_reselect(LSIState *s, uint32_t tag)
565{
566 lsi_queue *p;
567 int n;
568 int id;
569
570 p = NULL;
571 for (n = 0; n < s->active_commands; n++) {
572 p = &s->queue[n];
573 if (p->tag == tag)
574 break;
575 }
576 if (n == s->active_commands) {
577 BADF("Reselected non-existant command tag=0x%x\n", tag);
578 return;
579 }
580 id = (tag >> 8) & 0xf;
581 s->ssid = id | 0x80;
582 DPRINTF("Reselected target %d\n", id);
583 s->current_dev = s->scsi_dev[id];
584 s->current_tag = tag;
585 s->scntl1 |= LSI_SCNTL1_CON;
586 lsi_set_phase(s, PHASE_MI);
587 s->msg_action = p->out ? 2 : 3;
588 s->current_dma_len = p->pending;
589 s->dma_buf = NULL;
590 lsi_add_msg_byte(s, 0x80);
591 if (s->current_tag & LSI_TAG_VALID) {
592 lsi_add_msg_byte(s, 0x20);
593 lsi_add_msg_byte(s, tag & 0xff);
594 }
595
596 s->active_commands--;
597 if (n != s->active_commands) {
598 s->queue[n] = s->queue[s->active_commands];
599 }
600}
601
602/* Record that data is available for a queued command. Returns zero if
603 the device was reselected, nonzero if the IO is deferred. */
604static int lsi_queue_tag(LSIState *s, uint32_t tag, uint32_t arg)
605{
606 lsi_queue *p;
607 int i;
608 for (i = 0; i < s->active_commands; i++) {
609 p = &s->queue[i];
610 if (p->tag == tag) {
611 if (p->pending) {
612 BADF("Multiple IO pending for tag %d\n", tag);
613 }
614 p->pending = arg;
615 if (s->waiting == 1) {
616 /* Reselect device. */
617 lsi_reselect(s, tag);
618 return 0;
619 } else {
620 DPRINTF("Queueing IO tag=0x%x\n", tag);
621 p->pending = arg;
622 return 1;
623 }
624 }
625 }
626 BADF("IO with unknown tag %d\n", tag);
627 return 1;
7d8406be
PB		 628}
629
4d611c9a 630/* Callback to indicate that the SCSI layer has completed a transfer. */
a917d384
PB		 631static void lsi_command_complete(void *opaque, int reason, uint32_t tag,
632 uint32_t arg)
4d611c9a
PB		 633{
634 LSIState *s = (LSIState *)opaque;
4d611c9a
PB		 635 int out;
636
a917d384 637 out = (s->sstat1 & PHASE_MASK) == PHASE_DO;
4d611c9a 638 if (reason == SCSI_REASON_DONE) {
a917d384
PB		 639 DPRINTF("Command complete sense=%d\n", (int)arg);
640 s->sense = arg;
8ccc2ace 641 s->command_complete = 2;
a917d384
PB		 642 if (s->waiting && s->dbc != 0) {
643 /* Raise phase mismatch for short transfers. */
644 lsi_bad_phase(s, out, PHASE_ST);
645 } else {
646 lsi_set_phase(s, PHASE_ST);
647 }
648 lsi_resume_script(s);
649 return;
4d611c9a
PB		 650 }
651
a917d384
PB		 652 if (s->waiting == 1 || tag != s->current_tag) {
653 if (lsi_queue_tag(s, tag, arg))
654 return;
655 }
656 DPRINTF("Data ready tag=0x%x len=%d\n", tag, arg);
657 s->current_dma_len = arg;
8ccc2ace 658 s->command_complete = 1;
a917d384
PB		 659 if (!s->waiting)
660 return;
661 if (s->waiting == 1 || s->dbc == 0) {
662 lsi_resume_script(s);
663 } else {
4d611c9a 664 lsi_do_dma(s, out);
4d611c9a
PB		 665 }
666}
7d8406be
PB		 667
668static void lsi_do_command(LSIState *s)
669{
670 uint8_t buf[16];
671 int n;
672
673 DPRINTF("Send command len=%d\n", s->dbc);
674 if (s->dbc > 16)
675 s->dbc = 16;
676 cpu_physical_memory_read(s->dnad, buf, s->dbc);
677 s->sfbr = buf[0];
8ccc2ace
TS		 678 s->command_complete = 0;
679 n = s->current_dev->send_command(s->current_dev, s->current_tag, buf,
680 s->current_lun);
7d8406be 681 if (n > 0) {
7d8406be 682 lsi_set_phase(s, PHASE_DI);
8ccc2ace 683 s->current_dev->read_data(s->current_dev, s->current_tag);
7d8406be 684 } else if (n < 0) {
7d8406be 685 lsi_set_phase(s, PHASE_DO);
8ccc2ace 686 s->current_dev->write_data(s->current_dev, s->current_tag);
a917d384 687 }
8ccc2ace
TS		 688
689 if (!s->command_complete) {
690 if (n) {
691 /* Command did not complete immediately so disconnect. */
692 lsi_add_msg_byte(s, 2); /* SAVE DATA POINTER */
693 lsi_add_msg_byte(s, 4); /* DISCONNECT */
694 /* wait data */
695 lsi_set_phase(s, PHASE_MI);
696 s->msg_action = 1;
697 lsi_queue_command(s);
698 } else {
699 /* wait command complete */
700 lsi_set_phase(s, PHASE_DI);
701 }
7d8406be
PB		 702 }
703}
704
7d8406be
PB		 705static void lsi_do_status(LSIState *s)
706{
a917d384 707 uint8_t sense;
7d8406be
PB		 708 DPRINTF("Get status len=%d sense=%d\n", s->dbc, s->sense);
709 if (s->dbc != 1)
710 BADF("Bad Status move\n");
711 s->dbc = 1;
a917d384
PB		 712 sense = s->sense;
713 s->sfbr = sense;
714 cpu_physical_memory_write(s->dnad, &sense, 1);
7d8406be 715 lsi_set_phase(s, PHASE_MI);
a917d384
PB		 716 s->msg_action = 1;
717 lsi_add_msg_byte(s, 0); /* COMMAND COMPLETE */
7d8406be
PB		 718}
719
720static void lsi_disconnect(LSIState *s)
721{
722 s->scntl1 &= ~LSI_SCNTL1_CON;
723 s->sstat1 &= ~PHASE_MASK;
724}
725
726static void lsi_do_msgin(LSIState *s)
727{
a917d384
PB		 728 int len;
729 DPRINTF("Message in len=%d/%d\n", s->dbc, s->msg_len);
730 s->sfbr = s->msg[0];
731 len = s->msg_len;
732 if (len > s->dbc)
733 len = s->dbc;
734 cpu_physical_memory_write(s->dnad, s->msg, len);
735 /* Linux drivers rely on the last byte being in the SIDL. */
736 s->sidl = s->msg[len - 1];
737 s->msg_len -= len;
738 if (s->msg_len) {
739 memmove(s->msg, s->msg + len, s->msg_len);
7d8406be
PB		 740 } else {
741 /* ??? Check if ATN (not yet implemented) is asserted and maybe
742 switch to PHASE_MO. */
a917d384
PB		 743 switch (s->msg_action) {
744 case 0:
745 lsi_set_phase(s, PHASE_CMD);
746 break;
747 case 1:
748 lsi_disconnect(s);
749 break;
750 case 2:
751 lsi_set_phase(s, PHASE_DO);
752 break;
753 case 3:
754 lsi_set_phase(s, PHASE_DI);
755 break;
756 default:
757 abort();
758 }
7d8406be
PB		 759 }
760}
761
a917d384
PB		 762/* Read the next byte during a MSGOUT phase. */
763static uint8_t lsi_get_msgbyte(LSIState *s)
764{
765 uint8_t data;
766 cpu_physical_memory_read(s->dnad, &data, 1);
767 s->dnad++;
768 s->dbc--;
769 return data;
770}
771
7d8406be
PB		 772static void lsi_do_msgout(LSIState *s)
773{
774 uint8_t msg;
a917d384 775 int len;
7d8406be
PB		 776
777 DPRINTF("MSG out len=%d\n", s->dbc);
a917d384
PB		 778 while (s->dbc) {
779 msg = lsi_get_msgbyte(s);
780 s->sfbr = msg;
781
782 switch (msg) {
783 case 0x00:
784 DPRINTF("MSG: Disconnect\n");
785 lsi_disconnect(s);
786 break;
787 case 0x08:
788 DPRINTF("MSG: No Operation\n");
789 lsi_set_phase(s, PHASE_CMD);
790 break;
791 case 0x01:
792 len = lsi_get_msgbyte(s);
793 msg = lsi_get_msgbyte(s);
794 DPRINTF("Extended message 0x%x (len %d)\n", msg, len);
795 switch (msg) {
796 case 1:
797 DPRINTF("SDTR (ignored)\n");
798 s->dbc -= 2;
799 break;
800 case 3:
801 DPRINTF("WDTR (ignored)\n");
802 s->dbc -= 1;
803 break;
804 default:
805 goto bad;
806 }
807 break;
808 case 0x20: /* SIMPLE queue */
809 s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
810 DPRINTF("SIMPLE queue tag=0x%x\n", s->current_tag & 0xff);
811 break;
812 case 0x21: /* HEAD of queue */
813 BADF("HEAD queue not implemented\n");
814 s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
815 break;
816 case 0x22: /* ORDERED queue */
817 BADF("ORDERED queue not implemented\n");
818 s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
819 break;
820 default:
821 if ((msg & 0x80) == 0) {
822 goto bad;
823 }
824 s->current_lun = msg & 7;
825 DPRINTF("Select LUN %d\n", s->current_lun);
826 lsi_set_phase(s, PHASE_CMD);
827 break;
828 }
7d8406be 829 }
a917d384
PB		 830 return;
831bad:
832 BADF("Unimplemented message 0x%02x\n", msg);
833 lsi_set_phase(s, PHASE_MI);
834 lsi_add_msg_byte(s, 7); /* MESSAGE REJECT */
835 s->msg_action = 0;
7d8406be
PB		 836}
837
838/* Sign extend a 24-bit value. */
839static inline int32_t sxt24(int32_t n)
840{
841 return (n << 8) >> 8;
842}
843
e20a8dff 844#define LSI_BUF_SIZE 4096
7d8406be
PB		 845static void lsi_memcpy(LSIState *s, uint32_t dest, uint32_t src, int count)
846{
847 int n;
e20a8dff 848 uint8_t buf[LSI_BUF_SIZE];
7d8406be
PB		 849
850 DPRINTF("memcpy dest 0x%08x src 0x%08x count %d\n", dest, src, count);
851 while (count) {
e20a8dff 852 n = (count > LSI_BUF_SIZE) ? LSI_BUF_SIZE : count;
7d8406be
PB		 853 cpu_physical_memory_read(src, buf, n);
854 cpu_physical_memory_write(dest, buf, n);
855 src += n;
856 dest += n;
857 count -= n;
858 }
859}
860
a917d384
PB		 861static void lsi_wait_reselect(LSIState *s)
862{
863 int i;
864 DPRINTF("Wait Reselect\n");
865 if (s->current_dma_len)
866 BADF("Reselect with pending DMA\n");
867 for (i = 0; i < s->active_commands; i++) {
868 if (s->queue[i].pending) {
869 lsi_reselect(s, s->queue[i].tag);
870 break;
871 }
872 }
873 if (s->current_dma_len == 0) {
874 s->waiting = 1;
875 }
876}
877
7d8406be
PB		 878static void lsi_execute_script(LSIState *s)
879{
880 uint32_t insn;
b25cf589 881 uint32_t addr, addr_high;
7d8406be 882 int opcode;
ee4d919f 883 int insn_processed = 0;
7d8406be
PB		 884
885 s->istat1 |= LSI_ISTAT1_SRUN;
886again:
ee4d919f 887 insn_processed++;
7d8406be 888 insn = read_dword(s, s->dsp);
02b373ad
AZ		 889 if (!insn) {
890 /* If we receive an empty opcode increment the DSP by 4 bytes
891 instead of 8 and execute the next opcode at that location */
892 s->dsp += 4;
893 goto again;
894 }
7d8406be 895 addr = read_dword(s, s->dsp + 4);
b25cf589 896 addr_high = 0;
7d8406be
PB		 897 DPRINTF("SCRIPTS dsp=%08x opcode %08x arg %08x\n", s->dsp, insn, addr);
898 s->dsps = addr;
899 s->dcmd = insn >> 24;
900 s->dsp += 8;
901 switch (insn >> 30) {
902 case 0: /* Block move. */
903 if (s->sist1 & LSI_SIST1_STO) {
904 DPRINTF("Delayed select timeout\n");
905 lsi_stop_script(s);
906 break;
907 }
908 s->dbc = insn & 0xffffff;
909 s->rbc = s->dbc;
dd8edf01
AL		 910 /* ??? Set ESA. */
911 s->ia = s->dsp - 8;
7d8406be
PB		 912 if (insn & (1 << 29)) {
913 /* Indirect addressing. */
914 addr = read_dword(s, addr);
915 } else if (insn & (1 << 28)) {
916 uint32_t buf[2];
917 int32_t offset;
918 /* Table indirect addressing. */
dd8edf01
AL		 919
920 /* 32-bit Table indirect */
7d8406be
PB		 921 offset = sxt24(addr);
922 cpu_physical_memory_read(s->dsa + offset, (uint8_t *)buf, 8);
b25cf589
AL		 923 /* byte count is stored in bits 0:23 only */
924 s->dbc = cpu_to_le32(buf[0]) & 0xffffff;
7faa239c 925 s->rbc = s->dbc;
7d8406be 926 addr = cpu_to_le32(buf[1]);
b25cf589
AL		 927
928 /* 40-bit DMA, upper addr bits [39:32] stored in first DWORD of
929 * table, bits [31:24] */
930 if (lsi_dma_40bit(s))
931 addr_high = cpu_to_le32(buf[0]) >> 24;
dd8edf01
AL		 932 else if (lsi_dma_ti64bit(s)) {
933 int selector = (cpu_to_le32(buf[0]) >> 24) & 0x1f;
934 switch (selector) {
935 case 0 ... 0x0f:
936 /* offset index into scratch registers since
937 * TI64 mode can use registers C to R */
938 addr_high = s->scratch[2 + selector];
939 break;
940 case 0x10:
941 addr_high = s->mmrs;
942 break;
943 case 0x11:
944 addr_high = s->mmws;
945 break;
946 case 0x12:
947 addr_high = s->sfs;
948 break;
949 case 0x13:
950 addr_high = s->drs;
951 break;
952 case 0x14:
953 addr_high = s->sbms;
954 break;
955 case 0x15:
956 addr_high = s->dbms;
957 break;
958 default:
959 BADF("Illegal selector specified (0x%x > 0x15)"
960 " for 64-bit DMA block move", selector);
961 break;
962 }
963 }
964 } else if (lsi_dma_64bit(s)) {
965 /* fetch a 3rd dword if 64-bit direct move is enabled and
966 only if we're not doing table indirect or indirect addressing */
967 s->dbms = read_dword(s, s->dsp);
968 s->dsp += 4;
969 s->ia = s->dsp - 12;
7d8406be
PB		 970 }
971 if ((s->sstat1 & PHASE_MASK) != ((insn >> 24) & 7)) {
972 DPRINTF("Wrong phase got %d expected %d\n",
973 s->sstat1 & PHASE_MASK, (insn >> 24) & 7);
974 lsi_script_scsi_interrupt(s, LSI_SIST0_MA, 0);
975 break;
976 }
977 s->dnad = addr;
b25cf589 978 s->dnad64 = addr_high;
7d8406be
PB		 979 switch (s->sstat1 & 0x7) {
980 case PHASE_DO:
a917d384 981 s->waiting = 2;
7d8406be 982 lsi_do_dma(s, 1);
a917d384
PB		 983 if (s->waiting)
984 s->waiting = 3;
7d8406be
PB		 985 break;
986 case PHASE_DI:
a917d384 987 s->waiting = 2;
7d8406be 988 lsi_do_dma(s, 0);
a917d384
PB		 989 if (s->waiting)
990 s->waiting = 3;
7d8406be
PB		 991 break;
992 case PHASE_CMD:
993 lsi_do_command(s);
994 break;
995 case PHASE_ST:
996 lsi_do_status(s);
997 break;
998 case PHASE_MO:
999 lsi_do_msgout(s);
1000 break;
1001 case PHASE_MI:
1002 lsi_do_msgin(s);
1003 break;
1004 default:
1005 BADF("Unimplemented phase %d\n", s->sstat1 & PHASE_MASK);
1006 exit(1);
1007 }
1008 s->dfifo = s->dbc & 0xff;
1009 s->ctest5 = (s->ctest5 & 0xfc) | ((s->dbc >> 8) & 3);
1010 s->sbc = s->dbc;
1011 s->rbc -= s->dbc;
1012 s->ua = addr + s->dbc;
7d8406be
PB		 1013 break;
1014
1015 case 1: /* IO or Read/Write instruction. */
1016 opcode = (insn >> 27) & 7;
1017 if (opcode < 5) {
1018 uint32_t id;
1019
1020 if (insn & (1 << 25)) {
1021 id = read_dword(s, s->dsa + sxt24(insn));
1022 } else {
1023 id = addr;
1024 }
1025 id = (id >> 16) & 0xf;
1026 if (insn & (1 << 26)) {
1027 addr = s->dsp + sxt24(addr);
1028 }
1029 s->dnad = addr;
1030 switch (opcode) {
1031 case 0: /* Select */
a917d384
PB		 1032 s->sdid = id;
1033 if (s->current_dma_len && (s->ssid & 0xf) == id) {
1034 DPRINTF("Already reselected by target %d\n", id);
1035 break;
1036 }
7d8406be
PB		 1037 s->sstat0 |= LSI_SSTAT0_WOA;
1038 s->scntl1 &= ~LSI_SCNTL1_IARB;
7d8406be
PB		 1039 if (id >= LSI_MAX_DEVS || !s->scsi_dev[id]) {
1040 DPRINTF("Selected absent target %d\n", id);
1041 lsi_script_scsi_interrupt(s, 0, LSI_SIST1_STO);
1042 lsi_disconnect(s);
1043 break;
1044 }
1045 DPRINTF("Selected target %d%s\n",
1046 id, insn & (1 << 3) ? " ATN" : "");
1047 /* ??? Linux drivers compain when this is set. Maybe
1048 it only applies in low-level mode (unimplemented).
1049 lsi_script_scsi_interrupt(s, LSI_SIST0_CMP, 0); */
1050 s->current_dev = s->scsi_dev[id];
a917d384 1051 s->current_tag = id << 8;
7d8406be
PB		 1052 s->scntl1 |= LSI_SCNTL1_CON;
1053 if (insn & (1 << 3)) {
1054 s->socl |= LSI_SOCL_ATN;
1055 }
1056 lsi_set_phase(s, PHASE_MO);
1057 break;
1058 case 1: /* Disconnect */
1059 DPRINTF("Wait Disconect\n");
1060 s->scntl1 &= ~LSI_SCNTL1_CON;
1061 break;
1062 case 2: /* Wait Reselect */
a917d384 1063 lsi_wait_reselect(s);
7d8406be
PB		 1064 break;
1065 case 3: /* Set */
1066 DPRINTF("Set%s%s%s%s\n",
1067 insn & (1 << 3) ? " ATN" : "",
1068 insn & (1 << 6) ? " ACK" : "",
1069 insn & (1 << 9) ? " TM" : "",
1070 insn & (1 << 10) ? " CC" : "");
1071 if (insn & (1 << 3)) {
1072 s->socl |= LSI_SOCL_ATN;
1073 lsi_set_phase(s, PHASE_MO);
1074 }
1075 if (insn & (1 << 9)) {
1076 BADF("Target mode not implemented\n");
1077 exit(1);
1078 }
1079 if (insn & (1 << 10))
1080 s->carry = 1;
1081 break;
1082 case 4: /* Clear */
1083 DPRINTF("Clear%s%s%s%s\n",
1084 insn & (1 << 3) ? " ATN" : "",
1085 insn & (1 << 6) ? " ACK" : "",
1086 insn & (1 << 9) ? " TM" : "",
1087 insn & (1 << 10) ? " CC" : "");
1088 if (insn & (1 << 3)) {
1089 s->socl &= ~LSI_SOCL_ATN;
1090 }
1091 if (insn & (1 << 10))
1092 s->carry = 0;
1093 break;
1094 }
1095 } else {
1096 uint8_t op0;
1097 uint8_t op1;
1098 uint8_t data8;
1099 int reg;
1100 int operator;
1101#ifdef DEBUG_LSI
1102 static const char *opcode_names[3] =
1103 {"Write", "Read", "Read-Modify-Write"};
1104 static const char *operator_names[8] =
1105 {"MOV", "SHL", "OR", "XOR", "AND", "SHR", "ADD", "ADC"};
1106#endif
1107
1108 reg = ((insn >> 16) & 0x7f) | (insn & 0x80);
1109 data8 = (insn >> 8) & 0xff;
1110 opcode = (insn >> 27) & 7;
1111 operator = (insn >> 24) & 7;
a917d384 1112 DPRINTF("%s reg 0x%x %s data8=0x%02x sfbr=0x%02x%s\n",
7d8406be 1113 opcode_names[opcode - 5], reg,
a917d384 1114 operator_names[operator], data8, s->sfbr,
7d8406be
PB		 1115 (insn & (1 << 23)) ? " SFBR" : "");
1116 op0 = op1 = 0;
1117 switch (opcode) {
1118 case 5: /* From SFBR */
1119 op0 = s->sfbr;
1120 op1 = data8;
1121 break;
1122 case 6: /* To SFBR */
1123 if (operator)
1124 op0 = lsi_reg_readb(s, reg);
1125 op1 = data8;
1126 break;
1127 case 7: /* Read-modify-write */
1128 if (operator)
1129 op0 = lsi_reg_readb(s, reg);
1130 if (insn & (1 << 23)) {
1131 op1 = s->sfbr;
1132 } else {
1133 op1 = data8;
1134 }
1135 break;
1136 }
1137
1138 switch (operator) {
1139 case 0: /* move */
1140 op0 = op1;
1141 break;
1142 case 1: /* Shift left */
1143 op1 = op0 >> 7;
1144 op0 = (op0 << 1) | s->carry;
1145 s->carry = op1;
1146 break;
1147 case 2: /* OR */
1148 op0 |= op1;
1149 break;
1150 case 3: /* XOR */
dcfb9014 1151 op0 ^= op1;
7d8406be
PB		 1152 break;
1153 case 4: /* AND */
1154 op0 &= op1;
1155 break;
1156 case 5: /* SHR */
1157 op1 = op0 & 1;
1158 op0 = (op0 >> 1) | (s->carry << 7);
687fa640 1159 s->carry = op1;
7d8406be
PB		 1160 break;
1161 case 6: /* ADD */
1162 op0 += op1;
1163 s->carry = op0 < op1;
1164 break;
1165 case 7: /* ADC */
1166 op0 += op1 + s->carry;
1167 if (s->carry)
1168 s->carry = op0 <= op1;
1169 else
1170 s->carry = op0 < op1;
1171 break;
1172 }
1173
1174 switch (opcode) {
1175 case 5: /* From SFBR */
1176 case 7: /* Read-modify-write */
1177 lsi_reg_writeb(s, reg, op0);
1178 break;
1179 case 6: /* To SFBR */
1180 s->sfbr = op0;
1181 break;
1182 }
1183 }
1184 break;
1185
1186 case 2: /* Transfer Control. */
1187 {
1188 int cond;
1189 int jmp;
1190
1191 if ((insn & 0x002e0000) == 0) {
1192 DPRINTF("NOP\n");
1193 break;
1194 }
1195 if (s->sist1 & LSI_SIST1_STO) {
1196 DPRINTF("Delayed select timeout\n");
1197 lsi_stop_script(s);
1198 break;
1199 }
1200 cond = jmp = (insn & (1 << 19)) != 0;
1201 if (cond == jmp && (insn & (1 << 21))) {
1202 DPRINTF("Compare carry %d\n", s->carry == jmp);
1203 cond = s->carry != 0;
1204 }
1205 if (cond == jmp && (insn & (1 << 17))) {
1206 DPRINTF("Compare phase %d %c= %d\n",
1207 (s->sstat1 & PHASE_MASK),
1208 jmp ? '=' : '!',
1209 ((insn >> 24) & 7));
1210 cond = (s->sstat1 & PHASE_MASK) == ((insn >> 24) & 7);
1211 }
1212 if (cond == jmp && (insn & (1 << 18))) {
1213 uint8_t mask;
1214
1215 mask = (~insn >> 8) & 0xff;
1216 DPRINTF("Compare data 0x%x & 0x%x %c= 0x%x\n",
1217 s->sfbr, mask, jmp ? '=' : '!', insn & mask);
1218 cond = (s->sfbr & mask) == (insn & mask);
1219 }
1220 if (cond == jmp) {
1221 if (insn & (1 << 23)) {
1222 /* Relative address. */
1223 addr = s->dsp + sxt24(addr);
1224 }
1225 switch ((insn >> 27) & 7) {
1226 case 0: /* Jump */
1227 DPRINTF("Jump to 0x%08x\n", addr);
1228 s->dsp = addr;
1229 break;
1230 case 1: /* Call */
1231 DPRINTF("Call 0x%08x\n", addr);
1232 s->temp = s->dsp;
1233 s->dsp = addr;
1234 break;
1235 case 2: /* Return */
1236 DPRINTF("Return to 0x%08x\n", s->temp);
1237 s->dsp = s->temp;
1238 break;
1239 case 3: /* Interrupt */
1240 DPRINTF("Interrupt 0x%08x\n", s->dsps);
1241 if ((insn & (1 << 20)) != 0) {
1242 s->istat0 |= LSI_ISTAT0_INTF;
1243 lsi_update_irq(s);
1244 } else {
1245 lsi_script_dma_interrupt(s, LSI_DSTAT_SIR);
1246 }
1247 break;
1248 default:
1249 DPRINTF("Illegal transfer control\n");
1250 lsi_script_dma_interrupt(s, LSI_DSTAT_IID);
1251 break;
1252 }
1253 } else {
1254 DPRINTF("Control condition failed\n");
1255 }
1256 }
1257 break;
1258
1259 case 3:
1260 if ((insn & (1 << 29)) == 0) {
1261 /* Memory move. */
1262 uint32_t dest;
1263 /* ??? The docs imply the destination address is loaded into
1264 the TEMP register. However the Linux drivers rely on
1265 the value being presrved. */
1266 dest = read_dword(s, s->dsp);
1267 s->dsp += 4;
1268 lsi_memcpy(s, dest, addr, insn & 0xffffff);
1269 } else {
1270 uint8_t data[7];
1271 int reg;
1272 int n;
1273 int i;
1274
1275 if (insn & (1 << 28)) {
1276 addr = s->dsa + sxt24(addr);
1277 }
1278 n = (insn & 7);
1279 reg = (insn >> 16) & 0xff;
1280 if (insn & (1 << 24)) {
7d8406be 1281 cpu_physical_memory_read(addr, data, n);
a917d384
PB		 1282 DPRINTF("Load reg 0x%x size %d addr 0x%08x = %08x\n", reg, n,
1283 addr, *(int *)data);
7d8406be
PB		 1284 for (i = 0; i < n; i++) {
1285 lsi_reg_writeb(s, reg + i, data[i]);
1286 }
1287 } else {
1288 DPRINTF("Store reg 0x%x size %d addr 0x%08x\n", reg, n, addr);
1289 for (i = 0; i < n; i++) {
1290 data[i] = lsi_reg_readb(s, reg + i);
1291 }
1292 cpu_physical_memory_write(addr, data, n);
1293 }
1294 }
1295 }
ee4d919f 1296 if (insn_processed > 10000 && !s->waiting) {
64c68080
PB		 1297 /* Some windows drivers make the device spin waiting for a memory
1298 location to change. If we have been executed a lot of code then
1299 assume this is the case and force an unexpected device disconnect.
1300 This is apparently sufficient to beat the drivers into submission.
1301 */
ee4d919f
AL		 1302 if (!(s->sien0 & LSI_SIST0_UDC))
1303 fprintf(stderr, "inf. loop with UDC masked\n");
1304 lsi_script_scsi_interrupt(s, LSI_SIST0_UDC, 0);
1305 lsi_disconnect(s);
1306 } else if (s->istat1 & LSI_ISTAT1_SRUN && !s->waiting) {
7d8406be
PB		 1307 if (s->dcntl & LSI_DCNTL_SSM) {
1308 lsi_script_dma_interrupt(s, LSI_DSTAT_SSI);
1309 } else {
1310 goto again;
1311 }
1312 }
1313 DPRINTF("SCRIPTS execution stopped\n");
1314}
1315
1316static uint8_t lsi_reg_readb(LSIState *s, int offset)
1317{
1318 uint8_t tmp;
75f76531
AJ		 1319#define CASE_GET_REG24(name, addr) \
1320 case addr: return s->name & 0xff; \
1321 case addr + 1: return (s->name >> 8) & 0xff; \
1322 case addr + 2: return (s->name >> 16) & 0xff;
1323
7d8406be
PB		 1324#define CASE_GET_REG32(name, addr) \
1325 case addr: return s->name & 0xff; \
1326 case addr + 1: return (s->name >> 8) & 0xff; \
1327 case addr + 2: return (s->name >> 16) & 0xff; \
1328 case addr + 3: return (s->name >> 24) & 0xff;
1329
1330#ifdef DEBUG_LSI_REG
1331 DPRINTF("Read reg %x\n", offset);
1332#endif
1333 switch (offset) {
1334 case 0x00: /* SCNTL0 */
1335 return s->scntl0;
1336 case 0x01: /* SCNTL1 */
1337 return s->scntl1;
1338 case 0x02: /* SCNTL2 */
1339 return s->scntl2;
1340 case 0x03: /* SCNTL3 */
1341 return s->scntl3;
1342 case 0x04: /* SCID */
1343 return s->scid;
1344 case 0x05: /* SXFER */
1345 return s->sxfer;
1346 case 0x06: /* SDID */
1347 return s->sdid;
1348 case 0x07: /* GPREG0 */
1349 return 0x7f;
985a03b0
TS		 1350 case 0x08: /* Revision ID */
1351 return 0x00;
a917d384
PB		 1352 case 0xa: /* SSID */
1353 return s->ssid;
7d8406be
PB		 1354 case 0xb: /* SBCL */
1355 /* ??? This is not correct. However it's (hopefully) only
1356 used for diagnostics, so should be ok. */
1357 return 0;
1358 case 0xc: /* DSTAT */
1359 tmp = s->dstat | 0x80;
1360 if ((s->istat0 & LSI_ISTAT0_INTF) == 0)
1361 s->dstat = 0;
1362 lsi_update_irq(s);
1363 return tmp;
1364 case 0x0d: /* SSTAT0 */
1365 return s->sstat0;
1366 case 0x0e: /* SSTAT1 */
1367 return s->sstat1;
1368 case 0x0f: /* SSTAT2 */
1369 return s->scntl1 & LSI_SCNTL1_CON ? 0 : 2;
1370 CASE_GET_REG32(dsa, 0x10)
1371 case 0x14: /* ISTAT0 */
1372 return s->istat0;
ecabe8cc
AL		 1373 case 0x15: /* ISTAT1 */
1374 return s->istat1;
7d8406be
PB		 1375 case 0x16: /* MBOX0 */
1376 return s->mbox0;
1377 case 0x17: /* MBOX1 */
1378 return s->mbox1;
1379 case 0x18: /* CTEST0 */
1380 return 0xff;
1381 case 0x19: /* CTEST1 */
1382 return 0;
1383 case 0x1a: /* CTEST2 */
9167a69a 1384 tmp = s->ctest2 | LSI_CTEST2_DACK | LSI_CTEST2_CM;
7d8406be
PB		 1385 if (s->istat0 & LSI_ISTAT0_SIGP) {
1386 s->istat0 &= ~LSI_ISTAT0_SIGP;
1387 tmp |= LSI_CTEST2_SIGP;
1388 }
1389 return tmp;
1390 case 0x1b: /* CTEST3 */
1391 return s->ctest3;
1392 CASE_GET_REG32(temp, 0x1c)
1393 case 0x20: /* DFIFO */
1394 return 0;
1395 case 0x21: /* CTEST4 */
1396 return s->ctest4;
1397 case 0x22: /* CTEST5 */
1398 return s->ctest5;
985a03b0
TS		 1399 case 0x23: /* CTEST6 */
1400 return 0;
75f76531 1401 CASE_GET_REG24(dbc, 0x24)
7d8406be
PB		 1402 case 0x27: /* DCMD */
1403 return s->dcmd;
1404 CASE_GET_REG32(dsp, 0x2c)
1405 CASE_GET_REG32(dsps, 0x30)
1406 CASE_GET_REG32(scratch[0], 0x34)
1407 case 0x38: /* DMODE */
1408 return s->dmode;
1409 case 0x39: /* DIEN */
1410 return s->dien;
1411 case 0x3b: /* DCNTL */
1412 return s->dcntl;
1413 case 0x40: /* SIEN0 */
1414 return s->sien0;
1415 case 0x41: /* SIEN1 */
1416 return s->sien1;
1417 case 0x42: /* SIST0 */
1418 tmp = s->sist0;
1419 s->sist0 = 0;
1420 lsi_update_irq(s);
1421 return tmp;
1422 case 0x43: /* SIST1 */
1423 tmp = s->sist1;
1424 s->sist1 = 0;
1425 lsi_update_irq(s);
1426 return tmp;
9167a69a
AZ		 1427 case 0x46: /* MACNTL */
1428 return 0x0f;
7d8406be
PB		 1429 case 0x47: /* GPCNTL0 */
1430 return 0x0f;
1431 case 0x48: /* STIME0 */
1432 return s->stime0;
1433 case 0x4a: /* RESPID0 */
1434 return s->respid0;
1435 case 0x4b: /* RESPID1 */
1436 return s->respid1;
1437 case 0x4d: /* STEST1 */
1438 return s->stest1;
1439 case 0x4e: /* STEST2 */
1440 return s->stest2;
1441 case 0x4f: /* STEST3 */
1442 return s->stest3;
a917d384
PB		 1443 case 0x50: /* SIDL */
1444 /* This is needed by the linux drivers. We currently only update it
1445 during the MSG IN phase. */
1446 return s->sidl;
7d8406be
PB		 1447 case 0x52: /* STEST4 */
1448 return 0xe0;
1449 case 0x56: /* CCNTL0 */
1450 return s->ccntl0;
1451 case 0x57: /* CCNTL1 */
1452 return s->ccntl1;
a917d384
PB		 1453 case 0x58: /* SBDL */
1454 /* Some drivers peek at the data bus during the MSG IN phase. */
1455 if ((s->sstat1 & PHASE_MASK) == PHASE_MI)
1456 return s->msg[0];
1457 return 0;
1458 case 0x59: /* SBDL high */
7d8406be
PB		 1459 return 0;
1460 CASE_GET_REG32(mmrs, 0xa0)
1461 CASE_GET_REG32(mmws, 0xa4)
1462 CASE_GET_REG32(sfs, 0xa8)
1463 CASE_GET_REG32(drs, 0xac)
1464 CASE_GET_REG32(sbms, 0xb0)
ab57d967 1465 CASE_GET_REG32(dbms, 0xb4)
7d8406be
PB		 1466 CASE_GET_REG32(dnad64, 0xb8)
1467 CASE_GET_REG32(pmjad1, 0xc0)
1468 CASE_GET_REG32(pmjad2, 0xc4)
1469 CASE_GET_REG32(rbc, 0xc8)
1470 CASE_GET_REG32(ua, 0xcc)
1471 CASE_GET_REG32(ia, 0xd4)
1472 CASE_GET_REG32(sbc, 0xd8)
1473 CASE_GET_REG32(csbc, 0xdc)
1474 }
1475 if (offset >= 0x5c && offset < 0xa0) {
1476 int n;
1477 int shift;
1478 n = (offset - 0x58) >> 2;
1479 shift = (offset & 3) * 8;
1480 return (s->scratch[n] >> shift) & 0xff;
1481 }
1482 BADF("readb 0x%x\n", offset);
1483 exit(1);
75f76531 1484#undef CASE_GET_REG24
7d8406be
PB		 1485#undef CASE_GET_REG32
1486}
1487
1488static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val)
1489{
1490#define CASE_SET_REG32(name, addr) \
1491 case addr : s->name &= 0xffffff00; s->name |= val; break; \
1492 case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8; break; \
1493 case addr + 2: s->name &= 0xff00ffff; s->name |= val << 16; break; \
1494 case addr + 3: s->name &= 0x00ffffff; s->name |= val << 24; break;
1495
1496#ifdef DEBUG_LSI_REG
1497 DPRINTF("Write reg %x = %02x\n", offset, val);
1498#endif
1499 switch (offset) {
1500 case 0x00: /* SCNTL0 */
1501 s->scntl0 = val;
1502 if (val & LSI_SCNTL0_START) {
1503 BADF("Start sequence not implemented\n");
1504 }
1505 break;
1506 case 0x01: /* SCNTL1 */
1507 s->scntl1 = val & ~LSI_SCNTL1_SST;
1508 if (val & LSI_SCNTL1_IARB) {
1509 BADF("Immediate Arbritration not implemented\n");
1510 }
1511 if (val & LSI_SCNTL1_RST) {
1512 s->sstat0 |= LSI_SSTAT0_RST;
1513 lsi_script_scsi_interrupt(s, LSI_SIST0_RST, 0);
1514 } else {
1515 s->sstat0 &= ~LSI_SSTAT0_RST;
1516 }
1517 break;
1518 case 0x02: /* SCNTL2 */
1519 val &= ~(LSI_SCNTL2_WSR | LSI_SCNTL2_WSS);
3d834c78 1520 s->scntl2 = val;
7d8406be
PB		 1521 break;
1522 case 0x03: /* SCNTL3 */
1523 s->scntl3 = val;
1524 break;
1525 case 0x04: /* SCID */
1526 s->scid = val;
1527 break;
1528 case 0x05: /* SXFER */
1529 s->sxfer = val;
1530 break;
a917d384
PB		 1531 case 0x06: /* SDID */
1532 if ((val & 0xf) != (s->ssid & 0xf))
1533 BADF("Destination ID does not match SSID\n");
1534 s->sdid = val & 0xf;
1535 break;
7d8406be
PB		 1536 case 0x07: /* GPREG0 */
1537 break;
a917d384
PB		 1538 case 0x08: /* SFBR */
1539 /* The CPU is not allowed to write to this register. However the
1540 SCRIPTS register move instructions are. */
1541 s->sfbr = val;
1542 break;
9167a69a
AZ		 1543 case 0x0a: case 0x0b:
1544 /* Openserver writes to these readonly registers on startup */
1545 return;
7d8406be
PB		 1546 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1547 /* Linux writes to these readonly registers on startup. */
1548 return;
1549 CASE_SET_REG32(dsa, 0x10)
1550 case 0x14: /* ISTAT0 */
1551 s->istat0 = (s->istat0 & 0x0f) | (val & 0xf0);
1552 if (val & LSI_ISTAT0_ABRT) {
1553 lsi_script_dma_interrupt(s, LSI_DSTAT_ABRT);
1554 }
1555 if (val & LSI_ISTAT0_INTF) {
1556 s->istat0 &= ~LSI_ISTAT0_INTF;
1557 lsi_update_irq(s);
1558 }
4d611c9a 1559 if (s->waiting == 1 && val & LSI_ISTAT0_SIGP) {
7d8406be
PB		 1560 DPRINTF("Woken by SIGP\n");
1561 s->waiting = 0;
1562 s->dsp = s->dnad;
1563 lsi_execute_script(s);
1564 }
1565 if (val & LSI_ISTAT0_SRST) {
1566 lsi_soft_reset(s);
1567 }
92d88ecb 1568 break;
7d8406be
PB		 1569 case 0x16: /* MBOX0 */
1570 s->mbox0 = val;
92d88ecb 1571 break;
7d8406be
PB		 1572 case 0x17: /* MBOX1 */
1573 s->mbox1 = val;
92d88ecb 1574 break;
9167a69a
AZ		 1575 case 0x1a: /* CTEST2 */
1576 s->ctest2 = val & LSI_CTEST2_PCICIE;
1577 break;
7d8406be
PB		 1578 case 0x1b: /* CTEST3 */
1579 s->ctest3 = val & 0x0f;
1580 break;
1581 CASE_SET_REG32(temp, 0x1c)
1582 case 0x21: /* CTEST4 */
1583 if (val & 7) {
1584 BADF("Unimplemented CTEST4-FBL 0x%x\n", val);
1585 }
1586 s->ctest4 = val;
1587 break;
1588 case 0x22: /* CTEST5 */
1589 if (val & (LSI_CTEST5_ADCK | LSI_CTEST5_BBCK)) {
1590 BADF("CTEST5 DMA increment not implemented\n");
1591 }
1592 s->ctest5 = val;
1593 break;
3d834c78 1594 case 0x2c: /* DSP[0:7] */
7d8406be
PB		 1595 s->dsp &= 0xffffff00;
1596 s->dsp |= val;
1597 break;
3d834c78 1598 case 0x2d: /* DSP[8:15] */
7d8406be
PB		 1599 s->dsp &= 0xffff00ff;
1600 s->dsp |= val << 8;
1601 break;
3d834c78 1602 case 0x2e: /* DSP[16:23] */
7d8406be
PB		 1603 s->dsp &= 0xff00ffff;
1604 s->dsp |= val << 16;
1605 break;
3d834c78 1606 case 0x2f: /* DSP[24:31] */
7d8406be
PB		 1607 s->dsp &= 0x00ffffff;
1608 s->dsp |= val << 24;
1609 if ((s->dmode & LSI_DMODE_MAN) == 0
1610 && (s->istat1 & LSI_ISTAT1_SRUN) == 0)
1611 lsi_execute_script(s);
1612 break;
1613 CASE_SET_REG32(dsps, 0x30)
1614 CASE_SET_REG32(scratch[0], 0x34)
1615 case 0x38: /* DMODE */
1616 if (val & (LSI_DMODE_SIOM | LSI_DMODE_DIOM)) {
1617 BADF("IO mappings not implemented\n");
1618 }
1619 s->dmode = val;
1620 break;
1621 case 0x39: /* DIEN */
1622 s->dien = val;
1623 lsi_update_irq(s);
1624 break;
1625 case 0x3b: /* DCNTL */
1626 s->dcntl = val & ~(LSI_DCNTL_PFF | LSI_DCNTL_STD);
1627 if ((val & LSI_DCNTL_STD) && (s->istat1 & LSI_ISTAT1_SRUN) == 0)
1628 lsi_execute_script(s);
1629 break;
1630 case 0x40: /* SIEN0 */
1631 s->sien0 = val;
1632 lsi_update_irq(s);
1633 break;
1634 case 0x41: /* SIEN1 */
1635 s->sien1 = val;
1636 lsi_update_irq(s);
1637 break;
1638 case 0x47: /* GPCNTL0 */
1639 break;
1640 case 0x48: /* STIME0 */
1641 s->stime0 = val;
1642 break;
1643 case 0x49: /* STIME1 */
1644 if (val & 0xf) {
1645 DPRINTF("General purpose timer not implemented\n");
1646 /* ??? Raising the interrupt immediately seems to be sufficient
1647 to keep the FreeBSD driver happy. */
1648 lsi_script_scsi_interrupt(s, 0, LSI_SIST1_GEN);
1649 }
1650 break;
1651 case 0x4a: /* RESPID0 */
1652 s->respid0 = val;
1653 break;
1654 case 0x4b: /* RESPID1 */
1655 s->respid1 = val;
1656 break;
1657 case 0x4d: /* STEST1 */
1658 s->stest1 = val;
1659 break;
1660 case 0x4e: /* STEST2 */
1661 if (val & 1) {
1662 BADF("Low level mode not implemented\n");
1663 }
1664 s->stest2 = val;
1665 break;
1666 case 0x4f: /* STEST3 */
1667 if (val & 0x41) {
1668 BADF("SCSI FIFO test mode not implemented\n");
1669 }
1670 s->stest3 = val;
1671 break;
1672 case 0x56: /* CCNTL0 */
1673 s->ccntl0 = val;
1674 break;
1675 case 0x57: /* CCNTL1 */
1676 s->ccntl1 = val;
1677 break;
1678 CASE_SET_REG32(mmrs, 0xa0)
1679 CASE_SET_REG32(mmws, 0xa4)
1680 CASE_SET_REG32(sfs, 0xa8)
1681 CASE_SET_REG32(drs, 0xac)
1682 CASE_SET_REG32(sbms, 0xb0)
ab57d967 1683 CASE_SET_REG32(dbms, 0xb4)
7d8406be
PB		 1684 CASE_SET_REG32(dnad64, 0xb8)
1685 CASE_SET_REG32(pmjad1, 0xc0)
1686 CASE_SET_REG32(pmjad2, 0xc4)
1687 CASE_SET_REG32(rbc, 0xc8)
1688 CASE_SET_REG32(ua, 0xcc)
1689 CASE_SET_REG32(ia, 0xd4)
1690 CASE_SET_REG32(sbc, 0xd8)
1691 CASE_SET_REG32(csbc, 0xdc)
1692 default:
1693 if (offset >= 0x5c && offset < 0xa0) {
1694 int n;
1695 int shift;
1696 n = (offset - 0x58) >> 2;
1697 shift = (offset & 3) * 8;
1698 s->scratch[n] &= ~(0xff << shift);
1699 s->scratch[n] |= (val & 0xff) << shift;
1700 } else {
1701 BADF("Unhandled writeb 0x%x = 0x%x\n", offset, val);
1702 }
1703 }
1704#undef CASE_SET_REG32
1705}
1706
1707static void lsi_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1708{
1709 LSIState *s = (LSIState *)opaque;
1710
1711 lsi_reg_writeb(s, addr & 0xff, val);
1712}
1713
1714static void lsi_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1715{
1716 LSIState *s = (LSIState *)opaque;
1717
1718 addr &= 0xff;
1719 lsi_reg_writeb(s, addr, val & 0xff);
1720 lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1721}
1722
1723static void lsi_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1724{
1725 LSIState *s = (LSIState *)opaque;
1726
1727 addr &= 0xff;
1728 lsi_reg_writeb(s, addr, val & 0xff);
1729 lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1730 lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff);
1731 lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff);
1732}
1733
1734static uint32_t lsi_mmio_readb(void *opaque, target_phys_addr_t addr)
1735{
1736 LSIState *s = (LSIState *)opaque;
1737
1738 return lsi_reg_readb(s, addr & 0xff);
1739}
1740
1741static uint32_t lsi_mmio_readw(void *opaque, target_phys_addr_t addr)
1742{
1743 LSIState *s = (LSIState *)opaque;
1744 uint32_t val;
1745
1746 addr &= 0xff;
1747 val = lsi_reg_readb(s, addr);
1748 val |= lsi_reg_readb(s, addr + 1) << 8;
1749 return val;
1750}
1751
1752static uint32_t lsi_mmio_readl(void *opaque, target_phys_addr_t addr)
1753{
1754 LSIState *s = (LSIState *)opaque;
1755 uint32_t val;
1756 addr &= 0xff;
1757 val = lsi_reg_readb(s, addr);
1758 val |= lsi_reg_readb(s, addr + 1) << 8;
1759 val |= lsi_reg_readb(s, addr + 2) << 16;
1760 val |= lsi_reg_readb(s, addr + 3) << 24;
1761 return val;
1762}
1763
1764static CPUReadMemoryFunc *lsi_mmio_readfn[3] = {
1765 lsi_mmio_readb,
1766 lsi_mmio_readw,
1767 lsi_mmio_readl,
1768};
1769
1770static CPUWriteMemoryFunc *lsi_mmio_writefn[3] = {
1771 lsi_mmio_writeb,
1772 lsi_mmio_writew,
1773 lsi_mmio_writel,
1774};
1775
1776static void lsi_ram_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1777{
1778 LSIState *s = (LSIState *)opaque;
1779 uint32_t newval;
1780 int shift;
1781
1782 addr &= 0x1fff;
1783 newval = s->script_ram[addr >> 2];
1784 shift = (addr & 3) * 8;
1785 newval &= ~(0xff << shift);
1786 newval |= val << shift;
1787 s->script_ram[addr >> 2] = newval;
1788}
1789
1790static void lsi_ram_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1791{
1792 LSIState *s = (LSIState *)opaque;
1793 uint32_t newval;
1794
1795 addr &= 0x1fff;
1796 newval = s->script_ram[addr >> 2];
1797 if (addr & 2) {
1798 newval = (newval & 0xffff) | (val << 16);
1799 } else {
1800 newval = (newval & 0xffff0000) | val;
1801 }
1802 s->script_ram[addr >> 2] = newval;
1803}
1804
1805
1806static void lsi_ram_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1807{
1808 LSIState *s = (LSIState *)opaque;
1809
1810 addr &= 0x1fff;
1811 s->script_ram[addr >> 2] = val;
1812}
1813
1814static uint32_t lsi_ram_readb(void *opaque, target_phys_addr_t addr)
1815{
1816 LSIState *s = (LSIState *)opaque;
1817 uint32_t val;
1818
1819 addr &= 0x1fff;
1820 val = s->script_ram[addr >> 2];
1821 val >>= (addr & 3) * 8;
1822 return val & 0xff;
1823}
1824
1825static uint32_t lsi_ram_readw(void *opaque, target_phys_addr_t addr)
1826{
1827 LSIState *s = (LSIState *)opaque;
1828 uint32_t val;
1829
1830 addr &= 0x1fff;
1831 val = s->script_ram[addr >> 2];
1832 if (addr & 2)
1833 val >>= 16;
1834 return le16_to_cpu(val);
1835}
1836
1837static uint32_t lsi_ram_readl(void *opaque, target_phys_addr_t addr)
1838{
1839 LSIState *s = (LSIState *)opaque;
1840
1841 addr &= 0x1fff;
1842 return le32_to_cpu(s->script_ram[addr >> 2]);
1843}
1844
1845static CPUReadMemoryFunc *lsi_ram_readfn[3] = {
1846 lsi_ram_readb,
1847 lsi_ram_readw,
1848 lsi_ram_readl,
1849};
1850
1851static CPUWriteMemoryFunc *lsi_ram_writefn[3] = {
1852 lsi_ram_writeb,
1853 lsi_ram_writew,
1854 lsi_ram_writel,
1855};
1856
1857static uint32_t lsi_io_readb(void *opaque, uint32_t addr)
1858{
1859 LSIState *s = (LSIState *)opaque;
1860 return lsi_reg_readb(s, addr & 0xff);
1861}
1862
1863static uint32_t lsi_io_readw(void *opaque, uint32_t addr)
1864{
1865 LSIState *s = (LSIState *)opaque;
1866 uint32_t val;
1867 addr &= 0xff;
1868 val = lsi_reg_readb(s, addr);
1869 val |= lsi_reg_readb(s, addr + 1) << 8;
1870 return val;
1871}
1872
1873static uint32_t lsi_io_readl(void *opaque, uint32_t addr)
1874{
1875 LSIState *s = (LSIState *)opaque;
1876 uint32_t val;
1877 addr &= 0xff;
1878 val = lsi_reg_readb(s, addr);
1879 val |= lsi_reg_readb(s, addr + 1) << 8;
1880 val |= lsi_reg_readb(s, addr + 2) << 16;
1881 val |= lsi_reg_readb(s, addr + 3) << 24;
1882 return val;
1883}
1884
1885static void lsi_io_writeb(void *opaque, uint32_t addr, uint32_t val)
1886{
1887 LSIState *s = (LSIState *)opaque;
1888 lsi_reg_writeb(s, addr & 0xff, val);
1889}
1890
1891static void lsi_io_writew(void *opaque, uint32_t addr, uint32_t val)
1892{
1893 LSIState *s = (LSIState *)opaque;
1894 addr &= 0xff;
1895 lsi_reg_writeb(s, addr, val & 0xff);
1896 lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1897}
1898
1899static void lsi_io_writel(void *opaque, uint32_t addr, uint32_t val)
1900{
1901 LSIState *s = (LSIState *)opaque;
1902 addr &= 0xff;
1903 lsi_reg_writeb(s, addr, val & 0xff);
1904 lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1905 lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff);
dcfb9014 1906 lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff);
7d8406be
PB		 1907}
1908
5fafdf24 1909static void lsi_io_mapfunc(PCIDevice *pci_dev, int region_num,
7d8406be
PB		 1910 uint32_t addr, uint32_t size, int type)
1911{
1912 LSIState *s = (LSIState *)pci_dev;
1913
1914 DPRINTF("Mapping IO at %08x\n", addr);
1915
1916 register_ioport_write(addr, 256, 1, lsi_io_writeb, s);
1917 register_ioport_read(addr, 256, 1, lsi_io_readb, s);
1918 register_ioport_write(addr, 256, 2, lsi_io_writew, s);
1919 register_ioport_read(addr, 256, 2, lsi_io_readw, s);
1920 register_ioport_write(addr, 256, 4, lsi_io_writel, s);
1921 register_ioport_read(addr, 256, 4, lsi_io_readl, s);
1922}
1923
5fafdf24 1924static void lsi_ram_mapfunc(PCIDevice *pci_dev, int region_num,
7d8406be
PB		 1925 uint32_t addr, uint32_t size, int type)
1926{
1927 LSIState *s = (LSIState *)pci_dev;
1928
1929 DPRINTF("Mapping ram at %08x\n", addr);
1930 s->script_ram_base = addr;
1931 cpu_register_physical_memory(addr + 0, 0x2000, s->ram_io_addr);
1932}
1933
5fafdf24 1934static void lsi_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
7d8406be
PB		 1935 uint32_t addr, uint32_t size, int type)
1936{
1937 LSIState *s = (LSIState *)pci_dev;
1938
1939 DPRINTF("Mapping registers at %08x\n", addr);
1940 cpu_register_physical_memory(addr + 0, 0x400, s->mmio_io_addr);
1941}
1942
9be5dafe 1943void lsi_scsi_attach(DeviceState *host, BlockDriverState *bd, int id)
7d8406be 1944{
9be5dafe 1945 LSIState *s = (LSIState *)host;
7d8406be
PB		 1946
1947 if (id < 0) {
1948 for (id = 0; id < LSI_MAX_DEVS; id++) {
1949 if (s->scsi_dev[id] == NULL)
1950 break;
1951 }
1952 }
1953 if (id >= LSI_MAX_DEVS) {
1954 BADF("Bad Device ID %d\n", id);
1955 return;
1956 }
1957 if (s->scsi_dev[id]) {
1958 DPRINTF("Destroying device %d\n", id);
8ccc2ace 1959 s->scsi_dev[id]->destroy(s->scsi_dev[id]);
7d8406be
PB		 1960 }
1961 DPRINTF("Attaching block device %d\n", id);
985a03b0
TS		 1962 s->scsi_dev[id] = scsi_generic_init(bd, 1, lsi_command_complete, s);
1963 if (s->scsi_dev[id] == NULL)
1964 s->scsi_dev[id] = scsi_disk_init(bd, 1, lsi_command_complete, s);
b0a7b120 1965 bd->private = &s->pci_dev;
7d8406be
PB		 1966}
1967
4b09be85
AL		 1968static int lsi_scsi_uninit(PCIDevice *d)
1969{
1970 LSIState *s = (LSIState *) d;
1971
1972 cpu_unregister_io_memory(s->mmio_io_addr);
1973 cpu_unregister_io_memory(s->ram_io_addr);
1974
1975 qemu_free(s->queue);
1976
1977 return 0;
1978}
1979
9be5dafe 1980static void lsi_scsi_init(PCIDevice *dev)
7d8406be 1981{
9be5dafe 1982 LSIState *s = (LSIState *)dev;
deb54399 1983 uint8_t *pci_conf;
7d8406be 1984
deb54399
AL		 1985 pci_conf = s->pci_dev.config;
1986
9167a69a 1987 /* PCI Vendor ID (word) */
deb54399 1988 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_LSI_LOGIC);
9167a69a 1989 /* PCI device ID (word) */
deb54399 1990 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_LSI_53C895A);
9167a69a 1991 /* PCI base class code */
173a543b 1992 pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_SCSI);
9167a69a 1993 /* PCI subsystem ID */
deb54399
AL		 1994 pci_conf[0x2e] = 0x00;
1995 pci_conf[0x2f] = 0x10;
9167a69a 1996 /* PCI latency timer = 255 */
deb54399 1997 pci_conf[0x0d] = 0xff;
9167a69a 1998 /* Interrupt pin 1 */
deb54399 1999 pci_conf[0x3d] = 0x01;
7d8406be 2000
1eed09cb 2001 s->mmio_io_addr = cpu_register_io_memory(lsi_mmio_readfn,
7d8406be 2002 lsi_mmio_writefn, s);
1eed09cb 2003 s->ram_io_addr = cpu_register_io_memory(lsi_ram_readfn,
7d8406be
PB		 2004 lsi_ram_writefn, s);
2005
2006 pci_register_io_region((struct PCIDevice *)s, 0, 256,
2007 PCI_ADDRESS_SPACE_IO, lsi_io_mapfunc);
2008 pci_register_io_region((struct PCIDevice *)s, 1, 0x400,
2009 PCI_ADDRESS_SPACE_MEM, lsi_mmio_mapfunc);
2010 pci_register_io_region((struct PCIDevice *)s, 2, 0x2000,
2011 PCI_ADDRESS_SPACE_MEM, lsi_ram_mapfunc);
a917d384
PB		 2012 s->queue = qemu_malloc(sizeof(lsi_queue));
2013 s->queue_len = 1;
2014 s->active_commands = 0;
4b09be85 2015 s->pci_dev.unregister = lsi_scsi_uninit;
7d8406be
PB		 2016
2017 lsi_soft_reset(s);
2018
9be5dafe 2019 scsi_bus_new(&dev->qdev, lsi_scsi_attach);
7d8406be 2020}
9be5dafe
PB		 2021
2022static void lsi53c895a_register_devices(void)
2023{
2024 pci_qdev_register("lsi53c895a", sizeof(LSIState), lsi_scsi_init);
2025}
2026
2027device_init(lsi53c895a_register_devices);
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