[qemu.git] / hw / apb_pci.c

/*
 * QEMU Ultrasparc APB PCI host
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

/* XXX This file and most of its contents are somewhat misnamed.  The
   Ultrasparc PCI host is called the PCI Bus Module (PBM).  The APB is
   the secondary PCI bridge.  */

#include "sysbus.h"
#include "pci.h"
#include "pci_host.h"
#include "pci_bridge.h"
#include "pci_internals.h"
#include "rwhandler.h"
#include "apb_pci.h"
#include "sysemu.h"
#include "exec-memory.h"

/* debug APB */
//#define DEBUG_APB

#ifdef DEBUG_APB
#define APB_DPRINTF(fmt, ...) \
do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
#else
#define APB_DPRINTF(fmt, ...)
#endif

/*
 * Chipset docs:
 * PBM: "UltraSPARC IIi User's Manual",
 * http://www.sun.com/processors/manuals/805-0087.pdf
 *
 * APB: "Advanced PCI Bridge (APB) User's Manual",
 * http://www.sun.com/processors/manuals/805-1251.pdf
 */

#define PBM_PCI_IMR_MASK    0x7fffffff
#define PBM_PCI_IMR_ENABLED 0x80000000

#define POR          (1 << 31)
#define SOFT_POR     (1 << 30)
#define SOFT_XIR     (1 << 29)
#define BTN_POR      (1 << 28)
#define BTN_XIR      (1 << 27)
#define RESET_MASK   0xf8000000
#define RESET_WCMASK 0x98000000
#define RESET_WMASK  0x60000000

typedef struct APBState {
    SysBusDevice busdev;
    PCIBus      *bus;
    ReadWriteHandler pci_config_handler;
    uint32_t iommu[4];
    uint32_t pci_control[16];
    uint32_t pci_irq_map[8];
    uint32_t obio_irq_map[32];
    qemu_irq pci_irqs[32];
    uint32_t reset_control;
    unsigned int nr_resets;
} APBState;

static void apb_config_writel (void *opaque, target_phys_addr_t addr,
                               uint32_t val)
{
    APBState *s = opaque;

    APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);

    switch (addr & 0xffff) {
    case 0x30 ... 0x4f: /* DMA error registers */
        /* XXX: not implemented yet */
        break;
    case 0x200 ... 0x20b: /* IOMMU */
        s->iommu[(addr & 0xf) >> 2] = val;
        break;
    case 0x20c ... 0x3ff: /* IOMMU flush */
        break;
    case 0xc00 ... 0xc3f: /* PCI interrupt control */
        if (addr & 4) {
            s->pci_irq_map[(addr & 0x3f) >> 3] &= PBM_PCI_IMR_MASK;
            s->pci_irq_map[(addr & 0x3f) >> 3] |= val & ~PBM_PCI_IMR_MASK;
        }
        break;
    case 0x2000 ... 0x202f: /* PCI control */
        s->pci_control[(addr & 0x3f) >> 2] = val;
        break;
    case 0xf020 ... 0xf027: /* Reset control */
        if (addr & 4) {
            val &= RESET_MASK;
            s->reset_control &= ~(val & RESET_WCMASK);
            s->reset_control |= val & RESET_WMASK;
            if (val & SOFT_POR) {
                s->nr_resets = 0;
                qemu_system_reset_request();
            } else if (val & SOFT_XIR) {
                qemu_system_reset_request();
            }
        }
        break;
    case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
    case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
    case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
    case 0xf000 ... 0xf01f: /* FFB config, memory control */
        /* we don't care */
    default:
        break;
    }
}

static uint32_t apb_config_readl (void *opaque,
                                  target_phys_addr_t addr)
{
    APBState *s = opaque;
    uint32_t val;

    switch (addr & 0xffff) {
    case 0x30 ... 0x4f: /* DMA error registers */
        val = 0;
        /* XXX: not implemented yet */
        break;
    case 0x200 ... 0x20b: /* IOMMU */
        val = s->iommu[(addr & 0xf) >> 2];
        break;
    case 0x20c ... 0x3ff: /* IOMMU flush */
        val = 0;
        break;
    case 0xc00 ... 0xc3f: /* PCI interrupt control */
        if (addr & 4) {
            val = s->pci_irq_map[(addr & 0x3f) >> 3];
        } else {
            val = 0;
        }
        break;
    case 0x2000 ... 0x202f: /* PCI control */
        val = s->pci_control[(addr & 0x3f) >> 2];
        break;
    case 0xf020 ... 0xf027: /* Reset control */
        if (addr & 4) {
            val = s->reset_control;
        } else {
            val = 0;
        }
        break;
    case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
    case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
    case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
    case 0xf000 ... 0xf01f: /* FFB config, memory control */
        /* we don't care */
    default:
        val = 0;
        break;
    }
    APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, val);

    return val;
}

static CPUWriteMemoryFunc * const apb_config_write[] = {
    &apb_config_writel,
    &apb_config_writel,
    &apb_config_writel,
};

static CPUReadMemoryFunc * const apb_config_read[] = {
    &apb_config_readl,
    &apb_config_readl,
    &apb_config_readl,
};

static void apb_pci_config_write(ReadWriteHandler *h, pcibus_t addr,
                                 uint32_t val, int size)
{
    APBState *s = container_of(h, APBState, pci_config_handler);

    val = qemu_bswap_len(val, size);
    APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
    pci_data_write(s->bus, addr, val, size);
}

static uint32_t apb_pci_config_read(ReadWriteHandler *h, pcibus_t addr,
                                    int size)
{
    uint32_t ret;
    APBState *s = container_of(h, APBState, pci_config_handler);

    ret = pci_data_read(s->bus, addr, size);
    ret = qemu_bswap_len(ret, size);
    APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, ret);
    return ret;
}

static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    cpu_outb(addr & IOPORTS_MASK, val);
}

static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    cpu_outw(addr & IOPORTS_MASK, bswap16(val));
}

static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
                                uint32_t val)
{
    cpu_outl(addr & IOPORTS_MASK, bswap32(val));
}

static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
{
    uint32_t val;

    val = cpu_inb(addr & IOPORTS_MASK);
    return val;
}

static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
{
    uint32_t val;

    val = bswap16(cpu_inw(addr & IOPORTS_MASK));
    return val;
}

static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
{
    uint32_t val;

    val = bswap32(cpu_inl(addr & IOPORTS_MASK));
    return val;
}

static CPUWriteMemoryFunc * const pci_apb_iowrite[] = {
    &pci_apb_iowriteb,
    &pci_apb_iowritew,
    &pci_apb_iowritel,
};

static CPUReadMemoryFunc * const pci_apb_ioread[] = {
    &pci_apb_ioreadb,
    &pci_apb_ioreadw,
    &pci_apb_ioreadl,
};

/* The APB host has an IRQ line for each IRQ line of each slot.  */
static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
{
    return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
}

static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int bus_offset;
    if (pci_dev->devfn & 1)
        bus_offset = 16;
    else
        bus_offset = 0;
    return bus_offset + irq_num;
}

static void pci_apb_set_irq(void *opaque, int irq_num, int level)
{
    APBState *s = opaque;

    /* PCI IRQ map onto the first 32 INO.  */
    if (irq_num < 32) {
        if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
            APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
            qemu_set_irq(s->pci_irqs[irq_num], level);
        } else {
            APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);
            qemu_irq_lower(s->pci_irqs[irq_num]);
        }
    }
}

static int apb_pci_bridge_initfn(PCIDevice *dev)
{
    int rc;

    rc = pci_bridge_initfn(dev);
    if (rc < 0) {
        return rc;
    }

    /*
     * command register:
     * According to PCI bridge spec, after reset
     *   bus master bit is off
     *   memory space enable bit is off
     * According to manual (805-1251.pdf).
     *   the reset value should be zero unless the boot pin is tied high
     *   (which is true) and thus it should be PCI_COMMAND_MEMORY.
     */
    pci_set_word(dev->config + PCI_COMMAND,
                 PCI_COMMAND_MEMORY);
    pci_set_word(dev->config + PCI_STATUS,
                 PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
                 PCI_STATUS_DEVSEL_MEDIUM);
    return 0;
}

PCIBus *pci_apb_init(target_phys_addr_t special_base,
                     target_phys_addr_t mem_base,
                     qemu_irq *pic, PCIBus **bus2, PCIBus **bus3)
{
    DeviceState *dev;
    SysBusDevice *s;
    APBState *d;
    unsigned int i;
    PCIDevice *pci_dev;
    PCIBridge *br;

    /* Ultrasparc PBM main bus */
    dev = qdev_create(NULL, "pbm");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    /* apb_config */
    sysbus_mmio_map(s, 0, special_base);
    /* PCI configuration space */
    sysbus_mmio_map(s, 1, special_base + 0x1000000ULL);
    /* pci_ioport */
    sysbus_mmio_map(s, 2, special_base + 0x2000000ULL);
    d = FROM_SYSBUS(APBState, s);

    d->bus = pci_register_bus(&d->busdev.qdev, "pci",
                                         pci_apb_set_irq, pci_pbm_map_irq, d,
                                         get_system_memory(),
                                         0, 32);
    pci_bus_set_mem_base(d->bus, mem_base);

    for (i = 0; i < 32; i++) {
        sysbus_connect_irq(s, i, pic[i]);
    }

    pci_create_simple(d->bus, 0, "pbm");

    /* APB secondary busses */
    pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 0), true,
                                   "pbm-bridge");
    br = DO_UPCAST(PCIBridge, dev, pci_dev);
    pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 1",
                       pci_apb_map_irq);
    qdev_init_nofail(&pci_dev->qdev);
    *bus2 = pci_bridge_get_sec_bus(br);

    pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 1), true,
                                   "pbm-bridge");
    br = DO_UPCAST(PCIBridge, dev, pci_dev);
    pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 2",
                       pci_apb_map_irq);
    qdev_init_nofail(&pci_dev->qdev);
    *bus3 = pci_bridge_get_sec_bus(br);

    return d->bus;
}

static void pci_pbm_reset(DeviceState *d)
{
    unsigned int i;
    APBState *s = container_of(d, APBState, busdev.qdev);

    for (i = 0; i < 8; i++) {
        s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
    }

    if (s->nr_resets++ == 0) {
        /* Power on reset */
        s->reset_control = POR;
    }
}

static int pci_pbm_init_device(SysBusDevice *dev)
{
    APBState *s;
    int pci_config, apb_config, pci_ioport;
    unsigned int i;

    s = FROM_SYSBUS(APBState, dev);
    for (i = 0; i < 8; i++) {
        s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
    }
    for (i = 0; i < 32; i++) {
        sysbus_init_irq(dev, &s->pci_irqs[i]);
    }

    /* apb_config */
    apb_config = cpu_register_io_memory(apb_config_read,
                                        apb_config_write, s,
                                        DEVICE_NATIVE_ENDIAN);
    /* at region 0 */
    sysbus_init_mmio(dev, 0x10000ULL, apb_config);

    /* PCI configuration space */
    s->pci_config_handler.read = apb_pci_config_read;
    s->pci_config_handler.write = apb_pci_config_write;
    pci_config = cpu_register_io_memory_simple(&s->pci_config_handler,
                                               DEVICE_NATIVE_ENDIAN);
    assert(pci_config >= 0);
    /* at region 1 */
    sysbus_init_mmio(dev, 0x1000000ULL, pci_config);

    /* pci_ioport */
    pci_ioport = cpu_register_io_memory(pci_apb_ioread,
                                        pci_apb_iowrite, s,
                                        DEVICE_NATIVE_ENDIAN);
    /* at region 2 */
    sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);

    return 0;
}

static int pbm_pci_host_init(PCIDevice *d)
{
    pci_set_word(d->config + PCI_COMMAND,
                 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
    pci_set_word(d->config + PCI_STATUS,
                 PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
                 PCI_STATUS_DEVSEL_MEDIUM);
    return 0;
}

static PCIDeviceInfo pbm_pci_host_info = {
    .qdev.name = "pbm",
    .qdev.size = sizeof(PCIDevice),
    .init      = pbm_pci_host_init,
    .vendor_id = PCI_VENDOR_ID_SUN,
    .device_id = PCI_DEVICE_ID_SUN_SABRE,
    .class_id  = PCI_CLASS_BRIDGE_HOST,
    .is_bridge = 1,
};

static SysBusDeviceInfo pbm_host_info = {
    .qdev.name = "pbm",
    .qdev.size = sizeof(APBState),
    .qdev.reset = pci_pbm_reset,
    .init = pci_pbm_init_device,
};

static PCIDeviceInfo pbm_pci_bridge_info = {
    .qdev.name = "pbm-bridge",
    .qdev.size = sizeof(PCIBridge),
    .qdev.vmsd = &vmstate_pci_device,
    .qdev.reset = pci_bridge_reset,
    .init = apb_pci_bridge_initfn,
    .exit = pci_bridge_exitfn,
    .vendor_id = PCI_VENDOR_ID_SUN,
    .device_id = PCI_DEVICE_ID_SUN_SIMBA,
    .revision = 0x11,
    .config_write = pci_bridge_write_config,
    .is_bridge = 1,
};

static void pbm_register_devices(void)
{
    sysbus_register_withprop(&pbm_host_info);
    pci_qdev_register(&pbm_pci_host_info);
    pci_qdev_register(&pbm_pci_bridge_info);
}

device_init(pbm_register_devices)
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU Ultrasparc APB PCI host
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
80b3ada7	24
a94fd955	25	/* XXX This file and most of its contents are somewhat misnamed. The
80b3ada7 PB	26	Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is
	27	the secondary PCI bridge. */
	28
72f44c8c	29	#include "sysbus.h"
87ecb68b	30	#include "pci.h"
4f5e19e6	31	#include "pci_host.h"
783753fd	32	#include "pci_bridge.h"
68f79994	33	#include "pci_internals.h"
63e6f31d	34	#include "rwhandler.h"
18e08a55	35	#include "apb_pci.h"
666daa68	36	#include "sysemu.h"
1e39101c	37	#include "exec-memory.h"
a94fd955 BS	38
	39	/* debug APB */
	40	//#define DEBUG_APB
	41
	42	#ifdef DEBUG_APB
001faf32 BS	43	#define APB_DPRINTF(fmt, ...) \
001faf32 BS	44	do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
a94fd955	45	#else
001faf32	46	#define APB_DPRINTF(fmt, ...)
a94fd955 BS	47	#endif
a94fd955 BS	48
930f3fe1 BS	49	/*
	50	* Chipset docs:
	51	* PBM: "UltraSPARC IIi User's Manual",
	52	* http://www.sun.com/processors/manuals/805-0087.pdf
	53	*
	54	* APB: "Advanced PCI Bridge (APB) User's Manual",
	55	* http://www.sun.com/processors/manuals/805-1251.pdf
	56	*/
	57
95819af0 BS	58	#define PBM_PCI_IMR_MASK 0x7fffffff
	59	#define PBM_PCI_IMR_ENABLED 0x80000000
	60
	61	#define POR (1 << 31)
	62	#define SOFT_POR (1 << 30)
	63	#define SOFT_XIR (1 << 29)
	64	#define BTN_POR (1 << 28)
	65	#define BTN_XIR (1 << 27)
	66	#define RESET_MASK 0xf8000000
	67	#define RESET_WCMASK 0x98000000
	68	#define RESET_WMASK 0x60000000
	69
72f44c8c BS	70	typedef struct APBState {
72f44c8c BS	71	SysBusDevice busdev;
d63baf92	72	PCIBus *bus;
63e6f31d	73	ReadWriteHandler pci_config_handler;
95819af0 BS	74	uint32_t iommu[4];
	75	uint32_t pci_control[16];
	76	uint32_t pci_irq_map[8];
	77	uint32_t obio_irq_map[32];
	78	qemu_irq pci_irqs[32];
	79	uint32_t reset_control;
9c0afd0e	80	unsigned int nr_resets;
72f44c8c	81	} APBState;
502a5395	82
c227f099	83	static void apb_config_writel (void *opaque, target_phys_addr_t addr,
f930d07e	84	uint32_t val)
502a5395	85	{
95819af0 BS	86	APBState *s = opaque;
	87
	88	APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
	89
	90	switch (addr & 0xffff) {
	91	case 0x30 ... 0x4f: /* DMA error registers */
	92	/* XXX: not implemented yet */
	93	break;
	94	case 0x200 ... 0x20b: /* IOMMU */
	95	s->iommu[(addr & 0xf) >> 2] = val;
	96	break;
	97	case 0x20c ... 0x3ff: /* IOMMU flush */
	98	break;
	99	case 0xc00 ... 0xc3f: /* PCI interrupt control */
	100	if (addr & 4) {
	101	s->pci_irq_map[(addr & 0x3f) >> 3] &= PBM_PCI_IMR_MASK;
	102	s->pci_irq_map[(addr & 0x3f) >> 3] \|= val & ~PBM_PCI_IMR_MASK;
	103	}
	104	break;
	105	case 0x2000 ... 0x202f: /* PCI control */
	106	s->pci_control[(addr & 0x3f) >> 2] = val;
	107	break;
	108	case 0xf020 ... 0xf027: /* Reset control */
	109	if (addr & 4) {
	110	val &= RESET_MASK;
	111	s->reset_control &= ~(val & RESET_WCMASK);
	112	s->reset_control \|= val & RESET_WMASK;
	113	if (val & SOFT_POR) {
9c0afd0e	114	s->nr_resets = 0;
95819af0 BS	115	qemu_system_reset_request();
	116	} else if (val & SOFT_XIR) {
	117	qemu_system_reset_request();
	118	}
	119	}
	120	break;
	121	case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
	122	case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
	123	case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
	124	case 0xf000 ... 0xf01f: /* FFB config, memory control */
	125	/* we don't care */
502a5395	126	default:
f930d07e	127	break;
502a5395 PB	128	}
	129	}
	130
	131	static uint32_t apb_config_readl (void *opaque,
c227f099	132	target_phys_addr_t addr)
502a5395	133	{
95819af0	134	APBState *s = opaque;
502a5395 PB	135	uint32_t val;
502a5395 PB	136
95819af0 BS	137	switch (addr & 0xffff) {
	138	case 0x30 ... 0x4f: /* DMA error registers */
	139	val = 0;
	140	/* XXX: not implemented yet */
	141	break;
	142	case 0x200 ... 0x20b: /* IOMMU */
	143	val = s->iommu[(addr & 0xf) >> 2];
	144	break;
	145	case 0x20c ... 0x3ff: /* IOMMU flush */
	146	val = 0;
	147	break;
	148	case 0xc00 ... 0xc3f: /* PCI interrupt control */
	149	if (addr & 4) {
	150	val = s->pci_irq_map[(addr & 0x3f) >> 3];
	151	} else {
	152	val = 0;
	153	}
	154	break;
	155	case 0x2000 ... 0x202f: /* PCI control */
	156	val = s->pci_control[(addr & 0x3f) >> 2];
	157	break;
	158	case 0xf020 ... 0xf027: /* Reset control */
	159	if (addr & 4) {
	160	val = s->reset_control;
	161	} else {
	162	val = 0;
	163	}
	164	break;
	165	case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
	166	case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
	167	case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
	168	case 0xf000 ... 0xf01f: /* FFB config, memory control */
	169	/* we don't care */
502a5395	170	default:
f930d07e BS	171	val = 0;
f930d07e BS	172	break;
502a5395	173	}
95819af0 BS	174	APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, val);
95819af0 BS	175
502a5395 PB	176	return val;
	177	}
	178
d60efc6b	179	static CPUWriteMemoryFunc * const apb_config_write[] = {
502a5395 PB	180	&apb_config_writel,
	181	&apb_config_writel,
	182	&apb_config_writel,
	183	};
	184
d60efc6b	185	static CPUReadMemoryFunc * const apb_config_read[] = {
502a5395 PB	186	&apb_config_readl,
	187	&apb_config_readl,
	188	&apb_config_readl,
	189	};
	190
63e6f31d	191	static void apb_pci_config_write(ReadWriteHandler *h, pcibus_t addr,
5a5d4a76 BS	192	uint32_t val, int size)
5a5d4a76 BS	193	{
63e6f31d MT	194	APBState *s = container_of(h, APBState, pci_config_handler);
	195
	196	val = qemu_bswap_len(val, size);
5a5d4a76	197	APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
d63baf92	198	pci_data_write(s->bus, addr, val, size);
5a5d4a76 BS	199	}
5a5d4a76 BS	200
63e6f31d	201	static uint32_t apb_pci_config_read(ReadWriteHandler *h, pcibus_t addr,
5a5d4a76 BS	202	int size)
	203	{
	204	uint32_t ret;
63e6f31d	205	APBState *s = container_of(h, APBState, pci_config_handler);
5a5d4a76	206
d63baf92	207	ret = pci_data_read(s->bus, addr, size);
63e6f31d	208	ret = qemu_bswap_len(ret, size);
5a5d4a76 BS	209	APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, ret);
	210	return ret;
	211	}
	212
c227f099	213	static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
502a5395 PB	214	uint32_t val)
502a5395 PB	215	{
afcea8cb	216	cpu_outb(addr & IOPORTS_MASK, val);
502a5395 PB	217	}
502a5395 PB	218
c227f099	219	static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
502a5395 PB	220	uint32_t val)
502a5395 PB	221	{
a4d5f62c	222	cpu_outw(addr & IOPORTS_MASK, bswap16(val));
502a5395 PB	223	}
502a5395 PB	224
c227f099	225	static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
502a5395 PB	226	uint32_t val)
502a5395 PB	227	{
a4d5f62c	228	cpu_outl(addr & IOPORTS_MASK, bswap32(val));
502a5395 PB	229	}
502a5395 PB	230
c227f099	231	static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
502a5395 PB	232	{
	233	uint32_t val;
	234
afcea8cb	235	val = cpu_inb(addr & IOPORTS_MASK);
502a5395 PB	236	return val;
	237	}
	238
c227f099	239	static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
502a5395 PB	240	{
	241	uint32_t val;
	242
a4d5f62c	243	val = bswap16(cpu_inw(addr & IOPORTS_MASK));
502a5395 PB	244	return val;
	245	}
	246
c227f099	247	static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
502a5395 PB	248	{
	249	uint32_t val;
	250
a4d5f62c	251	val = bswap32(cpu_inl(addr & IOPORTS_MASK));
502a5395 PB	252	return val;
	253	}
	254
d60efc6b	255	static CPUWriteMemoryFunc * const pci_apb_iowrite[] = {
502a5395 PB	256	&pci_apb_iowriteb,
	257	&pci_apb_iowritew,
	258	&pci_apb_iowritel,
	259	};
	260
d60efc6b	261	static CPUReadMemoryFunc * const pci_apb_ioread[] = {
502a5395 PB	262	&pci_apb_ioreadb,
	263	&pci_apb_ioreadw,
	264	&pci_apb_ioreadl,
	265	};
	266
80b3ada7	267	/* The APB host has an IRQ line for each IRQ line of each slot. */
d2b59317	268	static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
502a5395	269	{
80b3ada7 PB	270	return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
	271	}
	272
	273	static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
	274	{
	275	int bus_offset;
	276	if (pci_dev->devfn & 1)
	277	bus_offset = 16;
	278	else
	279	bus_offset = 0;
	280	return bus_offset + irq_num;
d2b59317 PB	281	}
d2b59317 PB	282
5d4e84c8	283	static void pci_apb_set_irq(void *opaque, int irq_num, int level)
d2b59317	284	{
95819af0	285	APBState *s = opaque;
5d4e84c8	286
80b3ada7	287	/* PCI IRQ map onto the first 32 INO. */
95819af0 BS	288	if (irq_num < 32) {
	289	if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
	290	APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
	291	qemu_set_irq(s->pci_irqs[irq_num], level);
	292	} else {
	293	APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);
	294	qemu_irq_lower(s->pci_irqs[irq_num]);
	295	}
	296	}
502a5395 PB	297	}
502a5395 PB	298
68f79994	299	static int apb_pci_bridge_initfn(PCIDevice *dev)
d6318738	300	{
68f79994 IY	301	int rc;
	302
	303	rc = pci_bridge_initfn(dev);
	304	if (rc < 0) {
	305	return rc;
	306	}
	307
d6318738 MT	308	/*
	309	* command register:
	310	* According to PCI bridge spec, after reset
	311	* bus master bit is off
	312	* memory space enable bit is off
	313	* According to manual (805-1251.pdf).
	314	* the reset value should be zero unless the boot pin is tied high
	315	* (which is true) and thus it should be PCI_COMMAND_MEMORY.
	316	*/
	317	pci_set_word(dev->config + PCI_COMMAND,
9fe52c7f BS	318	PCI_COMMAND_MEMORY);
	319	pci_set_word(dev->config + PCI_STATUS,
	320	PCI_STATUS_FAST_BACK \| PCI_STATUS_66MHZ \|
	321	PCI_STATUS_DEVSEL_MEDIUM);
68f79994	322	return 0;
d6318738 MT	323	}
d6318738 MT	324
c227f099 AL	325	PCIBus *pci_apb_init(target_phys_addr_t special_base,
c227f099 AL	326	target_phys_addr_t mem_base,
c190ea07	327	qemu_irq pic, PCIBus bus2, PCIBus *bus3)
502a5395	328	{
72f44c8c BS	329	DeviceState *dev;
	330	SysBusDevice *s;
	331	APBState *d;
95819af0	332	unsigned int i;
68f79994 IY	333	PCIDevice *pci_dev;
68f79994 IY	334	PCIBridge *br;
502a5395	335
80b3ada7	336	/* Ultrasparc PBM main bus */
72f44c8c	337	dev = qdev_create(NULL, "pbm");
e23a1b33	338	qdev_init_nofail(dev);
72f44c8c BS	339	s = sysbus_from_qdev(dev);
72f44c8c BS	340	/* apb_config */
bae7b517	341	sysbus_mmio_map(s, 0, special_base);
d63baf92 IK	342	/* PCI configuration space */
d63baf92 IK	343	sysbus_mmio_map(s, 1, special_base + 0x1000000ULL);
72f44c8c	344	/* pci_ioport */
d63baf92	345	sysbus_mmio_map(s, 2, special_base + 0x2000000ULL);
72f44c8c	346	d = FROM_SYSBUS(APBState, s);
d63baf92 IK	347
d63baf92 IK	348	d->bus = pci_register_bus(&d->busdev.qdev, "pci",
95819af0	349	pci_apb_set_irq, pci_pbm_map_irq, d,
1e39101c	350	get_system_memory(),
72f44c8c	351	0, 32);
d63baf92	352	pci_bus_set_mem_base(d->bus, mem_base);
f6b6f1bc	353
95819af0 BS	354	for (i = 0; i < 32; i++) {
	355	sysbus_connect_irq(s, i, pic[i]);
	356	}
	357
d63baf92 IK	358	pci_create_simple(d->bus, 0, "pbm");
d63baf92 IK	359
72f44c8c	360	/* APB secondary busses */
68f79994 IY	361	pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 0), true,
	362	"pbm-bridge");
	363	br = DO_UPCAST(PCIBridge, dev, pci_dev);
	364	pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 1",
	365	pci_apb_map_irq);
	366	qdev_init_nofail(&pci_dev->qdev);
	367	*bus2 = pci_bridge_get_sec_bus(br);
	368
	369	pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 1), true,
	370	"pbm-bridge");
	371	br = DO_UPCAST(PCIBridge, dev, pci_dev);
	372	pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 2",
	373	pci_apb_map_irq);
	374	qdev_init_nofail(&pci_dev->qdev);
	375	*bus3 = pci_bridge_get_sec_bus(br);
502a5395	376
d63baf92	377	return d->bus;
72f44c8c BS	378	}
72f44c8c BS	379
95819af0	380	static void pci_pbm_reset(DeviceState *d)
72f44c8c	381	{
95819af0 BS	382	unsigned int i;
95819af0 BS	383	APBState *s = container_of(d, APBState, busdev.qdev);
72f44c8c	384
95819af0 BS	385	for (i = 0; i < 8; i++) {
	386	s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
	387	}
	388
9c0afd0e	389	if (s->nr_resets++ == 0) {
95819af0 BS	390	/* Power on reset */
	391	s->reset_control = POR;
	392	}
	393	}
	394
	395	static int pci_pbm_init_device(SysBusDevice *dev)
	396	{
72f44c8c	397	APBState *s;
d63baf92	398	int pci_config, apb_config, pci_ioport;
95819af0	399	unsigned int i;
72f44c8c BS	400
72f44c8c BS	401	s = FROM_SYSBUS(APBState, dev);
95819af0 BS	402	for (i = 0; i < 8; i++) {
	403	s->pci_irq_map[i] = (0x1f << 6) \| (i << 2);
	404	}
	405	for (i = 0; i < 32; i++) {
	406	sysbus_init_irq(dev, &s->pci_irqs[i]);
	407	}
	408
72f44c8c	409	/* apb_config */
1eed09cb	410	apb_config = cpu_register_io_memory(apb_config_read,
2507c12a AG	411	apb_config_write, s,
2507c12a AG	412	DEVICE_NATIVE_ENDIAN);
d63baf92	413	/* at region 0 */
bae7b517	414	sysbus_init_mmio(dev, 0x10000ULL, apb_config);
d63baf92 IK	415
d63baf92 IK	416	/* PCI configuration space */
63e6f31d MT	417	s->pci_config_handler.read = apb_pci_config_read;
63e6f31d MT	418	s->pci_config_handler.write = apb_pci_config_write;
6bef0436 AG	419	pci_config = cpu_register_io_memory_simple(&s->pci_config_handler,
6bef0436 AG	420	DEVICE_NATIVE_ENDIAN);
63e6f31d	421	assert(pci_config >= 0);
d63baf92	422	/* at region 1 */
5a5d4a76	423	sysbus_init_mmio(dev, 0x1000000ULL, pci_config);
d63baf92 IK	424
	425	/* pci_ioport */
	426	pci_ioport = cpu_register_io_memory(pci_apb_ioread,
2507c12a AG	427	pci_apb_iowrite, s,
2507c12a AG	428	DEVICE_NATIVE_ENDIAN);
d63baf92 IK	429	/* at region 2 */
	430	sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);
	431
81a322d4	432	return 0;
72f44c8c	433	}
502a5395	434
81a322d4	435	static int pbm_pci_host_init(PCIDevice *d)
72f44c8c	436	{
9fe52c7f BS	437	pci_set_word(d->config + PCI_COMMAND,
	438	PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
	439	pci_set_word(d->config + PCI_STATUS,
	440	PCI_STATUS_FAST_BACK \| PCI_STATUS_66MHZ \|
	441	PCI_STATUS_DEVSEL_MEDIUM);
81a322d4	442	return 0;
72f44c8c	443	}
80b3ada7	444
72f44c8c BS	445	static PCIDeviceInfo pbm_pci_host_info = {
	446	.qdev.name = "pbm",
	447	.qdev.size = sizeof(PCIDevice),
	448	.init = pbm_pci_host_init,
92f9a4f1 IY	449	.vendor_id = PCI_VENDOR_ID_SUN,
	450	.device_id = PCI_DEVICE_ID_SUN_SABRE,
	451	.class_id = PCI_CLASS_BRIDGE_HOST,
e327e323	452	.is_bridge = 1,
72f44c8c BS	453	};
72f44c8c BS	454
95819af0 BS	455	static SysBusDeviceInfo pbm_host_info = {
	456	.qdev.name = "pbm",
	457	.qdev.size = sizeof(APBState),
	458	.qdev.reset = pci_pbm_reset,
	459	.init = pci_pbm_init_device,
	460	};
68f79994 IY	461
	462	static PCIDeviceInfo pbm_pci_bridge_info = {
	463	.qdev.name = "pbm-bridge",
	464	.qdev.size = sizeof(PCIBridge),
	465	.qdev.vmsd = &vmstate_pci_device,
	466	.qdev.reset = pci_bridge_reset,
	467	.init = apb_pci_bridge_initfn,
	468	.exit = pci_bridge_exitfn,
92f9a4f1 IY	469	.vendor_id = PCI_VENDOR_ID_SUN,
	470	.device_id = PCI_DEVICE_ID_SUN_SIMBA,
	471	.revision = 0x11,
68f79994 IY	472	.config_write = pci_bridge_write_config,
	473	.is_bridge = 1,
	474	};
	475
72f44c8c BS	476	static void pbm_register_devices(void)
72f44c8c BS	477	{
95819af0	478	sysbus_register_withprop(&pbm_host_info);
72f44c8c	479	pci_qdev_register(&pbm_pci_host_info);
68f79994	480	pci_qdev_register(&pbm_pci_bridge_info);
502a5395	481	}
72f44c8c BS	482
72f44c8c BS	483	device_init(pbm_register_devices)