projects / qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 8dd3dca3 AJ |
1 | #include "hw/hw.h" |
| 2 | #include "hw/boards.h" | |
| 0b8f1b10 | 3 | #include "qemu-timer.h" |
| 8dd3dca3 AJ |
4 | |
| 5 | #include "exec-all.h" | |
| 6 | ||
| 8dd3dca3 AJ |
7 | void cpu_save(QEMUFile *f, void *opaque) |
| 8 | { | |
| 9 | CPUState *env = opaque; | |
| 10 | int i; | |
| 11 | uint32_t tmp; | |
| 12 | ||
| a7a044f2 BS |
13 | // if env->cwp == env->nwindows - 1, this will set the ins of the last |
| 14 | // window as the outs of the first window | |
| 15 | cpu_set_cwp(env, env->cwp); | |
| 16 | ||
| 8dd3dca3 AJ |
17 | for(i = 0; i < 8; i++) |
| 18 | qemu_put_betls(f, &env->gregs[i]); | |
| 1a14026e BS |
19 | qemu_put_be32s(f, &env->nwindows); |
| 20 | for(i = 0; i < env->nwindows * 16; i++) | |
| 8dd3dca3 AJ |
21 | qemu_put_betls(f, &env->regbase[i]); |
| 22 | ||
| 23 | /* FPU */ | |
| 24 | for(i = 0; i < TARGET_FPREGS; i++) { | |
| 25 | union { | |
| 26 | float32 f; | |
| 27 | uint32_t i; | |
| 28 | } u; | |
| 29 | u.f = env->fpr[i]; | |
| 30 | qemu_put_be32(f, u.i); | |
| 31 | } | |
| 32 | ||
| 33 | qemu_put_betls(f, &env->pc); | |
| 34 | qemu_put_betls(f, &env->npc); | |
| 35 | qemu_put_betls(f, &env->y); | |
| 36 | tmp = GET_PSR(env); | |
| 37 | qemu_put_be32(f, tmp); | |
| 38 | qemu_put_betls(f, &env->fsr); | |
| 39 | qemu_put_betls(f, &env->tbr); | |
| a7a044f2 BS |
40 | tmp = env->interrupt_index; |
| 41 | qemu_put_be32(f, tmp); | |
| 42 | qemu_put_be32s(f, &env->pil_in); | |
| 8dd3dca3 AJ |
43 | #ifndef TARGET_SPARC64 |
| 44 | qemu_put_be32s(f, &env->wim); | |
| 45 | /* MMU */ | |
| 0b8f1b10 | 46 | for (i = 0; i < 32; i++) |
| 8dd3dca3 | 47 | qemu_put_be32s(f, &env->mmuregs[i]); |
| 0b8f1b10 BS |
48 | #else |
| 49 | qemu_put_be64s(f, &env->lsu); | |
| 50 | for (i = 0; i < 16; i++) { | |
| 51 | qemu_put_be64s(f, &env->immuregs[i]); | |
| 52 | qemu_put_be64s(f, &env->dmmuregs[i]); | |
| 53 | } | |
| 54 | for (i = 0; i < 64; i++) { | |
| 6e8e7d4c IK |
55 | qemu_put_be64s(f, &env->itlb[i].tag); |
| 56 | qemu_put_be64s(f, &env->itlb[i].tte); | |
| 57 | qemu_put_be64s(f, &env->dtlb[i].tag); | |
| 58 | qemu_put_be64s(f, &env->dtlb[i].tte); | |
| 0b8f1b10 BS |
59 | } |
| 60 | qemu_put_be32s(f, &env->mmu_version); | |
| c19148bd | 61 | for (i = 0; i < MAXTL_MAX; i++) { |
| 0b8f1b10 BS |
62 | qemu_put_be64s(f, &env->ts[i].tpc); |
| 63 | qemu_put_be64s(f, &env->ts[i].tnpc); | |
| 64 | qemu_put_be64s(f, &env->ts[i].tstate); | |
| 65 | qemu_put_be32s(f, &env->ts[i].tt); | |
| 66 | } | |
| 67 | qemu_put_be32s(f, &env->xcc); | |
| 68 | qemu_put_be32s(f, &env->asi); | |
| 69 | qemu_put_be32s(f, &env->pstate); | |
| 70 | qemu_put_be32s(f, &env->tl); | |
| 71 | qemu_put_be32s(f, &env->cansave); | |
| 72 | qemu_put_be32s(f, &env->canrestore); | |
| 73 | qemu_put_be32s(f, &env->otherwin); | |
| 74 | qemu_put_be32s(f, &env->wstate); | |
| 75 | qemu_put_be32s(f, &env->cleanwin); | |
| 76 | for (i = 0; i < 8; i++) | |
| 77 | qemu_put_be64s(f, &env->agregs[i]); | |
| 78 | for (i = 0; i < 8; i++) | |
| 79 | qemu_put_be64s(f, &env->bgregs[i]); | |
| 80 | for (i = 0; i < 8; i++) | |
| 81 | qemu_put_be64s(f, &env->igregs[i]); | |
| 82 | for (i = 0; i < 8; i++) | |
| 83 | qemu_put_be64s(f, &env->mgregs[i]); | |
| 84 | qemu_put_be64s(f, &env->fprs); | |
| 85 | qemu_put_be64s(f, &env->tick_cmpr); | |
| 86 | qemu_put_be64s(f, &env->stick_cmpr); | |
| 87 | qemu_put_ptimer(f, env->tick); | |
| 88 | qemu_put_ptimer(f, env->stick); | |
| 89 | qemu_put_be64s(f, &env->gsr); | |
| 90 | qemu_put_be32s(f, &env->gl); | |
| 91 | qemu_put_be64s(f, &env->hpstate); | |
| c19148bd | 92 | for (i = 0; i < MAXTL_MAX; i++) |
| 0b8f1b10 BS |
93 | qemu_put_be64s(f, &env->htstate[i]); |
| 94 | qemu_put_be64s(f, &env->hintp); | |
| 95 | qemu_put_be64s(f, &env->htba); | |
| 96 | qemu_put_be64s(f, &env->hver); | |
| 97 | qemu_put_be64s(f, &env->hstick_cmpr); | |
| 98 | qemu_put_be64s(f, &env->ssr); | |
| a7a044f2 | 99 | qemu_put_ptimer(f, env->hstick); |
| 8dd3dca3 AJ |
100 | #endif |
| 101 | } | |
| 102 | ||
| 103 | int cpu_load(QEMUFile *f, void *opaque, int version_id) | |
| 104 | { | |
| 105 | CPUState *env = opaque; | |
| 106 | int i; | |
| 107 | uint32_t tmp; | |
| 108 | ||
| 0b8f1b10 | 109 | if (version_id != 5) |
| 1a14026e | 110 | return -EINVAL; |
| 8dd3dca3 AJ |
111 | for(i = 0; i < 8; i++) |
| 112 | qemu_get_betls(f, &env->gregs[i]); | |
| 1a14026e BS |
113 | qemu_get_be32s(f, &env->nwindows); |
| 114 | for(i = 0; i < env->nwindows * 16; i++) | |
| 8dd3dca3 AJ |
115 | qemu_get_betls(f, &env->regbase[i]); |
| 116 | ||
| 117 | /* FPU */ | |
| 118 | for(i = 0; i < TARGET_FPREGS; i++) { | |
| 119 | union { | |
| 120 | float32 f; | |
| 121 | uint32_t i; | |
| 122 | } u; | |
| 123 | u.i = qemu_get_be32(f); | |
| 124 | env->fpr[i] = u.f; | |
| 125 | } | |
| 126 | ||
| 127 | qemu_get_betls(f, &env->pc); | |
| 128 | qemu_get_betls(f, &env->npc); | |
| 129 | qemu_get_betls(f, &env->y); | |
| 130 | tmp = qemu_get_be32(f); | |
| 131 | env->cwp = 0; /* needed to ensure that the wrapping registers are | |
| 132 | correctly updated */ | |
| 133 | PUT_PSR(env, tmp); | |
| 134 | qemu_get_betls(f, &env->fsr); | |
| 135 | qemu_get_betls(f, &env->tbr); | |
| a7a044f2 BS |
136 | tmp = qemu_get_be32(f); |
| 137 | env->interrupt_index = tmp; | |
| 138 | qemu_get_be32s(f, &env->pil_in); | |
| 8dd3dca3 AJ |
139 | #ifndef TARGET_SPARC64 |
| 140 | qemu_get_be32s(f, &env->wim); | |
| 141 | /* MMU */ | |
| 0b8f1b10 | 142 | for (i = 0; i < 32; i++) |
| 8dd3dca3 | 143 | qemu_get_be32s(f, &env->mmuregs[i]); |
| 0b8f1b10 BS |
144 | #else |
| 145 | qemu_get_be64s(f, &env->lsu); | |
| 146 | for (i = 0; i < 16; i++) { | |
| 147 | qemu_get_be64s(f, &env->immuregs[i]); | |
| 148 | qemu_get_be64s(f, &env->dmmuregs[i]); | |
| 149 | } | |
| 150 | for (i = 0; i < 64; i++) { | |
| 6e8e7d4c IK |
151 | qemu_get_be64s(f, &env->itlb[i].tag); |
| 152 | qemu_get_be64s(f, &env->itlb[i].tte); | |
| 153 | qemu_get_be64s(f, &env->dtlb[i].tag); | |
| 154 | qemu_get_be64s(f, &env->dtlb[i].tte); | |
| 0b8f1b10 BS |
155 | } |
| 156 | qemu_get_be32s(f, &env->mmu_version); | |
| c19148bd | 157 | for (i = 0; i < MAXTL_MAX; i++) { |
| 0b8f1b10 BS |
158 | qemu_get_be64s(f, &env->ts[i].tpc); |
| 159 | qemu_get_be64s(f, &env->ts[i].tnpc); | |
| 160 | qemu_get_be64s(f, &env->ts[i].tstate); | |
| 161 | qemu_get_be32s(f, &env->ts[i].tt); | |
| 162 | } | |
| 163 | qemu_get_be32s(f, &env->xcc); | |
| 164 | qemu_get_be32s(f, &env->asi); | |
| 165 | qemu_get_be32s(f, &env->pstate); | |
| 166 | qemu_get_be32s(f, &env->tl); | |
| 0b8f1b10 BS |
167 | qemu_get_be32s(f, &env->cansave); |
| 168 | qemu_get_be32s(f, &env->canrestore); | |
| 169 | qemu_get_be32s(f, &env->otherwin); | |
| 170 | qemu_get_be32s(f, &env->wstate); | |
| 171 | qemu_get_be32s(f, &env->cleanwin); | |
| 172 | for (i = 0; i < 8; i++) | |
| 173 | qemu_get_be64s(f, &env->agregs[i]); | |
| 174 | for (i = 0; i < 8; i++) | |
| 175 | qemu_get_be64s(f, &env->bgregs[i]); | |
| 176 | for (i = 0; i < 8; i++) | |
| 177 | qemu_get_be64s(f, &env->igregs[i]); | |
| 178 | for (i = 0; i < 8; i++) | |
| 179 | qemu_get_be64s(f, &env->mgregs[i]); | |
| 180 | qemu_get_be64s(f, &env->fprs); | |
| 181 | qemu_get_be64s(f, &env->tick_cmpr); | |
| 182 | qemu_get_be64s(f, &env->stick_cmpr); | |
| 183 | qemu_get_ptimer(f, env->tick); | |
| 184 | qemu_get_ptimer(f, env->stick); | |
| 185 | qemu_get_be64s(f, &env->gsr); | |
| 186 | qemu_get_be32s(f, &env->gl); | |
| 187 | qemu_get_be64s(f, &env->hpstate); | |
| c19148bd | 188 | for (i = 0; i < MAXTL_MAX; i++) |
| 0b8f1b10 BS |
189 | qemu_get_be64s(f, &env->htstate[i]); |
| 190 | qemu_get_be64s(f, &env->hintp); | |
| 191 | qemu_get_be64s(f, &env->htba); | |
| 192 | qemu_get_be64s(f, &env->hver); | |
| 193 | qemu_get_be64s(f, &env->hstick_cmpr); | |
| 194 | qemu_get_be64s(f, &env->ssr); | |
| 195 | qemu_get_ptimer(f, env->hstick); | |
| 8dd3dca3 AJ |
196 | #endif |
| 197 | tlb_flush(env, 1); | |
| 198 | return 0; | |
| 199 | } |