[qemu.git] / linux-user / vm86.c

/*
 *  vm86 linux syscall support
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, see <http://www.gnu.org/licenses/>.
 */
#include <stdlib.h>
#include <stdio.h>
#include <stdarg.h>
#include <string.h>
#include <errno.h>
#include <unistd.h>

#include "qemu.h"

//#define DEBUG_VM86

#ifdef DEBUG_VM86
#  define LOG_VM86(...) qemu_log(__VA_ARGS__);
#else
#  define LOG_VM86(...) do { } while (0)
#endif


#define set_flags(X,new,mask) \
((X) = ((X) & ~(mask)) | ((new) & (mask)))

#define SAFE_MASK	(0xDD5)
#define RETURN_MASK	(0xDFF)

static inline int is_revectored(int nr, struct target_revectored_struct *bitmap)
{
    return (((uint8_t *)bitmap)[nr >> 3] >> (nr & 7)) & 1;
}

static inline void vm_putw(uint32_t segptr, unsigned int reg16, unsigned int val)
{
    stw(segptr + (reg16 & 0xffff), val);
}

static inline void vm_putl(uint32_t segptr, unsigned int reg16, unsigned int val)
{
    stl(segptr + (reg16 & 0xffff), val);
}

static inline unsigned int vm_getb(uint32_t segptr, unsigned int reg16)
{
    return ldub(segptr + (reg16 & 0xffff));
}

static inline unsigned int vm_getw(uint32_t segptr, unsigned int reg16)
{
    return lduw(segptr + (reg16 & 0xffff));
}

static inline unsigned int vm_getl(uint32_t segptr, unsigned int reg16)
{
    return ldl(segptr + (reg16 & 0xffff));
}

void save_v86_state(CPUX86State *env)
{
    TaskState *ts = env->opaque;
    struct target_vm86plus_struct * target_v86;

    if (!lock_user_struct(VERIFY_WRITE, target_v86, ts->target_v86, 0))
        /* FIXME - should return an error */
        return;
    /* put the VM86 registers in the userspace register structure */
    target_v86->regs.eax = tswap32(env->regs[R_EAX]);
    target_v86->regs.ebx = tswap32(env->regs[R_EBX]);
    target_v86->regs.ecx = tswap32(env->regs[R_ECX]);
    target_v86->regs.edx = tswap32(env->regs[R_EDX]);
    target_v86->regs.esi = tswap32(env->regs[R_ESI]);
    target_v86->regs.edi = tswap32(env->regs[R_EDI]);
    target_v86->regs.ebp = tswap32(env->regs[R_EBP]);
    target_v86->regs.esp = tswap32(env->regs[R_ESP]);
    target_v86->regs.eip = tswap32(env->eip);
    target_v86->regs.cs = tswap16(env->segs[R_CS].selector);
    target_v86->regs.ss = tswap16(env->segs[R_SS].selector);
    target_v86->regs.ds = tswap16(env->segs[R_DS].selector);
    target_v86->regs.es = tswap16(env->segs[R_ES].selector);
    target_v86->regs.fs = tswap16(env->segs[R_FS].selector);
    target_v86->regs.gs = tswap16(env->segs[R_GS].selector);
    set_flags(env->eflags, ts->v86flags, VIF_MASK | ts->v86mask);
    target_v86->regs.eflags = tswap32(env->eflags);
    unlock_user_struct(target_v86, ts->target_v86, 1);
    LOG_VM86("save_v86_state: eflags=%08x cs:ip=%04x:%04x\n",
             env->eflags, env->segs[R_CS].selector, env->eip);

    /* restore 32 bit registers */
    env->regs[R_EAX] = ts->vm86_saved_regs.eax;
    env->regs[R_EBX] = ts->vm86_saved_regs.ebx;
    env->regs[R_ECX] = ts->vm86_saved_regs.ecx;
    env->regs[R_EDX] = ts->vm86_saved_regs.edx;
    env->regs[R_ESI] = ts->vm86_saved_regs.esi;
    env->regs[R_EDI] = ts->vm86_saved_regs.edi;
    env->regs[R_EBP] = ts->vm86_saved_regs.ebp;
    env->regs[R_ESP] = ts->vm86_saved_regs.esp;
    env->eflags = ts->vm86_saved_regs.eflags;
    env->eip = ts->vm86_saved_regs.eip;

    cpu_x86_load_seg(env, R_CS, ts->vm86_saved_regs.cs);
    cpu_x86_load_seg(env, R_SS, ts->vm86_saved_regs.ss);
    cpu_x86_load_seg(env, R_DS, ts->vm86_saved_regs.ds);
    cpu_x86_load_seg(env, R_ES, ts->vm86_saved_regs.es);
    cpu_x86_load_seg(env, R_FS, ts->vm86_saved_regs.fs);
    cpu_x86_load_seg(env, R_GS, ts->vm86_saved_regs.gs);
}

/* return from vm86 mode to 32 bit. The vm86() syscall will return
   'retval' */
static inline void return_to_32bit(CPUX86State *env, int retval)
{
    LOG_VM86("return_to_32bit: ret=0x%x\n", retval);
    save_v86_state(env);
    env->regs[R_EAX] = retval;
}

static inline int set_IF(CPUX86State *env)
{
    TaskState *ts = env->opaque;

    ts->v86flags |= VIF_MASK;
    if (ts->v86flags & VIP_MASK) {
        return_to_32bit(env, TARGET_VM86_STI);
        return 1;
    }
    return 0;
}

static inline void clear_IF(CPUX86State *env)
{
    TaskState *ts = env->opaque;

    ts->v86flags &= ~VIF_MASK;
}

static inline void clear_TF(CPUX86State *env)
{
    env->eflags &= ~TF_MASK;
}

static inline void clear_AC(CPUX86State *env)
{
    env->eflags &= ~AC_MASK;
}

static inline int set_vflags_long(unsigned long eflags, CPUX86State *env)
{
    TaskState *ts = env->opaque;

    set_flags(ts->v86flags, eflags, ts->v86mask);
    set_flags(env->eflags, eflags, SAFE_MASK);
    if (eflags & IF_MASK)
        return set_IF(env);
    else
        clear_IF(env);
    return 0;
}

static inline int set_vflags_short(unsigned short flags, CPUX86State *env)
{
    TaskState *ts = env->opaque;

    set_flags(ts->v86flags, flags, ts->v86mask & 0xffff);
    set_flags(env->eflags, flags, SAFE_MASK);
    if (flags & IF_MASK)
        return set_IF(env);
    else
        clear_IF(env);
    return 0;
}

static inline unsigned int get_vflags(CPUX86State *env)
{
    TaskState *ts = env->opaque;
    unsigned int flags;

    flags = env->eflags & RETURN_MASK;
    if (ts->v86flags & VIF_MASK)
        flags |= IF_MASK;
    flags |= IOPL_MASK;
    return flags | (ts->v86flags & ts->v86mask);
}

#define ADD16(reg, val) reg = (reg & ~0xffff) | ((reg + (val)) & 0xffff)

/* handle VM86 interrupt (NOTE: the CPU core currently does not
   support TSS interrupt revectoring, so this code is always executed) */
static void do_int(CPUX86State *env, int intno)
{
    TaskState *ts = env->opaque;
    uint32_t int_addr, segoffs, ssp;
    unsigned int sp;

    if (env->segs[R_CS].selector == TARGET_BIOSSEG)
        goto cannot_handle;
    if (is_revectored(intno, &ts->vm86plus.int_revectored))
        goto cannot_handle;
    if (intno == 0x21 && is_revectored((env->regs[R_EAX] >> 8) & 0xff,
                                       &ts->vm86plus.int21_revectored))
        goto cannot_handle;
    int_addr = (intno << 2);
    segoffs = ldl(int_addr);
    if ((segoffs >> 16) == TARGET_BIOSSEG)
        goto cannot_handle;
    LOG_VM86("VM86: emulating int 0x%x. CS:IP=%04x:%04x\n",
             intno, segoffs >> 16, segoffs & 0xffff);
    /* save old state */
    ssp = env->segs[R_SS].selector << 4;
    sp = env->regs[R_ESP] & 0xffff;
    vm_putw(ssp, sp - 2, get_vflags(env));
    vm_putw(ssp, sp - 4, env->segs[R_CS].selector);
    vm_putw(ssp, sp - 6, env->eip);
    ADD16(env->regs[R_ESP], -6);
    /* goto interrupt handler */
    env->eip = segoffs & 0xffff;
    cpu_x86_load_seg(env, R_CS, segoffs >> 16);
    clear_TF(env);
    clear_IF(env);
    clear_AC(env);
    return;
 cannot_handle:
    LOG_VM86("VM86: return to 32 bits int 0x%x\n", intno);
    return_to_32bit(env, TARGET_VM86_INTx | (intno << 8));
}

void handle_vm86_trap(CPUX86State *env, int trapno)
{
    if (trapno == 1 || trapno == 3) {
        return_to_32bit(env, TARGET_VM86_TRAP + (trapno << 8));
    } else {
        do_int(env, trapno);
    }
}

#define CHECK_IF_IN_TRAP() \
      if ((ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_active) && \
          (ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_TFpendig)) \
		newflags |= TF_MASK

#define VM86_FAULT_RETURN \
        if ((ts->vm86plus.vm86plus.flags & TARGET_force_return_for_pic) && \
            (ts->v86flags & (IF_MASK | VIF_MASK))) \
            return_to_32bit(env, TARGET_VM86_PICRETURN); \
        return

void handle_vm86_fault(CPUX86State *env)
{
    TaskState *ts = env->opaque;
    uint32_t csp, ssp;
    unsigned int ip, sp, newflags, newip, newcs, opcode, intno;
    int data32, pref_done;

    csp = env->segs[R_CS].selector << 4;
    ip = env->eip & 0xffff;

    ssp = env->segs[R_SS].selector << 4;
    sp = env->regs[R_ESP] & 0xffff;

    LOG_VM86("VM86 exception %04x:%08x\n",
             env->segs[R_CS].selector, env->eip);

    data32 = 0;
    pref_done = 0;
    do {
        opcode = vm_getb(csp, ip);
        ADD16(ip, 1);
        switch (opcode) {
        case 0x66:      /* 32-bit data */     data32=1; break;
        case 0x67:      /* 32-bit address */  break;
        case 0x2e:      /* CS */              break;
        case 0x3e:      /* DS */              break;
        case 0x26:      /* ES */              break;
        case 0x36:      /* SS */              break;
        case 0x65:      /* GS */              break;
        case 0x64:      /* FS */              break;
        case 0xf2:      /* repnz */	      break;
        case 0xf3:      /* rep */             break;
        default: pref_done = 1;
        }
    } while (!pref_done);

    /* VM86 mode */
    switch(opcode) {
    case 0x9c: /* pushf */
        if (data32) {
            vm_putl(ssp, sp - 4, get_vflags(env));
            ADD16(env->regs[R_ESP], -4);
        } else {
            vm_putw(ssp, sp - 2, get_vflags(env));
            ADD16(env->regs[R_ESP], -2);
        }
        env->eip = ip;
        VM86_FAULT_RETURN;

    case 0x9d: /* popf */
        if (data32) {
            newflags = vm_getl(ssp, sp);
            ADD16(env->regs[R_ESP], 4);
        } else {
            newflags = vm_getw(ssp, sp);
            ADD16(env->regs[R_ESP], 2);
        }
        env->eip = ip;
        CHECK_IF_IN_TRAP();
        if (data32) {
            if (set_vflags_long(newflags, env))
                return;
        } else {
            if (set_vflags_short(newflags, env))
                return;
        }
        VM86_FAULT_RETURN;

    case 0xcd: /* int */
        intno = vm_getb(csp, ip);
        ADD16(ip, 1);
        env->eip = ip;
        if (ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_active) {
            if ( (ts->vm86plus.vm86plus.vm86dbg_intxxtab[intno >> 3] >>
                  (intno &7)) & 1) {
                return_to_32bit(env, TARGET_VM86_INTx + (intno << 8));
                return;
            }
        }
        do_int(env, intno);
        break;

    case 0xcf: /* iret */
        if (data32) {
            newip = vm_getl(ssp, sp) & 0xffff;
            newcs = vm_getl(ssp, sp + 4) & 0xffff;
            newflags = vm_getl(ssp, sp + 8);
            ADD16(env->regs[R_ESP], 12);
        } else {
            newip = vm_getw(ssp, sp);
            newcs = vm_getw(ssp, sp + 2);
            newflags = vm_getw(ssp, sp + 4);
            ADD16(env->regs[R_ESP], 6);
        }
        env->eip = newip;
        cpu_x86_load_seg(env, R_CS, newcs);
        CHECK_IF_IN_TRAP();
        if (data32) {
            if (set_vflags_long(newflags, env))
                return;
        } else {
            if (set_vflags_short(newflags, env))
                return;
        }
        VM86_FAULT_RETURN;

    case 0xfa: /* cli */
        env->eip = ip;
        clear_IF(env);
        VM86_FAULT_RETURN;

    case 0xfb: /* sti */
        env->eip = ip;
        if (set_IF(env))
            return;
        VM86_FAULT_RETURN;

    default:
        /* real VM86 GPF exception */
        return_to_32bit(env, TARGET_VM86_UNKNOWN);
        break;
    }
}

int do_vm86(CPUX86State *env, long subfunction, abi_ulong vm86_addr)
{
    TaskState *ts = env->opaque;
    struct target_vm86plus_struct * target_v86;
    int ret;

    switch (subfunction) {
    case TARGET_VM86_REQUEST_IRQ:
    case TARGET_VM86_FREE_IRQ:
    case TARGET_VM86_GET_IRQ_BITS:
    case TARGET_VM86_GET_AND_RESET_IRQ:
        gemu_log("qemu: unsupported vm86 subfunction (%ld)\n", subfunction);
        ret = -TARGET_EINVAL;
        goto out;
    case TARGET_VM86_PLUS_INSTALL_CHECK:
        /* NOTE: on old vm86 stuff this will return the error
           from verify_area(), because the subfunction is
           interpreted as (invalid) address to vm86_struct.
           So the installation check works.
            */
        ret = 0;
        goto out;
    }

    /* save current CPU regs */
    ts->vm86_saved_regs.eax = 0; /* default vm86 syscall return code */
    ts->vm86_saved_regs.ebx = env->regs[R_EBX];
    ts->vm86_saved_regs.ecx = env->regs[R_ECX];
    ts->vm86_saved_regs.edx = env->regs[R_EDX];
    ts->vm86_saved_regs.esi = env->regs[R_ESI];
    ts->vm86_saved_regs.edi = env->regs[R_EDI];
    ts->vm86_saved_regs.ebp = env->regs[R_EBP];
    ts->vm86_saved_regs.esp = env->regs[R_ESP];
    ts->vm86_saved_regs.eflags = env->eflags;
    ts->vm86_saved_regs.eip  = env->eip;
    ts->vm86_saved_regs.cs = env->segs[R_CS].selector;
    ts->vm86_saved_regs.ss = env->segs[R_SS].selector;
    ts->vm86_saved_regs.ds = env->segs[R_DS].selector;
    ts->vm86_saved_regs.es = env->segs[R_ES].selector;
    ts->vm86_saved_regs.fs = env->segs[R_FS].selector;
    ts->vm86_saved_regs.gs = env->segs[R_GS].selector;

    ts->target_v86 = vm86_addr;
    if (!lock_user_struct(VERIFY_READ, target_v86, vm86_addr, 1))
        return -TARGET_EFAULT;
    /* build vm86 CPU state */
    ts->v86flags = tswap32(target_v86->regs.eflags);
    env->eflags = (env->eflags & ~SAFE_MASK) |
        (tswap32(target_v86->regs.eflags) & SAFE_MASK) | VM_MASK;

    ts->vm86plus.cpu_type = tswapl(target_v86->cpu_type);
    switch (ts->vm86plus.cpu_type) {
    case TARGET_CPU_286:
        ts->v86mask = 0;
        break;
    case TARGET_CPU_386:
        ts->v86mask = NT_MASK | IOPL_MASK;
        break;
    case TARGET_CPU_486:
        ts->v86mask = AC_MASK | NT_MASK | IOPL_MASK;
        break;
    default:
        ts->v86mask = ID_MASK | AC_MASK | NT_MASK | IOPL_MASK;
        break;
    }

    env->regs[R_EBX] = tswap32(target_v86->regs.ebx);
    env->regs[R_ECX] = tswap32(target_v86->regs.ecx);
    env->regs[R_EDX] = tswap32(target_v86->regs.edx);
    env->regs[R_ESI] = tswap32(target_v86->regs.esi);
    env->regs[R_EDI] = tswap32(target_v86->regs.edi);
    env->regs[R_EBP] = tswap32(target_v86->regs.ebp);
    env->regs[R_ESP] = tswap32(target_v86->regs.esp);
    env->eip = tswap32(target_v86->regs.eip);
    cpu_x86_load_seg(env, R_CS, tswap16(target_v86->regs.cs));
    cpu_x86_load_seg(env, R_SS, tswap16(target_v86->regs.ss));
    cpu_x86_load_seg(env, R_DS, tswap16(target_v86->regs.ds));
    cpu_x86_load_seg(env, R_ES, tswap16(target_v86->regs.es));
    cpu_x86_load_seg(env, R_FS, tswap16(target_v86->regs.fs));
    cpu_x86_load_seg(env, R_GS, tswap16(target_v86->regs.gs));
    ret = tswap32(target_v86->regs.eax); /* eax will be restored at
                                            the end of the syscall */
    memcpy(&ts->vm86plus.int_revectored,
           &target_v86->int_revectored, 32);
    memcpy(&ts->vm86plus.int21_revectored,
           &target_v86->int21_revectored, 32);
    ts->vm86plus.vm86plus.flags = tswapl(target_v86->vm86plus.flags);
    memcpy(&ts->vm86plus.vm86plus.vm86dbg_intxxtab,
           target_v86->vm86plus.vm86dbg_intxxtab, 32);
    unlock_user_struct(target_v86, vm86_addr, 0);

    LOG_VM86("do_vm86: cs:ip=%04x:%04x\n",
             env->segs[R_CS].selector, env->eip);
    /* now the virtual CPU is ready for vm86 execution ! */
 out:
    return ret;
}
Commit	Line	Data
46ddf551 FB	1	/*
46ddf551 FB	2	* vm86 linux syscall support
5fafdf24	3	*
46ddf551 FB	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
8167ee88	17	* along with this program; if not, see <http://www.gnu.org/licenses/>.
46ddf551 FB	18	*/
	19	#include <stdlib.h>
	20	#include <stdio.h>
	21	#include <stdarg.h>
	22	#include <string.h>
	23	#include <errno.h>
	24	#include <unistd.h>
	25
	26	#include "qemu.h"
	27
	28	//#define DEBUG_VM86
	29
d12d51d5	30	#ifdef DEBUG_VM86
93fcfe39	31	# define LOG_VM86(...) qemu_log(__VA_ARGS__);
d12d51d5 AL	32	#else
	33	# define LOG_VM86(...) do { } while (0)
	34	#endif
	35
	36
46ddf551 FB	37	#define set_flags(X,new,mask) \
	38	((X) = ((X) & ~(mask)) \| ((new) & (mask)))
	39
	40	#define SAFE_MASK (0xDD5)
	41	#define RETURN_MASK (0xDFF)
	42
	43	static inline int is_revectored(int nr, struct target_revectored_struct *bitmap)
	44	{
b333af06	45	return (((uint8_t *)bitmap)[nr >> 3] >> (nr & 7)) & 1;
46ddf551 FB	46	}
46ddf551 FB	47
1455bf48	48	static inline void vm_putw(uint32_t segptr, unsigned int reg16, unsigned int val)
46ddf551	49	{
84fa15d8	50	stw(segptr + (reg16 & 0xffff), val);
46ddf551 FB	51	}
46ddf551 FB	52
1455bf48	53	static inline void vm_putl(uint32_t segptr, unsigned int reg16, unsigned int val)
46ddf551	54	{
84fa15d8	55	stl(segptr + (reg16 & 0xffff), val);
46ddf551 FB	56	}
46ddf551 FB	57
1455bf48 FB	58	static inline unsigned int vm_getb(uint32_t segptr, unsigned int reg16)
	59	{
	60	return ldub(segptr + (reg16 & 0xffff));
	61	}
	62
	63	static inline unsigned int vm_getw(uint32_t segptr, unsigned int reg16)
46ddf551	64	{
84fa15d8	65	return lduw(segptr + (reg16 & 0xffff));
46ddf551 FB	66	}
46ddf551 FB	67
1455bf48	68	static inline unsigned int vm_getl(uint32_t segptr, unsigned int reg16)
46ddf551	69	{
84fa15d8	70	return ldl(segptr + (reg16 & 0xffff));
46ddf551 FB	71	}
	72
	73	void save_v86_state(CPUX86State *env)
	74	{
	75	TaskState *ts = env->opaque;
53a5960a	76	struct target_vm86plus_struct * target_v86;
46ddf551	77
579a97f7 FB	78	if (!lock_user_struct(VERIFY_WRITE, target_v86, ts->target_v86, 0))
	79	/* FIXME - should return an error */
	80	return;
46ddf551	81	/* put the VM86 registers in the userspace register structure */
53a5960a PB	82	target_v86->regs.eax = tswap32(env->regs[R_EAX]);
	83	target_v86->regs.ebx = tswap32(env->regs[R_EBX]);
	84	target_v86->regs.ecx = tswap32(env->regs[R_ECX]);
	85	target_v86->regs.edx = tswap32(env->regs[R_EDX]);
	86	target_v86->regs.esi = tswap32(env->regs[R_ESI]);
	87	target_v86->regs.edi = tswap32(env->regs[R_EDI]);
	88	target_v86->regs.ebp = tswap32(env->regs[R_EBP]);
	89	target_v86->regs.esp = tswap32(env->regs[R_ESP]);
	90	target_v86->regs.eip = tswap32(env->eip);
	91	target_v86->regs.cs = tswap16(env->segs[R_CS].selector);
	92	target_v86->regs.ss = tswap16(env->segs[R_SS].selector);
	93	target_v86->regs.ds = tswap16(env->segs[R_DS].selector);
	94	target_v86->regs.es = tswap16(env->segs[R_ES].selector);
	95	target_v86->regs.fs = tswap16(env->segs[R_FS].selector);
	96	target_v86->regs.gs = tswap16(env->segs[R_GS].selector);
46ddf551	97	set_flags(env->eflags, ts->v86flags, VIF_MASK \| ts->v86mask);
53a5960a PB	98	target_v86->regs.eflags = tswap32(env->eflags);
53a5960a PB	99	unlock_user_struct(target_v86, ts->target_v86, 1);
d12d51d5 AL	100	LOG_VM86("save_v86_state: eflags=%08x cs:ip=%04x:%04x\n",
d12d51d5 AL	101	env->eflags, env->segs[R_CS].selector, env->eip);
46ddf551 FB	102
	103	/* restore 32 bit registers */
	104	env->regs[R_EAX] = ts->vm86_saved_regs.eax;
	105	env->regs[R_EBX] = ts->vm86_saved_regs.ebx;
	106	env->regs[R_ECX] = ts->vm86_saved_regs.ecx;
	107	env->regs[R_EDX] = ts->vm86_saved_regs.edx;
	108	env->regs[R_ESI] = ts->vm86_saved_regs.esi;
	109	env->regs[R_EDI] = ts->vm86_saved_regs.edi;
	110	env->regs[R_EBP] = ts->vm86_saved_regs.ebp;
	111	env->regs[R_ESP] = ts->vm86_saved_regs.esp;
	112	env->eflags = ts->vm86_saved_regs.eflags;
	113	env->eip = ts->vm86_saved_regs.eip;
	114
	115	cpu_x86_load_seg(env, R_CS, ts->vm86_saved_regs.cs);
	116	cpu_x86_load_seg(env, R_SS, ts->vm86_saved_regs.ss);
	117	cpu_x86_load_seg(env, R_DS, ts->vm86_saved_regs.ds);
	118	cpu_x86_load_seg(env, R_ES, ts->vm86_saved_regs.es);
	119	cpu_x86_load_seg(env, R_FS, ts->vm86_saved_regs.fs);
	120	cpu_x86_load_seg(env, R_GS, ts->vm86_saved_regs.gs);
	121	}
	122
	123	/* return from vm86 mode to 32 bit. The vm86() syscall will return
	124	'retval' */
	125	static inline void return_to_32bit(CPUX86State *env, int retval)
	126	{
d12d51d5	127	LOG_VM86("return_to_32bit: ret=0x%x\n", retval);
46ddf551 FB	128	save_v86_state(env);
	129	env->regs[R_EAX] = retval;
	130	}
	131
	132	static inline int set_IF(CPUX86State *env)
	133	{
	134	TaskState *ts = env->opaque;
3b46e624	135
46ddf551 FB	136	ts->v86flags \|= VIF_MASK;
	137	if (ts->v86flags & VIP_MASK) {
	138	return_to_32bit(env, TARGET_VM86_STI);
	139	return 1;
	140	}
	141	return 0;
	142	}
	143
	144	static inline void clear_IF(CPUX86State *env)
	145	{
	146	TaskState *ts = env->opaque;
	147
	148	ts->v86flags &= ~VIF_MASK;
	149	}
	150
	151	static inline void clear_TF(CPUX86State *env)
	152	{
	153	env->eflags &= ~TF_MASK;
	154	}
	155
226c9132 FB	156	static inline void clear_AC(CPUX86State *env)
	157	{
	158	env->eflags &= ~AC_MASK;
	159	}
	160
46ddf551 FB	161	static inline int set_vflags_long(unsigned long eflags, CPUX86State *env)
	162	{
	163	TaskState *ts = env->opaque;
	164
	165	set_flags(ts->v86flags, eflags, ts->v86mask);
	166	set_flags(env->eflags, eflags, SAFE_MASK);
	167	if (eflags & IF_MASK)
	168	return set_IF(env);
226c9132 FB	169	else
226c9132 FB	170	clear_IF(env);
46ddf551 FB	171	return 0;
	172	}
	173
	174	static inline int set_vflags_short(unsigned short flags, CPUX86State *env)
	175	{
	176	TaskState *ts = env->opaque;
	177
	178	set_flags(ts->v86flags, flags, ts->v86mask & 0xffff);
	179	set_flags(env->eflags, flags, SAFE_MASK);
	180	if (flags & IF_MASK)
	181	return set_IF(env);
226c9132 FB	182	else
226c9132 FB	183	clear_IF(env);
46ddf551 FB	184	return 0;
	185	}
	186
	187	static inline unsigned int get_vflags(CPUX86State *env)
	188	{
	189	TaskState *ts = env->opaque;
	190	unsigned int flags;
	191
	192	flags = env->eflags & RETURN_MASK;
	193	if (ts->v86flags & VIF_MASK)
	194	flags \|= IF_MASK;
c05bab77	195	flags \|= IOPL_MASK;
46ddf551 FB	196	return flags \| (ts->v86flags & ts->v86mask);
	197	}
	198
	199	#define ADD16(reg, val) reg = (reg & ~0xffff) \| ((reg + (val)) & 0xffff)
	200
	201	/* handle VM86 interrupt (NOTE: the CPU core currently does not
	202	support TSS interrupt revectoring, so this code is always executed) */
447db213	203	static void do_int(CPUX86State *env, int intno)
46ddf551 FB	204	{
46ddf551 FB	205	TaskState *ts = env->opaque;
1455bf48	206	uint32_t int_addr, segoffs, ssp;
46ddf551 FB	207	unsigned int sp;
46ddf551 FB	208
c05bab77	209	if (env->segs[R_CS].selector == TARGET_BIOSSEG)
46ddf551	210	goto cannot_handle;
b333af06	211	if (is_revectored(intno, &ts->vm86plus.int_revectored))
46ddf551	212	goto cannot_handle;
5fafdf24	213	if (intno == 0x21 && is_revectored((env->regs[R_EAX] >> 8) & 0xff,
b333af06	214	&ts->vm86plus.int21_revectored))
46ddf551	215	goto cannot_handle;
1455bf48 FB	216	int_addr = (intno << 2);
1455bf48 FB	217	segoffs = ldl(int_addr);
46ddf551 FB	218	if ((segoffs >> 16) == TARGET_BIOSSEG)
46ddf551 FB	219	goto cannot_handle;
d12d51d5 AL	220	LOG_VM86("VM86: emulating int 0x%x. CS:IP=%04x:%04x\n",
d12d51d5 AL	221	intno, segoffs >> 16, segoffs & 0xffff);
46ddf551	222	/* save old state */
1455bf48	223	ssp = env->segs[R_SS].selector << 4;
46ddf551 FB	224	sp = env->regs[R_ESP] & 0xffff;
46ddf551 FB	225	vm_putw(ssp, sp - 2, get_vflags(env));
c05bab77	226	vm_putw(ssp, sp - 4, env->segs[R_CS].selector);
46ddf551 FB	227	vm_putw(ssp, sp - 6, env->eip);
	228	ADD16(env->regs[R_ESP], -6);
	229	/* goto interrupt handler */
	230	env->eip = segoffs & 0xffff;
	231	cpu_x86_load_seg(env, R_CS, segoffs >> 16);
	232	clear_TF(env);
	233	clear_IF(env);
226c9132	234	clear_AC(env);
46ddf551 FB	235	return;
46ddf551 FB	236	cannot_handle:
d12d51d5	237	LOG_VM86("VM86: return to 32 bits int 0x%x\n", intno);
46ddf551 FB	238	return_to_32bit(env, TARGET_VM86_INTx \| (intno << 8));
	239	}
	240
447db213 FB	241	void handle_vm86_trap(CPUX86State *env, int trapno)
	242	{
	243	if (trapno == 1 \|\| trapno == 3) {
	244	return_to_32bit(env, TARGET_VM86_TRAP + (trapno << 8));
	245	} else {
	246	do_int(env, trapno);
	247	}
	248	}
	249
b333af06 FB	250	#define CHECK_IF_IN_TRAP() \
	251	if ((ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_active) && \
	252	(ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_TFpendig)) \
	253	newflags \|= TF_MASK
46ddf551 FB	254
46ddf551 FB	255	#define VM86_FAULT_RETURN \
b333af06	256	if ((ts->vm86plus.vm86plus.flags & TARGET_force_return_for_pic) && \
46ddf551 FB	257	(ts->v86flags & (IF_MASK \| VIF_MASK))) \
	258	return_to_32bit(env, TARGET_VM86_PICRETURN); \
	259	return
	260
	261	void handle_vm86_fault(CPUX86State *env)
	262	{
	263	TaskState *ts = env->opaque;
1455bf48	264	uint32_t csp, ssp;
b333af06 FB	265	unsigned int ip, sp, newflags, newip, newcs, opcode, intno;
b333af06 FB	266	int data32, pref_done;
46ddf551	267
1455bf48	268	csp = env->segs[R_CS].selector << 4;
46ddf551	269	ip = env->eip & 0xffff;
3b46e624	270
1455bf48	271	ssp = env->segs[R_SS].selector << 4;
46ddf551 FB	272	sp = env->regs[R_ESP] & 0xffff;
46ddf551 FB	273
d12d51d5 AL	274	LOG_VM86("VM86 exception %04x:%08x\n",
d12d51d5 AL	275	env->segs[R_CS].selector, env->eip);
46ddf551	276
b333af06 FB	277	data32 = 0;
	278	pref_done = 0;
	279	do {
1455bf48	280	opcode = vm_getb(csp, ip);
b333af06 FB	281	ADD16(ip, 1);
	282	switch (opcode) {
	283	case 0x66: /* 32-bit data */ data32=1; break;
	284	case 0x67: /* 32-bit address */ break;
	285	case 0x2e: /* CS */ break;
	286	case 0x3e: /* DS */ break;
	287	case 0x26: /* ES */ break;
	288	case 0x36: /* SS */ break;
	289	case 0x65: /* GS */ break;
	290	case 0x64: /* FS */ break;
	291	case 0xf2: /* repnz */ break;
	292	case 0xf3: /* rep */ break;
	293	default: pref_done = 1;
	294	}
	295	} while (!pref_done);
	296
46ddf551	297	/* VM86 mode */
b333af06 FB	298	switch(opcode) {
b333af06 FB	299	case 0x9c: /* pushf */
b333af06	300	if (data32) {
46ddf551	301	vm_putl(ssp, sp - 4, get_vflags(env));
b333af06 FB	302	ADD16(env->regs[R_ESP], -4);
	303	} else {
	304	vm_putw(ssp, sp - 2, get_vflags(env));
	305	ADD16(env->regs[R_ESP], -2);
	306	}
	307	env->eip = ip;
	308	VM86_FAULT_RETURN;
46ddf551	309
b333af06 FB	310	case 0x9d: /* popf */
	311	if (data32) {
	312	newflags = vm_getl(ssp, sp);
46ddf551	313	ADD16(env->regs[R_ESP], 4);
b333af06 FB	314	} else {
	315	newflags = vm_getw(ssp, sp);
	316	ADD16(env->regs[R_ESP], 2);
	317	}
	318	env->eip = ip;
	319	CHECK_IF_IN_TRAP();
	320	if (data32) {
	321	if (set_vflags_long(newflags, env))
46ddf551	322	return;
b333af06 FB	323	} else {
b333af06 FB	324	if (set_vflags_short(newflags, env))
46ddf551	325	return;
46ddf551	326	}
46ddf551 FB	327	VM86_FAULT_RETURN;
	328
	329	case 0xcd: /* int */
1455bf48	330	intno = vm_getb(csp, ip);
b333af06 FB	331	ADD16(ip, 1);
	332	env->eip = ip;
	333	if (ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_active) {
5fafdf24	334	if ( (ts->vm86plus.vm86plus.vm86dbg_intxxtab[intno >> 3] >>
b333af06 FB	335	(intno &7)) & 1) {
	336	return_to_32bit(env, TARGET_VM86_INTx + (intno << 8));
	337	return;
	338	}
	339	}
	340	do_int(env, intno);
46ddf551 FB	341	break;
	342
	343	case 0xcf: /* iret */
b333af06 FB	344	if (data32) {
	345	newip = vm_getl(ssp, sp) & 0xffff;
	346	newcs = vm_getl(ssp, sp + 4) & 0xffff;
	347	newflags = vm_getl(ssp, sp + 8);
	348	ADD16(env->regs[R_ESP], 12);
	349	} else {
	350	newip = vm_getw(ssp, sp);
	351	newcs = vm_getw(ssp, sp + 2);
	352	newflags = vm_getw(ssp, sp + 4);
	353	ADD16(env->regs[R_ESP], 6);
	354	}
	355	env->eip = newip;
	356	cpu_x86_load_seg(env, R_CS, newcs);
	357	CHECK_IF_IN_TRAP();
	358	if (data32) {
	359	if (set_vflags_long(newflags, env))
	360	return;
	361	} else {
	362	if (set_vflags_short(newflags, env))
	363	return;
	364	}
46ddf551	365	VM86_FAULT_RETURN;
3b46e624	366
46ddf551	367	case 0xfa: /* cli */
b333af06	368	env->eip = ip;
46ddf551 FB	369	clear_IF(env);
46ddf551 FB	370	VM86_FAULT_RETURN;
3b46e624	371
46ddf551	372	case 0xfb: /* sti */
b333af06	373	env->eip = ip;
46ddf551 FB	374	if (set_IF(env))
	375	return;
	376	VM86_FAULT_RETURN;
	377
	378	default:
46ddf551 FB	379	/* real VM86 GPF exception */
	380	return_to_32bit(env, TARGET_VM86_UNKNOWN);
	381	break;
	382	}
	383	}
	384
992f48a0	385	int do_vm86(CPUX86State *env, long subfunction, abi_ulong vm86_addr)
46ddf551 FB	386	{
46ddf551 FB	387	TaskState *ts = env->opaque;
53a5960a	388	struct target_vm86plus_struct * target_v86;
46ddf551	389	int ret;
3b46e624	390
46ddf551 FB	391	switch (subfunction) {
	392	case TARGET_VM86_REQUEST_IRQ:
	393	case TARGET_VM86_FREE_IRQ:
	394	case TARGET_VM86_GET_IRQ_BITS:
	395	case TARGET_VM86_GET_AND_RESET_IRQ:
	396	gemu_log("qemu: unsupported vm86 subfunction (%ld)\n", subfunction);
6c30b07f	397	ret = -TARGET_EINVAL;
46ddf551 FB	398	goto out;
	399	case TARGET_VM86_PLUS_INSTALL_CHECK:
	400	/* NOTE: on old vm86 stuff this will return the error
	401	from verify_area(), because the subfunction is
	402	interpreted as (invalid) address to vm86_struct.
	403	So the installation check works.
	404	*/
	405	ret = 0;
	406	goto out;
	407	}
	408
46ddf551 FB	409	/* save current CPU regs */
	410	ts->vm86_saved_regs.eax = 0; /* default vm86 syscall return code */
	411	ts->vm86_saved_regs.ebx = env->regs[R_EBX];
	412	ts->vm86_saved_regs.ecx = env->regs[R_ECX];
	413	ts->vm86_saved_regs.edx = env->regs[R_EDX];
	414	ts->vm86_saved_regs.esi = env->regs[R_ESI];
	415	ts->vm86_saved_regs.edi = env->regs[R_EDI];
	416	ts->vm86_saved_regs.ebp = env->regs[R_EBP];
	417	ts->vm86_saved_regs.esp = env->regs[R_ESP];
	418	ts->vm86_saved_regs.eflags = env->eflags;
	419	ts->vm86_saved_regs.eip = env->eip;
c05bab77 FB	420	ts->vm86_saved_regs.cs = env->segs[R_CS].selector;
	421	ts->vm86_saved_regs.ss = env->segs[R_SS].selector;
	422	ts->vm86_saved_regs.ds = env->segs[R_DS].selector;
	423	ts->vm86_saved_regs.es = env->segs[R_ES].selector;
	424	ts->vm86_saved_regs.fs = env->segs[R_FS].selector;
	425	ts->vm86_saved_regs.gs = env->segs[R_GS].selector;
46ddf551	426
53a5960a	427	ts->target_v86 = vm86_addr;
579a97f7	428	if (!lock_user_struct(VERIFY_READ, target_v86, vm86_addr, 1))
6c30b07f	429	return -TARGET_EFAULT;
46ddf551 FB	430	/* build vm86 CPU state */
46ddf551 FB	431	ts->v86flags = tswap32(target_v86->regs.eflags);
5fafdf24	432	env->eflags = (env->eflags & ~SAFE_MASK) \|
46ddf551	433	(tswap32(target_v86->regs.eflags) & SAFE_MASK) \| VM_MASK;
b333af06 FB	434
	435	ts->vm86plus.cpu_type = tswapl(target_v86->cpu_type);
	436	switch (ts->vm86plus.cpu_type) {
	437	case TARGET_CPU_286:
	438	ts->v86mask = 0;
	439	break;
	440	case TARGET_CPU_386:
	441	ts->v86mask = NT_MASK \| IOPL_MASK;
	442	break;
	443	case TARGET_CPU_486:
	444	ts->v86mask = AC_MASK \| NT_MASK \| IOPL_MASK;
	445	break;
	446	default:
	447	ts->v86mask = ID_MASK \| AC_MASK \| NT_MASK \| IOPL_MASK;
	448	break;
	449	}
46ddf551 FB	450
	451	env->regs[R_EBX] = tswap32(target_v86->regs.ebx);
	452	env->regs[R_ECX] = tswap32(target_v86->regs.ecx);
	453	env->regs[R_EDX] = tswap32(target_v86->regs.edx);
	454	env->regs[R_ESI] = tswap32(target_v86->regs.esi);
	455	env->regs[R_EDI] = tswap32(target_v86->regs.edi);
	456	env->regs[R_EBP] = tswap32(target_v86->regs.ebp);
	457	env->regs[R_ESP] = tswap32(target_v86->regs.esp);
	458	env->eip = tswap32(target_v86->regs.eip);
	459	cpu_x86_load_seg(env, R_CS, tswap16(target_v86->regs.cs));
	460	cpu_x86_load_seg(env, R_SS, tswap16(target_v86->regs.ss));
	461	cpu_x86_load_seg(env, R_DS, tswap16(target_v86->regs.ds));
	462	cpu_x86_load_seg(env, R_ES, tswap16(target_v86->regs.es));
	463	cpu_x86_load_seg(env, R_FS, tswap16(target_v86->regs.fs));
	464	cpu_x86_load_seg(env, R_GS, tswap16(target_v86->regs.gs));
	465	ret = tswap32(target_v86->regs.eax); /* eax will be restored at
	466	the end of the syscall */
5fafdf24	467	memcpy(&ts->vm86plus.int_revectored,
b333af06	468	&target_v86->int_revectored, 32);
5fafdf24	469	memcpy(&ts->vm86plus.int21_revectored,
b333af06 FB	470	&target_v86->int21_revectored, 32);
b333af06 FB	471	ts->vm86plus.vm86plus.flags = tswapl(target_v86->vm86plus.flags);
5fafdf24	472	memcpy(&ts->vm86plus.vm86plus.vm86dbg_intxxtab,
b333af06	473	target_v86->vm86plus.vm86dbg_intxxtab, 32);
53a5960a	474	unlock_user_struct(target_v86, vm86_addr, 0);
3b46e624	475
d12d51d5 AL	476	LOG_VM86("do_vm86: cs:ip=%04x:%04x\n",
d12d51d5 AL	477	env->segs[R_CS].selector, env->eip);
46ddf551 FB	478	/* now the virtual CPU is ready for vm86 execution ! */
	479	out:
	480	return ret;
	481	}