[qemu.git] / hw / misc / aspeed_scu.c

/*
 * ASPEED System Control Unit
 *
 * Andrew Jeffery <[email protected]>
 *
 * Copyright 2016 IBM Corp.
 *
 * This code is licensed under the GPL version 2 or later.  See
 * the COPYING file in the top-level directory.
 */

#include "qemu/osdep.h"
#include "hw/misc/aspeed_scu.h"
#include "hw/qdev-properties.h"
#include "qapi/error.h"
#include "qapi/visitor.h"
#include "qemu/bitops.h"
#include "qemu/log.h"
#include "trace.h"

#define TO_REG(offset) ((offset) >> 2)

#define PROT_KEY             TO_REG(0x00)
#define SYS_RST_CTRL         TO_REG(0x04)
#define CLK_SEL              TO_REG(0x08)
#define CLK_STOP_CTRL        TO_REG(0x0C)
#define FREQ_CNTR_CTRL       TO_REG(0x10)
#define FREQ_CNTR_EVAL       TO_REG(0x14)
#define IRQ_CTRL             TO_REG(0x18)
#define D2PLL_PARAM          TO_REG(0x1C)
#define MPLL_PARAM           TO_REG(0x20)
#define HPLL_PARAM           TO_REG(0x24)
#define FREQ_CNTR_RANGE      TO_REG(0x28)
#define MISC_CTRL1           TO_REG(0x2C)
#define PCI_CTRL1            TO_REG(0x30)
#define PCI_CTRL2            TO_REG(0x34)
#define PCI_CTRL3            TO_REG(0x38)
#define SYS_RST_STATUS       TO_REG(0x3C)
#define SOC_SCRATCH1         TO_REG(0x40)
#define SOC_SCRATCH2         TO_REG(0x44)
#define MAC_CLK_DELAY        TO_REG(0x48)
#define MISC_CTRL2           TO_REG(0x4C)
#define VGA_SCRATCH1         TO_REG(0x50)
#define VGA_SCRATCH2         TO_REG(0x54)
#define VGA_SCRATCH3         TO_REG(0x58)
#define VGA_SCRATCH4         TO_REG(0x5C)
#define VGA_SCRATCH5         TO_REG(0x60)
#define VGA_SCRATCH6         TO_REG(0x64)
#define VGA_SCRATCH7         TO_REG(0x68)
#define VGA_SCRATCH8         TO_REG(0x6C)
#define HW_STRAP1            TO_REG(0x70)
#define RNG_CTRL             TO_REG(0x74)
#define RNG_DATA             TO_REG(0x78)
#define SILICON_REV          TO_REG(0x7C)
#define PINMUX_CTRL1         TO_REG(0x80)
#define PINMUX_CTRL2         TO_REG(0x84)
#define PINMUX_CTRL3         TO_REG(0x88)
#define PINMUX_CTRL4         TO_REG(0x8C)
#define PINMUX_CTRL5         TO_REG(0x90)
#define PINMUX_CTRL6         TO_REG(0x94)
#define WDT_RST_CTRL         TO_REG(0x9C)
#define PINMUX_CTRL7         TO_REG(0xA0)
#define PINMUX_CTRL8         TO_REG(0xA4)
#define PINMUX_CTRL9         TO_REG(0xA8)
#define WAKEUP_EN            TO_REG(0xC0)
#define WAKEUP_CTRL          TO_REG(0xC4)
#define HW_STRAP2            TO_REG(0xD0)
#define FREE_CNTR4           TO_REG(0xE0)
#define FREE_CNTR4_EXT       TO_REG(0xE4)
#define CPU2_CTRL            TO_REG(0x100)
#define CPU2_BASE_SEG1       TO_REG(0x104)
#define CPU2_BASE_SEG2       TO_REG(0x108)
#define CPU2_BASE_SEG3       TO_REG(0x10C)
#define CPU2_BASE_SEG4       TO_REG(0x110)
#define CPU2_BASE_SEG5       TO_REG(0x114)
#define CPU2_CACHE_CTRL      TO_REG(0x118)
#define UART_HPLL_CLK        TO_REG(0x160)
#define PCIE_CTRL            TO_REG(0x180)
#define BMC_MMIO_CTRL        TO_REG(0x184)
#define RELOC_DECODE_BASE1   TO_REG(0x188)
#define RELOC_DECODE_BASE2   TO_REG(0x18C)
#define MAILBOX_DECODE_BASE  TO_REG(0x190)
#define SRAM_DECODE_BASE1    TO_REG(0x194)
#define SRAM_DECODE_BASE2    TO_REG(0x198)
#define BMC_REV              TO_REG(0x19C)
#define BMC_DEV_ID           TO_REG(0x1A4)

#define SCU_IO_REGION_SIZE 0x1000

static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = {
     [SYS_RST_CTRL]    = 0xFFCFFEDCU,
     [CLK_SEL]         = 0xF3F40000U,
     [CLK_STOP_CTRL]   = 0x19FC3E8BU,
     [D2PLL_PARAM]     = 0x00026108U,
     [MPLL_PARAM]      = 0x00030291U,
     [HPLL_PARAM]      = 0x00000291U,
     [MISC_CTRL1]      = 0x00000010U,
     [PCI_CTRL1]       = 0x20001A03U,
     [PCI_CTRL2]       = 0x20001A03U,
     [PCI_CTRL3]       = 0x04000030U,
     [SYS_RST_STATUS]  = 0x00000001U,
     [SOC_SCRATCH1]    = 0x000000C0U, /* SoC completed DRAM init */
     [MISC_CTRL2]      = 0x00000023U,
     [RNG_CTRL]        = 0x0000000EU,
     [PINMUX_CTRL2]    = 0x0000F000U,
     [PINMUX_CTRL3]    = 0x01000000U,
     [PINMUX_CTRL4]    = 0x000000FFU,
     [PINMUX_CTRL5]    = 0x0000A000U,
     [WDT_RST_CTRL]    = 0x003FFFF3U,
     [PINMUX_CTRL8]    = 0xFFFF0000U,
     [PINMUX_CTRL9]    = 0x000FFFFFU,
     [FREE_CNTR4]      = 0x000000FFU,
     [FREE_CNTR4_EXT]  = 0x000000FFU,
     [CPU2_BASE_SEG1]  = 0x80000000U,
     [CPU2_BASE_SEG4]  = 0x1E600000U,
     [CPU2_BASE_SEG5]  = 0xC0000000U,
     [UART_HPLL_CLK]   = 0x00001903U,
     [PCIE_CTRL]       = 0x0000007BU,
     [BMC_DEV_ID]      = 0x00002402U
};

/* SCU70 bit 23: 0 24Mhz. bit 11:9: 0b001 AXI:ABH ratio 2:1 */
/* AST2500 revision A1 */

static const uint32_t ast2500_a1_resets[ASPEED_SCU_NR_REGS] = {
     [SYS_RST_CTRL]    = 0xFFCFFEDCU,
     [CLK_SEL]         = 0xF3F40000U,
     [CLK_STOP_CTRL]   = 0x19FC3E8BU,
     [D2PLL_PARAM]     = 0x00026108U,
     [MPLL_PARAM]      = 0x00030291U,
     [HPLL_PARAM]      = 0x93000400U,
     [MISC_CTRL1]      = 0x00000010U,
     [PCI_CTRL1]       = 0x20001A03U,
     [PCI_CTRL2]       = 0x20001A03U,
     [PCI_CTRL3]       = 0x04000030U,
     [SYS_RST_STATUS]  = 0x00000001U,
     [SOC_SCRATCH1]    = 0x000000C0U, /* SoC completed DRAM init */
     [MISC_CTRL2]      = 0x00000023U,
     [RNG_CTRL]        = 0x0000000EU,
     [PINMUX_CTRL2]    = 0x0000F000U,
     [PINMUX_CTRL3]    = 0x03000000U,
     [PINMUX_CTRL4]    = 0x00000000U,
     [PINMUX_CTRL5]    = 0x0000A000U,
     [WDT_RST_CTRL]    = 0x023FFFF3U,
     [PINMUX_CTRL8]    = 0xFFFF0000U,
     [PINMUX_CTRL9]    = 0x000FFFFFU,
     [FREE_CNTR4]      = 0x000000FFU,
     [FREE_CNTR4_EXT]  = 0x000000FFU,
     [CPU2_BASE_SEG1]  = 0x80000000U,
     [CPU2_BASE_SEG4]  = 0x1E600000U,
     [CPU2_BASE_SEG5]  = 0xC0000000U,
     [UART_HPLL_CLK]   = 0x00001903U,
     [PCIE_CTRL]       = 0x0000007BU,
     [BMC_DEV_ID]      = 0x00002402U
};

static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
{
    AspeedSCUState *s = ASPEED_SCU(opaque);
    int reg = TO_REG(offset);

    if (reg >= ARRAY_SIZE(s->regs)) {
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
                      __func__, offset);
        return 0;
    }

    switch (reg) {
    case WAKEUP_EN:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: Read of write-only offset 0x%" HWADDR_PRIx "\n",
                      __func__, offset);
        break;
    }

    return s->regs[reg];
}

static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
                             unsigned size)
{
    AspeedSCUState *s = ASPEED_SCU(opaque);
    int reg = TO_REG(offset);

    if (reg >= ARRAY_SIZE(s->regs)) {
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
                      __func__, offset);
        return;
    }

    if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 &&
            !s->regs[PROT_KEY]) {
        qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__);
        return;
    }

    trace_aspeed_scu_write(offset, size, data);

    switch (reg) {
    case PROT_KEY:
        s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
        return;

    case FREQ_CNTR_EVAL:
    case VGA_SCRATCH1 ... VGA_SCRATCH8:
    case RNG_DATA:
    case SILICON_REV:
    case FREE_CNTR4:
    case FREE_CNTR4_EXT:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
                      __func__, offset);
        return;
    }

    s->regs[reg] = data;
}

static const MemoryRegionOps aspeed_scu_ops = {
    .read = aspeed_scu_read,
    .write = aspeed_scu_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
    .valid.min_access_size = 4,
    .valid.max_access_size = 4,
    .valid.unaligned = false,
};

static void aspeed_scu_reset(DeviceState *dev)
{
    AspeedSCUState *s = ASPEED_SCU(dev);
    const uint32_t *reset;

    switch (s->silicon_rev) {
    case AST2400_A0_SILICON_REV:
    case AST2400_A1_SILICON_REV:
        reset = ast2400_a0_resets;
        break;
    case AST2500_A0_SILICON_REV:
    case AST2500_A1_SILICON_REV:
        reset = ast2500_a1_resets;
        break;
    default:
        g_assert_not_reached();
    }

    memcpy(s->regs, reset, sizeof(s->regs));
    s->regs[SILICON_REV] = s->silicon_rev;
    s->regs[HW_STRAP1] = s->hw_strap1;
    s->regs[HW_STRAP2] = s->hw_strap2;
    s->regs[PROT_KEY] = s->hw_prot_key;
}

static uint32_t aspeed_silicon_revs[] = {
    AST2400_A0_SILICON_REV,
    AST2400_A1_SILICON_REV,
    AST2500_A0_SILICON_REV,
    AST2500_A1_SILICON_REV,
};

bool is_supported_silicon_rev(uint32_t silicon_rev)
{
    int i;

    for (i = 0; i < ARRAY_SIZE(aspeed_silicon_revs); i++) {
        if (silicon_rev == aspeed_silicon_revs[i]) {
            return true;
        }
    }

    return false;
}

static void aspeed_scu_realize(DeviceState *dev, Error **errp)
{
    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
    AspeedSCUState *s = ASPEED_SCU(dev);

    if (!is_supported_silicon_rev(s->silicon_rev)) {
        error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,
                s->silicon_rev);
        return;
    }

    memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_scu_ops, s,
                          TYPE_ASPEED_SCU, SCU_IO_REGION_SIZE);

    sysbus_init_mmio(sbd, &s->iomem);
}

static const VMStateDescription vmstate_aspeed_scu = {
    .name = "aspeed.scu",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_SCU_NR_REGS),
        VMSTATE_END_OF_LIST()
    }
};

static Property aspeed_scu_properties[] = {
    DEFINE_PROP_UINT32("silicon-rev", AspeedSCUState, silicon_rev, 0),
    DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0),
    DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0),
    DEFINE_PROP_UINT32("hw-prot-key", AspeedSCUState, hw_prot_key, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void aspeed_scu_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    dc->realize = aspeed_scu_realize;
    dc->reset = aspeed_scu_reset;
    dc->desc = "ASPEED System Control Unit";
    dc->vmsd = &vmstate_aspeed_scu;
    dc->props = aspeed_scu_properties;
}

static const TypeInfo aspeed_scu_info = {
    .name = TYPE_ASPEED_SCU,
    .parent = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(AspeedSCUState),
    .class_init = aspeed_scu_class_init,
};

static void aspeed_scu_register_types(void)
{
    type_register_static(&aspeed_scu_info);
}

type_init(aspeed_scu_register_types);
Commit	Line	Data
1c8a2388 AJ	1	/*
	2	* ASPEED System Control Unit
	3	*
	4	* Andrew Jeffery <[email protected]>
	5	*
	6	* Copyright 2016 IBM Corp.
	7	*
	8	* This code is licensed under the GPL version 2 or later. See
	9	* the COPYING file in the top-level directory.
	10	*/
	11
	12	#include "qemu/osdep.h"
	13	#include "hw/misc/aspeed_scu.h"
	14	#include "hw/qdev-properties.h"
	15	#include "qapi/error.h"
	16	#include "qapi/visitor.h"
	17	#include "qemu/bitops.h"
aa4b04a0	18	#include "qemu/log.h"
1c8a2388 AJ	19	#include "trace.h"
	20
	21	#define TO_REG(offset) ((offset) >> 2)
	22
	23	#define PROT_KEY TO_REG(0x00)
	24	#define SYS_RST_CTRL TO_REG(0x04)
	25	#define CLK_SEL TO_REG(0x08)
	26	#define CLK_STOP_CTRL TO_REG(0x0C)
	27	#define FREQ_CNTR_CTRL TO_REG(0x10)
	28	#define FREQ_CNTR_EVAL TO_REG(0x14)
	29	#define IRQ_CTRL TO_REG(0x18)
	30	#define D2PLL_PARAM TO_REG(0x1C)
	31	#define MPLL_PARAM TO_REG(0x20)
	32	#define HPLL_PARAM TO_REG(0x24)
	33	#define FREQ_CNTR_RANGE TO_REG(0x28)
	34	#define MISC_CTRL1 TO_REG(0x2C)
	35	#define PCI_CTRL1 TO_REG(0x30)
	36	#define PCI_CTRL2 TO_REG(0x34)
	37	#define PCI_CTRL3 TO_REG(0x38)
	38	#define SYS_RST_STATUS TO_REG(0x3C)
	39	#define SOC_SCRATCH1 TO_REG(0x40)
	40	#define SOC_SCRATCH2 TO_REG(0x44)
	41	#define MAC_CLK_DELAY TO_REG(0x48)
	42	#define MISC_CTRL2 TO_REG(0x4C)
	43	#define VGA_SCRATCH1 TO_REG(0x50)
	44	#define VGA_SCRATCH2 TO_REG(0x54)
	45	#define VGA_SCRATCH3 TO_REG(0x58)
	46	#define VGA_SCRATCH4 TO_REG(0x5C)
	47	#define VGA_SCRATCH5 TO_REG(0x60)
	48	#define VGA_SCRATCH6 TO_REG(0x64)
	49	#define VGA_SCRATCH7 TO_REG(0x68)
	50	#define VGA_SCRATCH8 TO_REG(0x6C)
	51	#define HW_STRAP1 TO_REG(0x70)
	52	#define RNG_CTRL TO_REG(0x74)
	53	#define RNG_DATA TO_REG(0x78)
	54	#define SILICON_REV TO_REG(0x7C)
	55	#define PINMUX_CTRL1 TO_REG(0x80)
	56	#define PINMUX_CTRL2 TO_REG(0x84)
	57	#define PINMUX_CTRL3 TO_REG(0x88)
	58	#define PINMUX_CTRL4 TO_REG(0x8C)
	59	#define PINMUX_CTRL5 TO_REG(0x90)
	60	#define PINMUX_CTRL6 TO_REG(0x94)
	61	#define WDT_RST_CTRL TO_REG(0x9C)
	62	#define PINMUX_CTRL7 TO_REG(0xA0)
	63	#define PINMUX_CTRL8 TO_REG(0xA4)
	64	#define PINMUX_CTRL9 TO_REG(0xA8)
	65	#define WAKEUP_EN TO_REG(0xC0)
	66	#define WAKEUP_CTRL TO_REG(0xC4)
	67	#define HW_STRAP2 TO_REG(0xD0)
	68	#define FREE_CNTR4 TO_REG(0xE0)
	69	#define FREE_CNTR4_EXT TO_REG(0xE4)
	70	#define CPU2_CTRL TO_REG(0x100)
	71	#define CPU2_BASE_SEG1 TO_REG(0x104)
	72	#define CPU2_BASE_SEG2 TO_REG(0x108)
	73	#define CPU2_BASE_SEG3 TO_REG(0x10C)
	74	#define CPU2_BASE_SEG4 TO_REG(0x110)
	75	#define CPU2_BASE_SEG5 TO_REG(0x114)
	76	#define CPU2_CACHE_CTRL TO_REG(0x118)
	77	#define UART_HPLL_CLK TO_REG(0x160)
	78	#define PCIE_CTRL TO_REG(0x180)
	79	#define BMC_MMIO_CTRL TO_REG(0x184)
	80	#define RELOC_DECODE_BASE1 TO_REG(0x188)
	81	#define RELOC_DECODE_BASE2 TO_REG(0x18C)
	82	#define MAILBOX_DECODE_BASE TO_REG(0x190)
83	#define SRAM_DECODE_BASE1 TO_REG(0x194)
84	#define SRAM_DECODE_BASE2 TO_REG(0x198)
85	#define BMC_REV TO_REG(0x19C)
86	#define BMC_DEV_ID TO_REG(0x1A4)
87
c491e152	88	#define SCU_IO_REGION_SIZE 0x1000
1c8a2388	89
1c8a2388 AJ	90	static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = {
	91	[SYS_RST_CTRL] = 0xFFCFFEDCU,
	92	[CLK_SEL] = 0xF3F40000U,
	93	[CLK_STOP_CTRL] = 0x19FC3E8BU,
	94	[D2PLL_PARAM] = 0x00026108U,
	95	[MPLL_PARAM] = 0x00030291U,
	96	[HPLL_PARAM] = 0x00000291U,
	97	[MISC_CTRL1] = 0x00000010U,
	98	[PCI_CTRL1] = 0x20001A03U,
	99	[PCI_CTRL2] = 0x20001A03U,
	100	[PCI_CTRL3] = 0x04000030U,
	101	[SYS_RST_STATUS] = 0x00000001U,
	102	[SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */
	103	[MISC_CTRL2] = 0x00000023U,
	104	[RNG_CTRL] = 0x0000000EU,
	105	[PINMUX_CTRL2] = 0x0000F000U,
	106	[PINMUX_CTRL3] = 0x01000000U,
	107	[PINMUX_CTRL4] = 0x000000FFU,
	108	[PINMUX_CTRL5] = 0x0000A000U,
	109	[WDT_RST_CTRL] = 0x003FFFF3U,
	110	[PINMUX_CTRL8] = 0xFFFF0000U,
	111	[PINMUX_CTRL9] = 0x000FFFFFU,
	112	[FREE_CNTR4] = 0x000000FFU,
	113	[FREE_CNTR4_EXT] = 0x000000FFU,
	114	[CPU2_BASE_SEG1] = 0x80000000U,
	115	[CPU2_BASE_SEG4] = 0x1E600000U,
	116	[CPU2_BASE_SEG5] = 0xC0000000U,
	117	[UART_HPLL_CLK] = 0x00001903U,
	118	[PCIE_CTRL] = 0x0000007BU,
	119	[BMC_DEV_ID] = 0x00002402U
	120	};
	121
365aff1e CLG	122	/* SCU70 bit 23: 0 24Mhz. bit 11:9: 0b001 AXI:ABH ratio 2:1 */
	123	/* AST2500 revision A1 */
	124
	125	static const uint32_t ast2500_a1_resets[ASPEED_SCU_NR_REGS] = {
	126	[SYS_RST_CTRL] = 0xFFCFFEDCU,
	127	[CLK_SEL] = 0xF3F40000U,
	128	[CLK_STOP_CTRL] = 0x19FC3E8BU,
	129	[D2PLL_PARAM] = 0x00026108U,
	130	[MPLL_PARAM] = 0x00030291U,
	131	[HPLL_PARAM] = 0x93000400U,
	132	[MISC_CTRL1] = 0x00000010U,
	133	[PCI_CTRL1] = 0x20001A03U,
	134	[PCI_CTRL2] = 0x20001A03U,
	135	[PCI_CTRL3] = 0x04000030U,
	136	[SYS_RST_STATUS] = 0x00000001U,
	137	[SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */
	138	[MISC_CTRL2] = 0x00000023U,
	139	[RNG_CTRL] = 0x0000000EU,
	140	[PINMUX_CTRL2] = 0x0000F000U,
	141	[PINMUX_CTRL3] = 0x03000000U,
	142	[PINMUX_CTRL4] = 0x00000000U,
	143	[PINMUX_CTRL5] = 0x0000A000U,
	144	[WDT_RST_CTRL] = 0x023FFFF3U,
	145	[PINMUX_CTRL8] = 0xFFFF0000U,
	146	[PINMUX_CTRL9] = 0x000FFFFFU,
	147	[FREE_CNTR4] = 0x000000FFU,
	148	[FREE_CNTR4_EXT] = 0x000000FFU,
	149	[CPU2_BASE_SEG1] = 0x80000000U,
	150	[CPU2_BASE_SEG4] = 0x1E600000U,
	151	[CPU2_BASE_SEG5] = 0xC0000000U,
	152	[UART_HPLL_CLK] = 0x00001903U,
	153	[PCIE_CTRL] = 0x0000007BU,
	154	[BMC_DEV_ID] = 0x00002402U
	155	};
	156
1c8a2388 AJ	157	static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
	158	{
	159	AspeedSCUState *s = ASPEED_SCU(opaque);
	160	int reg = TO_REG(offset);
	161
	162	if (reg >= ARRAY_SIZE(s->regs)) {
	163	qemu_log_mask(LOG_GUEST_ERROR,
	164	"%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
	165	__func__, offset);
	166	return 0;
	167	}
	168
	169	switch (reg) {
	170	case WAKEUP_EN:
	171	qemu_log_mask(LOG_GUEST_ERROR,
	172	"%s: Read of write-only offset 0x%" HWADDR_PRIx "\n",
	173	__func__, offset);
	174	break;
	175	}
	176
	177	return s->regs[reg];
	178	}
	179
	180	static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
	181	unsigned size)
	182	{
	183	AspeedSCUState *s = ASPEED_SCU(opaque);
	184	int reg = TO_REG(offset);
	185
	186	if (reg >= ARRAY_SIZE(s->regs)) {
	187	qemu_log_mask(LOG_GUEST_ERROR,
	188	"%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
	189	__func__, offset);
	190	return;
	191	}
	192
	193	if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 &&
5c1d3a2b	194	!s->regs[PROT_KEY]) {
1c8a2388 AJ	195	qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__);
	196	return;
	197	}
	198
	199	trace_aspeed_scu_write(offset, size, data);
	200
	201	switch (reg) {
5c1d3a2b HL	202	case PROT_KEY:
	203	s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
	204	return;
	205
1c8a2388 AJ	206	case FREQ_CNTR_EVAL:
	207	case VGA_SCRATCH1 ... VGA_SCRATCH8:
	208	case RNG_DATA:
	209	case SILICON_REV:
	210	case FREE_CNTR4:
	211	case FREE_CNTR4_EXT:
	212	qemu_log_mask(LOG_GUEST_ERROR,
	213	"%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
	214	__func__, offset);
	215	return;
	216	}
	217
	218	s->regs[reg] = data;
	219	}
	220
	221	static const MemoryRegionOps aspeed_scu_ops = {
	222	.read = aspeed_scu_read,
	223	.write = aspeed_scu_write,
	224	.endianness = DEVICE_LITTLE_ENDIAN,
	225	.valid.min_access_size = 4,
	226	.valid.max_access_size = 4,
	227	.valid.unaligned = false,
	228	};
	229
	230	static void aspeed_scu_reset(DeviceState *dev)
	231	{
	232	AspeedSCUState *s = ASPEED_SCU(dev);
	233	const uint32_t *reset;
	234
	235	switch (s->silicon_rev) {
	236	case AST2400_A0_SILICON_REV:
6efbac90	237	case AST2400_A1_SILICON_REV:
1c8a2388 AJ	238	reset = ast2400_a0_resets;
1c8a2388 AJ	239	break;
365aff1e CLG	240	case AST2500_A0_SILICON_REV:
	241	case AST2500_A1_SILICON_REV:
	242	reset = ast2500_a1_resets;
	243	break;
1c8a2388 AJ	244	default:
	245	g_assert_not_reached();
	246	}
	247
	248	memcpy(s->regs, reset, sizeof(s->regs));
	249	s->regs[SILICON_REV] = s->silicon_rev;
	250	s->regs[HW_STRAP1] = s->hw_strap1;
	251	s->regs[HW_STRAP2] = s->hw_strap2;
b6e70d1d	252	s->regs[PROT_KEY] = s->hw_prot_key;
1c8a2388 AJ	253	}
1c8a2388 AJ	254
365aff1e CLG	255	static uint32_t aspeed_silicon_revs[] = {
365aff1e CLG	256	AST2400_A0_SILICON_REV,
6efbac90	257	AST2400_A1_SILICON_REV,
365aff1e CLG	258	AST2500_A0_SILICON_REV,
	259	AST2500_A1_SILICON_REV,
	260	};
1c8a2388	261
79a9f323	262	bool is_supported_silicon_rev(uint32_t silicon_rev)
1c8a2388 AJ	263	{
	264	int i;
	265
	266	for (i = 0; i < ARRAY_SIZE(aspeed_silicon_revs); i++) {
	267	if (silicon_rev == aspeed_silicon_revs[i]) {
	268	return true;
	269	}
	270	}
	271
	272	return false;
	273	}
	274
	275	static void aspeed_scu_realize(DeviceState dev, Error *errp)
	276	{
	277	SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
	278	AspeedSCUState *s = ASPEED_SCU(dev);
	279
	280	if (!is_supported_silicon_rev(s->silicon_rev)) {
	281	error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,
	282	s->silicon_rev);
	283	return;
	284	}
	285
	286	memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_scu_ops, s,
	287	TYPE_ASPEED_SCU, SCU_IO_REGION_SIZE);
	288
	289	sysbus_init_mmio(sbd, &s->iomem);
	290	}
	291
	292	static const VMStateDescription vmstate_aspeed_scu = {
	293	.name = "aspeed.scu",
	294	.version_id = 1,
	295	.minimum_version_id = 1,
	296	.fields = (VMStateField[]) {
	297	VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_SCU_NR_REGS),
	298	VMSTATE_END_OF_LIST()
	299	}
	300	};
	301
	302	static Property aspeed_scu_properties[] = {
	303	DEFINE_PROP_UINT32("silicon-rev", AspeedSCUState, silicon_rev, 0),
	304	DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0),
2ddfa281	305	DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0),
b6e70d1d	306	DEFINE_PROP_UINT32("hw-prot-key", AspeedSCUState, hw_prot_key, 0),
1c8a2388 AJ	307	DEFINE_PROP_END_OF_LIST(),
	308	};
	309
	310	static void aspeed_scu_class_init(ObjectClass klass, void data)
	311	{
	312	DeviceClass *dc = DEVICE_CLASS(klass);
	313	dc->realize = aspeed_scu_realize;
	314	dc->reset = aspeed_scu_reset;
	315	dc->desc = "ASPEED System Control Unit";
	316	dc->vmsd = &vmstate_aspeed_scu;
	317	dc->props = aspeed_scu_properties;
	318	}
	319
	320	static const TypeInfo aspeed_scu_info = {
	321	.name = TYPE_ASPEED_SCU,
	322	.parent = TYPE_SYS_BUS_DEVICE,
	323	.instance_size = sizeof(AspeedSCUState),
	324	.class_init = aspeed_scu_class_init,
	325	};
	326
	327	static void aspeed_scu_register_types(void)
	328	{
	329	type_register_static(&aspeed_scu_info);
	330	}
	331
	332	type_init(aspeed_scu_register_types);