projects / qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| bf957284 PB |
1 | /* |
| 2 | * QEMU monitor | |
| 3 | * | |
| 4 | * Copyright (c) 2003-2004 Fabrice Bellard | |
| 5 | * | |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
| 7 | * of this software and associated documentation files (the "Software"), to deal | |
| 8 | * in the Software without restriction, including without limitation the rights | |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
| 10 | * copies of the Software, and to permit persons to whom the Software is | |
| 11 | * furnished to do so, subject to the following conditions: | |
| 12 | * | |
| 13 | * The above copyright notice and this permission notice shall be included in | |
| 14 | * all copies or substantial portions of the Software. | |
| 15 | * | |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
| 22 | * THE SOFTWARE. | |
| 23 | */ | |
| 24 | #include "cpu.h" | |
| 25 | #include "monitor/monitor.h" | |
| 26 | #include "monitor/hmp-target.h" | |
| 27 | #include "hmp.h" | |
| 28 | ||
| 29 | ||
| 30 | void hmp_info_tlb(Monitor *mon, const QDict *qdict) | |
| 31 | { | |
| 32 | CPUArchState *env1 = mon_get_cpu_env(); | |
| 33 | ||
| 34 | dump_mmu((FILE*)mon, (fprintf_function)monitor_printf, env1); | |
| 35 | } | |
| 36 | ||
| 37 | #ifndef TARGET_SPARC64 | |
| 38 | static target_long monitor_get_psr (const struct MonitorDef *md, int val) | |
| 39 | { | |
| 40 | CPUArchState *env = mon_get_cpu_env(); | |
| 41 | ||
| 42 | return cpu_get_psr(env); | |
| 43 | } | |
| 44 | #endif | |
| 45 | ||
| 46 | static target_long monitor_get_reg(const struct MonitorDef *md, int val) | |
| 47 | { | |
| 48 | CPUArchState *env = mon_get_cpu_env(); | |
| 49 | return env->regwptr[val]; | |
| 50 | } | |
| 51 | ||
| 52 | const MonitorDef monitor_defs[] = { | |
| 53 | { "g0", offsetof(CPUSPARCState, gregs[0]) }, | |
| 54 | { "g1", offsetof(CPUSPARCState, gregs[1]) }, | |
| 55 | { "g2", offsetof(CPUSPARCState, gregs[2]) }, | |
| 56 | { "g3", offsetof(CPUSPARCState, gregs[3]) }, | |
| 57 | { "g4", offsetof(CPUSPARCState, gregs[4]) }, | |
| 58 | { "g5", offsetof(CPUSPARCState, gregs[5]) }, | |
| 59 | { "g6", offsetof(CPUSPARCState, gregs[6]) }, | |
| 60 | { "g7", offsetof(CPUSPARCState, gregs[7]) }, | |
| 61 | { "o0", 0, monitor_get_reg }, | |
| 62 | { "o1", 1, monitor_get_reg }, | |
| 63 | { "o2", 2, monitor_get_reg }, | |
| 64 | { "o3", 3, monitor_get_reg }, | |
| 65 | { "o4", 4, monitor_get_reg }, | |
| 66 | { "o5", 5, monitor_get_reg }, | |
| 67 | { "o6", 6, monitor_get_reg }, | |
| 68 | { "o7", 7, monitor_get_reg }, | |
| 69 | { "l0", 8, monitor_get_reg }, | |
| 70 | { "l1", 9, monitor_get_reg }, | |
| 71 | { "l2", 10, monitor_get_reg }, | |
| 72 | { "l3", 11, monitor_get_reg }, | |
| 73 | { "l4", 12, monitor_get_reg }, | |
| 74 | { "l5", 13, monitor_get_reg }, | |
| 75 | { "l6", 14, monitor_get_reg }, | |
| 76 | { "l7", 15, monitor_get_reg }, | |
| 77 | { "i0", 16, monitor_get_reg }, | |
| 78 | { "i1", 17, monitor_get_reg }, | |
| 79 | { "i2", 18, monitor_get_reg }, | |
| 80 | { "i3", 19, monitor_get_reg }, | |
| 81 | { "i4", 20, monitor_get_reg }, | |
| 82 | { "i5", 21, monitor_get_reg }, | |
| 83 | { "i6", 22, monitor_get_reg }, | |
| 84 | { "i7", 23, monitor_get_reg }, | |
| 85 | { "pc", offsetof(CPUSPARCState, pc) }, | |
| 86 | { "npc", offsetof(CPUSPARCState, npc) }, | |
| 87 | { "y", offsetof(CPUSPARCState, y) }, | |
| 88 | #ifndef TARGET_SPARC64 | |
| 89 | { "psr", 0, &monitor_get_psr, }, | |
| 90 | { "wim", offsetof(CPUSPARCState, wim) }, | |
| 91 | #endif | |
| 92 | { "tbr", offsetof(CPUSPARCState, tbr) }, | |
| 93 | { "fsr", offsetof(CPUSPARCState, fsr) }, | |
| 94 | { "f0", offsetof(CPUSPARCState, fpr[0].l.upper) }, | |
| 95 | { "f1", offsetof(CPUSPARCState, fpr[0].l.lower) }, | |
| 96 | { "f2", offsetof(CPUSPARCState, fpr[1].l.upper) }, | |
| 97 | { "f3", offsetof(CPUSPARCState, fpr[1].l.lower) }, | |
| 98 | { "f4", offsetof(CPUSPARCState, fpr[2].l.upper) }, | |
| 99 | { "f5", offsetof(CPUSPARCState, fpr[2].l.lower) }, | |
| 100 | { "f6", offsetof(CPUSPARCState, fpr[3].l.upper) }, | |
| 101 | { "f7", offsetof(CPUSPARCState, fpr[3].l.lower) }, | |
| 102 | { "f8", offsetof(CPUSPARCState, fpr[4].l.upper) }, | |
| 103 | { "f9", offsetof(CPUSPARCState, fpr[4].l.lower) }, | |
| 104 | { "f10", offsetof(CPUSPARCState, fpr[5].l.upper) }, | |
| 105 | { "f11", offsetof(CPUSPARCState, fpr[5].l.lower) }, | |
| 106 | { "f12", offsetof(CPUSPARCState, fpr[6].l.upper) }, | |
| 107 | { "f13", offsetof(CPUSPARCState, fpr[6].l.lower) }, | |
| 108 | { "f14", offsetof(CPUSPARCState, fpr[7].l.upper) }, | |
| 109 | { "f15", offsetof(CPUSPARCState, fpr[7].l.lower) }, | |
| 110 | { "f16", offsetof(CPUSPARCState, fpr[8].l.upper) }, | |
| 111 | { "f17", offsetof(CPUSPARCState, fpr[8].l.lower) }, | |
| 112 | { "f18", offsetof(CPUSPARCState, fpr[9].l.upper) }, | |
| 113 | { "f19", offsetof(CPUSPARCState, fpr[9].l.lower) }, | |
| 114 | { "f20", offsetof(CPUSPARCState, fpr[10].l.upper) }, | |
| 115 | { "f21", offsetof(CPUSPARCState, fpr[10].l.lower) }, | |
| 116 | { "f22", offsetof(CPUSPARCState, fpr[11].l.upper) }, | |
| 117 | { "f23", offsetof(CPUSPARCState, fpr[11].l.lower) }, | |
| 118 | { "f24", offsetof(CPUSPARCState, fpr[12].l.upper) }, | |
| 119 | { "f25", offsetof(CPUSPARCState, fpr[12].l.lower) }, | |
| 120 | { "f26", offsetof(CPUSPARCState, fpr[13].l.upper) }, | |
| 121 | { "f27", offsetof(CPUSPARCState, fpr[13].l.lower) }, | |
| 122 | { "f28", offsetof(CPUSPARCState, fpr[14].l.upper) }, | |
| 123 | { "f29", offsetof(CPUSPARCState, fpr[14].l.lower) }, | |
| 124 | { "f30", offsetof(CPUSPARCState, fpr[15].l.upper) }, | |
| 125 | { "f31", offsetof(CPUSPARCState, fpr[15].l.lower) }, | |
| 126 | #ifdef TARGET_SPARC64 | |
| 127 | { "f32", offsetof(CPUSPARCState, fpr[16]) }, | |
| 128 | { "f34", offsetof(CPUSPARCState, fpr[17]) }, | |
| 129 | { "f36", offsetof(CPUSPARCState, fpr[18]) }, | |
| 130 | { "f38", offsetof(CPUSPARCState, fpr[19]) }, | |
| 131 | { "f40", offsetof(CPUSPARCState, fpr[20]) }, | |
| 132 | { "f42", offsetof(CPUSPARCState, fpr[21]) }, | |
| 133 | { "f44", offsetof(CPUSPARCState, fpr[22]) }, | |
| 134 | { "f46", offsetof(CPUSPARCState, fpr[23]) }, | |
| 135 | { "f48", offsetof(CPUSPARCState, fpr[24]) }, | |
| 136 | { "f50", offsetof(CPUSPARCState, fpr[25]) }, | |
| 137 | { "f52", offsetof(CPUSPARCState, fpr[26]) }, | |
| 138 | { "f54", offsetof(CPUSPARCState, fpr[27]) }, | |
| 139 | { "f56", offsetof(CPUSPARCState, fpr[28]) }, | |
| 140 | { "f58", offsetof(CPUSPARCState, fpr[29]) }, | |
| 141 | { "f60", offsetof(CPUSPARCState, fpr[30]) }, | |
| 142 | { "f62", offsetof(CPUSPARCState, fpr[31]) }, | |
| 143 | { "asi", offsetof(CPUSPARCState, asi) }, | |
| 144 | { "pstate", offsetof(CPUSPARCState, pstate) }, | |
| 145 | { "cansave", offsetof(CPUSPARCState, cansave) }, | |
| 146 | { "canrestore", offsetof(CPUSPARCState, canrestore) }, | |
| 147 | { "otherwin", offsetof(CPUSPARCState, otherwin) }, | |
| 148 | { "wstate", offsetof(CPUSPARCState, wstate) }, | |
| 149 | { "cleanwin", offsetof(CPUSPARCState, cleanwin) }, | |
| 150 | { "fprs", offsetof(CPUSPARCState, fprs) }, | |
| 151 | #endif | |
| 152 | { NULL }, | |
| 153 | }; | |
| 154 | ||
| 155 | const MonitorDef *target_monitor_defs(void) | |
| 156 | { | |
| 157 | return monitor_defs; | |
| 158 | } |