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Commit | Line | Data |
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244ab90e AL |
1 | /* |
2 | * DMA helper functions | |
3 | * | |
4 | * Copyright (c) 2009 Red Hat | |
5 | * | |
6 | * This work is licensed under the terms of the GNU General Public License | |
7 | * (GNU GPL), version 2 or later. | |
8 | */ | |
9 | ||
9c17d615 | 10 | #include "sysemu/dma.h" |
c57c4658 | 11 | #include "trace.h" |
1de7afc9 PB |
12 | #include "qemu/range.h" |
13 | #include "qemu/thread.h" | |
244ab90e | 14 | |
e5332e63 DG |
15 | /* #define DEBUG_IOMMU */ |
16 | ||
df32fd1c | 17 | int dma_memory_set(AddressSpace *as, dma_addr_t addr, uint8_t c, dma_addr_t len) |
d86a77f8 | 18 | { |
df32fd1c | 19 | dma_barrier(as, DMA_DIRECTION_FROM_DEVICE); |
24addbc7 | 20 | |
d86a77f8 DG |
21 | #define FILLBUF_SIZE 512 |
22 | uint8_t fillbuf[FILLBUF_SIZE]; | |
23 | int l; | |
24addbc7 | 24 | bool error = false; |
d86a77f8 DG |
25 | |
26 | memset(fillbuf, c, FILLBUF_SIZE); | |
27 | while (len > 0) { | |
28 | l = len < FILLBUF_SIZE ? len : FILLBUF_SIZE; | |
24addbc7 | 29 | error |= address_space_rw(as, addr, fillbuf, l, true); |
bc9b78de BH |
30 | len -= l; |
31 | addr += l; | |
d86a77f8 | 32 | } |
e5332e63 | 33 | |
24addbc7 | 34 | return error; |
d86a77f8 DG |
35 | } |
36 | ||
df32fd1c | 37 | void qemu_sglist_init(QEMUSGList *qsg, int alloc_hint, AddressSpace *as) |
244ab90e | 38 | { |
7267c094 | 39 | qsg->sg = g_malloc(alloc_hint * sizeof(ScatterGatherEntry)); |
244ab90e AL |
40 | qsg->nsg = 0; |
41 | qsg->nalloc = alloc_hint; | |
42 | qsg->size = 0; | |
df32fd1c | 43 | qsg->as = as; |
244ab90e AL |
44 | } |
45 | ||
d3231181 | 46 | void qemu_sglist_add(QEMUSGList *qsg, dma_addr_t base, dma_addr_t len) |
244ab90e AL |
47 | { |
48 | if (qsg->nsg == qsg->nalloc) { | |
49 | qsg->nalloc = 2 * qsg->nalloc + 1; | |
7267c094 | 50 | qsg->sg = g_realloc(qsg->sg, qsg->nalloc * sizeof(ScatterGatherEntry)); |
244ab90e AL |
51 | } |
52 | qsg->sg[qsg->nsg].base = base; | |
53 | qsg->sg[qsg->nsg].len = len; | |
54 | qsg->size += len; | |
55 | ++qsg->nsg; | |
56 | } | |
57 | ||
58 | void qemu_sglist_destroy(QEMUSGList *qsg) | |
59 | { | |
7267c094 | 60 | g_free(qsg->sg); |
ea8d82a1 | 61 | memset(qsg, 0, sizeof(*qsg)); |
244ab90e AL |
62 | } |
63 | ||
59a703eb | 64 | typedef struct { |
37b7842c | 65 | BlockDriverAIOCB common; |
59a703eb AL |
66 | BlockDriverState *bs; |
67 | BlockDriverAIOCB *acb; | |
68 | QEMUSGList *sg; | |
69 | uint64_t sector_num; | |
43cf8ae6 | 70 | DMADirection dir; |
c3adb5b9 | 71 | bool in_cancel; |
59a703eb | 72 | int sg_cur_index; |
d3231181 | 73 | dma_addr_t sg_cur_byte; |
59a703eb AL |
74 | QEMUIOVector iov; |
75 | QEMUBH *bh; | |
cb144ccb | 76 | DMAIOFunc *io_func; |
37b7842c | 77 | } DMAAIOCB; |
59a703eb AL |
78 | |
79 | static void dma_bdrv_cb(void *opaque, int ret); | |
80 | ||
81 | static void reschedule_dma(void *opaque) | |
82 | { | |
37b7842c | 83 | DMAAIOCB *dbs = (DMAAIOCB *)opaque; |
59a703eb AL |
84 | |
85 | qemu_bh_delete(dbs->bh); | |
86 | dbs->bh = NULL; | |
c3adb5b9 | 87 | dma_bdrv_cb(dbs, 0); |
59a703eb AL |
88 | } |
89 | ||
90 | static void continue_after_map_failure(void *opaque) | |
91 | { | |
37b7842c | 92 | DMAAIOCB *dbs = (DMAAIOCB *)opaque; |
59a703eb AL |
93 | |
94 | dbs->bh = qemu_bh_new(reschedule_dma, dbs); | |
95 | qemu_bh_schedule(dbs->bh); | |
96 | } | |
97 | ||
7403b14e | 98 | static void dma_bdrv_unmap(DMAAIOCB *dbs) |
59a703eb | 99 | { |
59a703eb AL |
100 | int i; |
101 | ||
59a703eb | 102 | for (i = 0; i < dbs->iov.niov; ++i) { |
df32fd1c | 103 | dma_memory_unmap(dbs->sg->as, dbs->iov.iov[i].iov_base, |
c65bcef3 DG |
104 | dbs->iov.iov[i].iov_len, dbs->dir, |
105 | dbs->iov.iov[i].iov_len); | |
59a703eb | 106 | } |
c3adb5b9 PB |
107 | qemu_iovec_reset(&dbs->iov); |
108 | } | |
109 | ||
110 | static void dma_complete(DMAAIOCB *dbs, int ret) | |
111 | { | |
c57c4658 KW |
112 | trace_dma_complete(dbs, ret, dbs->common.cb); |
113 | ||
c3adb5b9 PB |
114 | dma_bdrv_unmap(dbs); |
115 | if (dbs->common.cb) { | |
116 | dbs->common.cb(dbs->common.opaque, ret); | |
117 | } | |
118 | qemu_iovec_destroy(&dbs->iov); | |
119 | if (dbs->bh) { | |
120 | qemu_bh_delete(dbs->bh); | |
121 | dbs->bh = NULL; | |
122 | } | |
123 | if (!dbs->in_cancel) { | |
124 | /* Requests may complete while dma_aio_cancel is in progress. In | |
125 | * this case, the AIOCB should not be released because it is still | |
126 | * referenced by dma_aio_cancel. */ | |
127 | qemu_aio_release(dbs); | |
128 | } | |
7403b14e AL |
129 | } |
130 | ||
856ae5c3 | 131 | static void dma_bdrv_cb(void *opaque, int ret) |
7403b14e AL |
132 | { |
133 | DMAAIOCB *dbs = (DMAAIOCB *)opaque; | |
c65bcef3 | 134 | dma_addr_t cur_addr, cur_len; |
7403b14e AL |
135 | void *mem; |
136 | ||
c57c4658 KW |
137 | trace_dma_bdrv_cb(dbs, ret); |
138 | ||
7403b14e AL |
139 | dbs->acb = NULL; |
140 | dbs->sector_num += dbs->iov.size / 512; | |
141 | dma_bdrv_unmap(dbs); | |
59a703eb AL |
142 | |
143 | if (dbs->sg_cur_index == dbs->sg->nsg || ret < 0) { | |
c3adb5b9 | 144 | dma_complete(dbs, ret); |
59a703eb AL |
145 | return; |
146 | } | |
147 | ||
148 | while (dbs->sg_cur_index < dbs->sg->nsg) { | |
149 | cur_addr = dbs->sg->sg[dbs->sg_cur_index].base + dbs->sg_cur_byte; | |
150 | cur_len = dbs->sg->sg[dbs->sg_cur_index].len - dbs->sg_cur_byte; | |
df32fd1c | 151 | mem = dma_memory_map(dbs->sg->as, cur_addr, &cur_len, dbs->dir); |
59a703eb AL |
152 | if (!mem) |
153 | break; | |
154 | qemu_iovec_add(&dbs->iov, mem, cur_len); | |
155 | dbs->sg_cur_byte += cur_len; | |
156 | if (dbs->sg_cur_byte == dbs->sg->sg[dbs->sg_cur_index].len) { | |
157 | dbs->sg_cur_byte = 0; | |
158 | ++dbs->sg_cur_index; | |
159 | } | |
160 | } | |
161 | ||
162 | if (dbs->iov.size == 0) { | |
c57c4658 | 163 | trace_dma_map_wait(dbs); |
59a703eb AL |
164 | cpu_register_map_client(dbs, continue_after_map_failure); |
165 | return; | |
166 | } | |
167 | ||
cb144ccb CH |
168 | dbs->acb = dbs->io_func(dbs->bs, dbs->sector_num, &dbs->iov, |
169 | dbs->iov.size / 512, dma_bdrv_cb, dbs); | |
6bee44ea | 170 | assert(dbs->acb); |
59a703eb AL |
171 | } |
172 | ||
c16b5a2c CH |
173 | static void dma_aio_cancel(BlockDriverAIOCB *acb) |
174 | { | |
175 | DMAAIOCB *dbs = container_of(acb, DMAAIOCB, common); | |
176 | ||
c57c4658 KW |
177 | trace_dma_aio_cancel(dbs); |
178 | ||
c16b5a2c | 179 | if (dbs->acb) { |
c3adb5b9 PB |
180 | BlockDriverAIOCB *acb = dbs->acb; |
181 | dbs->acb = NULL; | |
182 | dbs->in_cancel = true; | |
183 | bdrv_aio_cancel(acb); | |
184 | dbs->in_cancel = false; | |
c16b5a2c | 185 | } |
c3adb5b9 PB |
186 | dbs->common.cb = NULL; |
187 | dma_complete(dbs, 0); | |
c16b5a2c CH |
188 | } |
189 | ||
d7331bed | 190 | static const AIOCBInfo dma_aiocb_info = { |
c16b5a2c CH |
191 | .aiocb_size = sizeof(DMAAIOCB), |
192 | .cancel = dma_aio_cancel, | |
193 | }; | |
194 | ||
cb144ccb | 195 | BlockDriverAIOCB *dma_bdrv_io( |
59a703eb | 196 | BlockDriverState *bs, QEMUSGList *sg, uint64_t sector_num, |
cb144ccb | 197 | DMAIOFunc *io_func, BlockDriverCompletionFunc *cb, |
43cf8ae6 | 198 | void *opaque, DMADirection dir) |
59a703eb | 199 | { |
d7331bed | 200 | DMAAIOCB *dbs = qemu_aio_get(&dma_aiocb_info, bs, cb, opaque); |
59a703eb | 201 | |
43cf8ae6 | 202 | trace_dma_bdrv_io(dbs, bs, sector_num, (dir == DMA_DIRECTION_TO_DEVICE)); |
c57c4658 | 203 | |
37b7842c | 204 | dbs->acb = NULL; |
59a703eb | 205 | dbs->bs = bs; |
59a703eb AL |
206 | dbs->sg = sg; |
207 | dbs->sector_num = sector_num; | |
208 | dbs->sg_cur_index = 0; | |
209 | dbs->sg_cur_byte = 0; | |
43cf8ae6 | 210 | dbs->dir = dir; |
cb144ccb | 211 | dbs->io_func = io_func; |
59a703eb AL |
212 | dbs->bh = NULL; |
213 | qemu_iovec_init(&dbs->iov, sg->nsg); | |
214 | dma_bdrv_cb(dbs, 0); | |
37b7842c | 215 | return &dbs->common; |
59a703eb AL |
216 | } |
217 | ||
218 | ||
219 | BlockDriverAIOCB *dma_bdrv_read(BlockDriverState *bs, | |
220 | QEMUSGList *sg, uint64_t sector, | |
221 | void (*cb)(void *opaque, int ret), void *opaque) | |
222 | { | |
43cf8ae6 DG |
223 | return dma_bdrv_io(bs, sg, sector, bdrv_aio_readv, cb, opaque, |
224 | DMA_DIRECTION_FROM_DEVICE); | |
59a703eb AL |
225 | } |
226 | ||
227 | BlockDriverAIOCB *dma_bdrv_write(BlockDriverState *bs, | |
228 | QEMUSGList *sg, uint64_t sector, | |
229 | void (*cb)(void *opaque, int ret), void *opaque) | |
230 | { | |
43cf8ae6 DG |
231 | return dma_bdrv_io(bs, sg, sector, bdrv_aio_writev, cb, opaque, |
232 | DMA_DIRECTION_TO_DEVICE); | |
59a703eb | 233 | } |
8171ee35 PB |
234 | |
235 | ||
c65bcef3 DG |
236 | static uint64_t dma_buf_rw(uint8_t *ptr, int32_t len, QEMUSGList *sg, |
237 | DMADirection dir) | |
8171ee35 PB |
238 | { |
239 | uint64_t resid; | |
240 | int sg_cur_index; | |
241 | ||
242 | resid = sg->size; | |
243 | sg_cur_index = 0; | |
244 | len = MIN(len, resid); | |
245 | while (len > 0) { | |
246 | ScatterGatherEntry entry = sg->sg[sg_cur_index++]; | |
247 | int32_t xfer = MIN(len, entry.len); | |
df32fd1c | 248 | dma_memory_rw(sg->as, entry.base, ptr, xfer, dir); |
8171ee35 PB |
249 | ptr += xfer; |
250 | len -= xfer; | |
251 | resid -= xfer; | |
252 | } | |
253 | ||
254 | return resid; | |
255 | } | |
256 | ||
257 | uint64_t dma_buf_read(uint8_t *ptr, int32_t len, QEMUSGList *sg) | |
258 | { | |
c65bcef3 | 259 | return dma_buf_rw(ptr, len, sg, DMA_DIRECTION_FROM_DEVICE); |
8171ee35 PB |
260 | } |
261 | ||
262 | uint64_t dma_buf_write(uint8_t *ptr, int32_t len, QEMUSGList *sg) | |
263 | { | |
c65bcef3 | 264 | return dma_buf_rw(ptr, len, sg, DMA_DIRECTION_TO_DEVICE); |
8171ee35 | 265 | } |
84a69356 PB |
266 | |
267 | void dma_acct_start(BlockDriverState *bs, BlockAcctCookie *cookie, | |
268 | QEMUSGList *sg, enum BlockAcctType type) | |
269 | { | |
270 | bdrv_acct_start(bs, cookie, sg->size, type); | |
271 | } |