[qemu.git] / target / xtensa / xtensa-semi.c

/*
 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of the Open Source and Linux Lab nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "chardev/char-fe.h"
#include "exec/helper-proto.h"
#include "exec/semihost.h"
#include "qapi/error.h"
#include "qemu/log.h"
#include "sysemu/sysemu.h"

enum {
    TARGET_SYS_exit = 1,
    TARGET_SYS_read = 3,
    TARGET_SYS_write = 4,
    TARGET_SYS_open = 5,
    TARGET_SYS_close = 6,
    TARGET_SYS_lseek = 19,
    TARGET_SYS_select_one = 29,

    TARGET_SYS_argc = 1000,
    TARGET_SYS_argv_sz = 1001,
    TARGET_SYS_argv = 1002,
    TARGET_SYS_memset = 1004,
};

enum {
    SELECT_ONE_READ   = 1,
    SELECT_ONE_WRITE  = 2,
    SELECT_ONE_EXCEPT = 3,
};

enum {
    TARGET_EPERM        =  1,
    TARGET_ENOENT       =  2,
    TARGET_ESRCH        =  3,
    TARGET_EINTR        =  4,
    TARGET_EIO          =  5,
    TARGET_ENXIO        =  6,
    TARGET_E2BIG        =  7,
    TARGET_ENOEXEC      =  8,
    TARGET_EBADF        =  9,
    TARGET_ECHILD       = 10,
    TARGET_EAGAIN       = 11,
    TARGET_ENOMEM       = 12,
    TARGET_EACCES       = 13,
    TARGET_EFAULT       = 14,
    TARGET_ENOTBLK      = 15,
    TARGET_EBUSY        = 16,
    TARGET_EEXIST       = 17,
    TARGET_EXDEV        = 18,
    TARGET_ENODEV       = 19,
    TARGET_ENOTDIR      = 20,
    TARGET_EISDIR       = 21,
    TARGET_EINVAL       = 22,
    TARGET_ENFILE       = 23,
    TARGET_EMFILE       = 24,
    TARGET_ENOTTY       = 25,
    TARGET_ETXTBSY      = 26,
    TARGET_EFBIG        = 27,
    TARGET_ENOSPC       = 28,
    TARGET_ESPIPE       = 29,
    TARGET_EROFS        = 30,
    TARGET_EMLINK       = 31,
    TARGET_EPIPE        = 32,
    TARGET_EDOM         = 33,
    TARGET_ERANGE       = 34,
    TARGET_ENOSYS       = 88,
    TARGET_ELOOP        = 92,
};

static uint32_t errno_h2g(int host_errno)
{
    static const uint32_t guest_errno[] = {
        [EPERM]         = TARGET_EPERM,
        [ENOENT]        = TARGET_ENOENT,
        [ESRCH]         = TARGET_ESRCH,
        [EINTR]         = TARGET_EINTR,
        [EIO]           = TARGET_EIO,
        [ENXIO]         = TARGET_ENXIO,
        [E2BIG]         = TARGET_E2BIG,
        [ENOEXEC]       = TARGET_ENOEXEC,
        [EBADF]         = TARGET_EBADF,
        [ECHILD]        = TARGET_ECHILD,
        [EAGAIN]        = TARGET_EAGAIN,
        [ENOMEM]        = TARGET_ENOMEM,
        [EACCES]        = TARGET_EACCES,
        [EFAULT]        = TARGET_EFAULT,
#ifdef ENOTBLK
        [ENOTBLK]       = TARGET_ENOTBLK,
#endif
        [EBUSY]         = TARGET_EBUSY,
        [EEXIST]        = TARGET_EEXIST,
        [EXDEV]         = TARGET_EXDEV,
        [ENODEV]        = TARGET_ENODEV,
        [ENOTDIR]       = TARGET_ENOTDIR,
        [EISDIR]        = TARGET_EISDIR,
        [EINVAL]        = TARGET_EINVAL,
        [ENFILE]        = TARGET_ENFILE,
        [EMFILE]        = TARGET_EMFILE,
        [ENOTTY]        = TARGET_ENOTTY,
#ifdef ETXTBSY
        [ETXTBSY]       = TARGET_ETXTBSY,
#endif
        [EFBIG]         = TARGET_EFBIG,
        [ENOSPC]        = TARGET_ENOSPC,
        [ESPIPE]        = TARGET_ESPIPE,
        [EROFS]         = TARGET_EROFS,
        [EMLINK]        = TARGET_EMLINK,
        [EPIPE]         = TARGET_EPIPE,
        [EDOM]          = TARGET_EDOM,
        [ERANGE]        = TARGET_ERANGE,
        [ENOSYS]        = TARGET_ENOSYS,
#ifdef ELOOP
        [ELOOP]         = TARGET_ELOOP,
#endif
    };

    if (host_errno == 0) {
        return 0;
    } else if (host_errno > 0 && host_errno < ARRAY_SIZE(guest_errno) &&
            guest_errno[host_errno]) {
        return guest_errno[host_errno];
    } else {
        return TARGET_EINVAL;
    }
}

typedef struct XtensaSimConsole {
    CharBackend be;
    struct {
        char buffer[16];
        size_t offset;
    } input;
} XtensaSimConsole;

static XtensaSimConsole *sim_console;

static IOCanReadHandler sim_console_can_read;
static int sim_console_can_read(void *opaque)
{
    XtensaSimConsole *p = opaque;

    return sizeof(p->input.buffer) - p->input.offset;
}

static IOReadHandler sim_console_read;
static void sim_console_read(void *opaque, const uint8_t *buf, int size)
{
    XtensaSimConsole *p = opaque;
    size_t copy = sizeof(p->input.buffer) - p->input.offset;

    if (size < copy) {
        copy = size;
    }
    memcpy(p->input.buffer + p->input.offset, buf, copy);
    p->input.offset += copy;
}

void xtensa_sim_open_console(Chardev *chr)
{
    static XtensaSimConsole console;

    qemu_chr_fe_init(&console.be, chr, &error_abort);
    qemu_chr_fe_set_handlers(&console.be,
                             sim_console_can_read,
                             sim_console_read,
                             NULL, NULL, &console,
                             NULL, true);
    sim_console = &console;
}

void HELPER(simcall)(CPUXtensaState *env)
{
    CPUState *cs = CPU(xtensa_env_get_cpu(env));
    uint32_t *regs = env->regs;

    switch (regs[2]) {
    case TARGET_SYS_exit:
        qemu_log("exit(%d) simcall\n", regs[3]);
        exit(regs[3]);
        break;

    case TARGET_SYS_read:
    case TARGET_SYS_write:
        {
            bool is_write = regs[2] == TARGET_SYS_write;
            uint32_t fd = regs[3];
            uint32_t vaddr = regs[4];
            uint32_t len = regs[5];
            uint32_t len_done = 0;

            while (len > 0) {
                hwaddr paddr = cpu_get_phys_page_debug(cs, vaddr);
                uint32_t page_left =
                    TARGET_PAGE_SIZE - (vaddr & (TARGET_PAGE_SIZE - 1));
                uint32_t io_sz = page_left < len ? page_left : len;
                hwaddr sz = io_sz;
                void *buf = cpu_physical_memory_map(paddr, &sz, !is_write);
                uint32_t io_done;
                bool error = false;

                if (buf) {
                    vaddr += io_sz;
                    len -= io_sz;
                    if (fd < 3 && sim_console) {
                        if (is_write && (fd == 1 || fd == 2)) {
                            io_done = qemu_chr_fe_write_all(&sim_console->be,
                                                            buf, io_sz);
                            regs[3] = errno_h2g(errno);
                        } else if (!is_write && fd == 0) {
                            if (sim_console->input.offset) {
                                io_done = sim_console->input.offset;
                                if (io_sz < io_done) {
                                    io_done = io_sz;
                                }
                                memcpy(buf, sim_console->input.buffer, io_done);
                                memmove(sim_console->input.buffer,
                                        sim_console->input.buffer + io_done,
                                        sim_console->input.offset - io_done);
                                sim_console->input.offset -= io_done;
                                qemu_chr_fe_accept_input(&sim_console->be);
                            } else {
                                io_done = -1;
                                regs[3] = TARGET_EAGAIN;
                            }
                        } else {
                            qemu_log_mask(LOG_GUEST_ERROR,
                                          "%s fd %d is not supported with chardev console\n",
                                          is_write ?
                                          "writing to" : "reading from", fd);
                            io_done = -1;
                            regs[3] = TARGET_EBADF;
                        }
                    } else {
                        io_done = is_write ?
                            write(fd, buf, io_sz) :
                            read(fd, buf, io_sz);
                        regs[3] = errno_h2g(errno);
                    }
                    if (io_done == -1) {
                        error = true;
                        io_done = 0;
                    }
                    cpu_physical_memory_unmap(buf, sz, !is_write, io_done);
                } else {
                    error = true;
                    regs[3] = TARGET_EINVAL;
                    break;
                }
                if (error) {
                    if (!len_done) {
                        len_done = -1;
                    }
                    break;
                }
                len_done += io_done;
                if (io_done < io_sz) {
                    break;
                }
            }
            regs[2] = len_done;
        }
        break;

    case TARGET_SYS_open:
        {
            char name[1024];
            int rc;
            int i;

            for (i = 0; i < ARRAY_SIZE(name); ++i) {
                rc = cpu_memory_rw_debug(cs, regs[3] + i,
                                         (uint8_t *)name + i, 1, 0);
                if (rc != 0 || name[i] == 0) {
                    break;
                }
            }

            if (rc == 0 && i < ARRAY_SIZE(name)) {
                regs[2] = open(name, regs[4], regs[5]);
                regs[3] = errno_h2g(errno);
            } else {
                regs[2] = -1;
                regs[3] = TARGET_EINVAL;
            }
        }
        break;

    case TARGET_SYS_close:
        if (regs[3] < 3) {
            regs[2] = regs[3] = 0;
        } else {
            regs[2] = close(regs[3]);
            regs[3] = errno_h2g(errno);
        }
        break;

    case TARGET_SYS_lseek:
        regs[2] = lseek(regs[3], (off_t)(int32_t)regs[4], regs[5]);
        regs[3] = errno_h2g(errno);
        break;

    case TARGET_SYS_select_one:
        {
            uint32_t fd = regs[3];
            uint32_t rq = regs[4];
            uint32_t target_tv = regs[5];
            uint32_t target_tvv[2];

            struct timeval tv = {0};

            if (target_tv) {
                cpu_memory_rw_debug(cs, target_tv,
                        (uint8_t *)target_tvv, sizeof(target_tvv), 0);
                tv.tv_sec = (int32_t)tswap32(target_tvv[0]);
                tv.tv_usec = (int32_t)tswap32(target_tvv[1]);
            }
            if (fd < 3 && sim_console) {
                if ((fd == 1 || fd == 2) && rq == SELECT_ONE_WRITE) {
                    regs[2] = 1;
                } else if (fd == 0 && rq == SELECT_ONE_READ) {
                    regs[2] = sim_console->input.offset > 0;
                } else {
                    regs[2] = 0;
                }
                regs[3] = 0;
            } else {
                fd_set fdset;

                FD_ZERO(&fdset);
                FD_SET(fd, &fdset);
                regs[2] = select(fd + 1,
                                 rq == SELECT_ONE_READ   ? &fdset : NULL,
                                 rq == SELECT_ONE_WRITE  ? &fdset : NULL,
                                 rq == SELECT_ONE_EXCEPT ? &fdset : NULL,
                                 target_tv ? &tv : NULL);
                regs[3] = errno_h2g(errno);
            }
        }
        break;

    case TARGET_SYS_argc:
        regs[2] = semihosting_get_argc();
        regs[3] = 0;
        break;

    case TARGET_SYS_argv_sz:
        {
            int argc = semihosting_get_argc();
            int sz = (argc + 1) * sizeof(uint32_t);
            int i;

            for (i = 0; i < argc; ++i) {
                sz += 1 + strlen(semihosting_get_arg(i));
            }
            regs[2] = sz;
            regs[3] = 0;
        }
        break;

    case TARGET_SYS_argv:
        {
            int argc = semihosting_get_argc();
            int str_offset = (argc + 1) * sizeof(uint32_t);
            int i;
            uint32_t argptr;

            for (i = 0; i < argc; ++i) {
                const char *str = semihosting_get_arg(i);
                int str_size = strlen(str) + 1;

                argptr = tswap32(regs[3] + str_offset);

                cpu_memory_rw_debug(cs,
                                    regs[3] + i * sizeof(uint32_t),
                                    (uint8_t *)&argptr, sizeof(argptr), 1);
                cpu_memory_rw_debug(cs,
                                    regs[3] + str_offset,
                                    (uint8_t *)str, str_size, 1);
                str_offset += str_size;
            }
            argptr = 0;
            cpu_memory_rw_debug(cs,
                                regs[3] + i * sizeof(uint32_t),
                                (uint8_t *)&argptr, sizeof(argptr), 1);
            regs[3] = 0;
        }
        break;

    case TARGET_SYS_memset:
        {
            uint32_t base = regs[3];
            uint32_t sz = regs[5];

            while (sz) {
                hwaddr len = sz;
                void *buf = cpu_physical_memory_map(base, &len, 1);

                if (buf && len) {
                    memset(buf, regs[4], len);
                    cpu_physical_memory_unmap(buf, len, 1, len);
                } else {
                    len = 1;
                }
                base += len;
                sz -= len;
            }
            regs[2] = regs[3];
            regs[3] = 0;
        }
        break;

    default:
        qemu_log_mask(LOG_GUEST_ERROR, "%s(%d): not implemented\n", __func__, regs[2]);
        regs[2] = -1;
        regs[3] = TARGET_ENOSYS;
        break;
    }
}
Commit	Line	Data
1ddeaa5d MF	1	/*
	2	* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
	3	* All rights reserved.
	4	*
	5	* Redistribution and use in source and binary forms, with or without
	6	* modification, are permitted provided that the following conditions are met:
	7	* * Redistributions of source code must retain the above copyright
	8	* notice, this list of conditions and the following disclaimer.
	9	* * Redistributions in binary form must reproduce the above copyright
	10	* notice, this list of conditions and the following disclaimer in the
	11	* documentation and/or other materials provided with the distribution.
	12	* * Neither the name of the Open Source and Linux Lab nor the
	13	* names of its contributors may be used to endorse or promote products
	14	* derived from this software without specific prior written permission.
	15	*
	16	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	17	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	18	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	19	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
	20	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	21	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	22	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	23	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	24	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	25	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	26	*/
	27
09aae23d	28	#include "qemu/osdep.h"
1ddeaa5d	29	#include "cpu.h"
8128b3e0	30	#include "chardev/char-fe.h"
2ef6175a	31	#include "exec/helper-proto.h"
f289bb09	32	#include "exec/semihost.h"
8128b3e0	33	#include "qapi/error.h"
1de7afc9	34	#include "qemu/log.h"
8128b3e0 MF	35	#include "sysemu/sysemu.h"
8128b3e0 MF	36
1ddeaa5d MF	37	enum {
	38	TARGET_SYS_exit = 1,
	39	TARGET_SYS_read = 3,
	40	TARGET_SYS_write = 4,
	41	TARGET_SYS_open = 5,
	42	TARGET_SYS_close = 6,
	43	TARGET_SYS_lseek = 19,
	44	TARGET_SYS_select_one = 29,
	45
	46	TARGET_SYS_argc = 1000,
	47	TARGET_SYS_argv_sz = 1001,
	48	TARGET_SYS_argv = 1002,
	49	TARGET_SYS_memset = 1004,
	50	};
	51
	52	enum {
	53	SELECT_ONE_READ = 1,
	54	SELECT_ONE_WRITE = 2,
	55	SELECT_ONE_EXCEPT = 3,
	56	};
	57
d6ce52c1 MF	58	enum {
	59	TARGET_EPERM = 1,
	60	TARGET_ENOENT = 2,
	61	TARGET_ESRCH = 3,
	62	TARGET_EINTR = 4,
	63	TARGET_EIO = 5,
	64	TARGET_ENXIO = 6,
	65	TARGET_E2BIG = 7,
	66	TARGET_ENOEXEC = 8,
	67	TARGET_EBADF = 9,
	68	TARGET_ECHILD = 10,
	69	TARGET_EAGAIN = 11,
	70	TARGET_ENOMEM = 12,
	71	TARGET_EACCES = 13,
	72	TARGET_EFAULT = 14,
	73	TARGET_ENOTBLK = 15,
	74	TARGET_EBUSY = 16,
	75	TARGET_EEXIST = 17,
	76	TARGET_EXDEV = 18,
	77	TARGET_ENODEV = 19,
	78	TARGET_ENOTDIR = 20,
	79	TARGET_EISDIR = 21,
	80	TARGET_EINVAL = 22,
	81	TARGET_ENFILE = 23,
	82	TARGET_EMFILE = 24,
	83	TARGET_ENOTTY = 25,
	84	TARGET_ETXTBSY = 26,
	85	TARGET_EFBIG = 27,
	86	TARGET_ENOSPC = 28,
	87	TARGET_ESPIPE = 29,
	88	TARGET_EROFS = 30,
	89	TARGET_EMLINK = 31,
	90	TARGET_EPIPE = 32,
	91	TARGET_EDOM = 33,
	92	TARGET_ERANGE = 34,
	93	TARGET_ENOSYS = 88,
	94	TARGET_ELOOP = 92,
	95	};
	96
	97	static uint32_t errno_h2g(int host_errno)
	98	{
	99	static const uint32_t guest_errno[] = {
	100	[EPERM] = TARGET_EPERM,
	101	[ENOENT] = TARGET_ENOENT,
	102	[ESRCH] = TARGET_ESRCH,
	103	[EINTR] = TARGET_EINTR,
	104	[EIO] = TARGET_EIO,
	105	[ENXIO] = TARGET_ENXIO,
	106	[E2BIG] = TARGET_E2BIG,
	107	[ENOEXEC] = TARGET_ENOEXEC,
	108	[EBADF] = TARGET_EBADF,
	109	[ECHILD] = TARGET_ECHILD,
	110	[EAGAIN] = TARGET_EAGAIN,
	111	[ENOMEM] = TARGET_ENOMEM,
	112	[EACCES] = TARGET_EACCES,
	113	[EFAULT] = TARGET_EFAULT,
c29b1bee	114	#ifdef ENOTBLK
d6ce52c1	115	[ENOTBLK] = TARGET_ENOTBLK,
c29b1bee	116	#endif
d6ce52c1 MF	117	[EBUSY] = TARGET_EBUSY,
	118	[EEXIST] = TARGET_EEXIST,
	119	[EXDEV] = TARGET_EXDEV,
	120	[ENODEV] = TARGET_ENODEV,
	121	[ENOTDIR] = TARGET_ENOTDIR,
	122	[EISDIR] = TARGET_EISDIR,
	123	[EINVAL] = TARGET_EINVAL,
	124	[ENFILE] = TARGET_ENFILE,
	125	[EMFILE] = TARGET_EMFILE,
	126	[ENOTTY] = TARGET_ENOTTY,
c29b1bee	127	#ifdef ETXTBSY
d6ce52c1	128	[ETXTBSY] = TARGET_ETXTBSY,
c29b1bee	129	#endif
d6ce52c1 MF	130	[EFBIG] = TARGET_EFBIG,
	131	[ENOSPC] = TARGET_ENOSPC,
	132	[ESPIPE] = TARGET_ESPIPE,
	133	[EROFS] = TARGET_EROFS,
	134	[EMLINK] = TARGET_EMLINK,
	135	[EPIPE] = TARGET_EPIPE,
	136	[EDOM] = TARGET_EDOM,
	137	[ERANGE] = TARGET_ERANGE,
	138	[ENOSYS] = TARGET_ENOSYS,
c29b1bee	139	#ifdef ELOOP
d6ce52c1	140	[ELOOP] = TARGET_ELOOP,
c29b1bee	141	#endif
d6ce52c1 MF	142	};
	143
	144	if (host_errno == 0) {
	145	return 0;
	146	} else if (host_errno > 0 && host_errno < ARRAY_SIZE(guest_errno) &&
	147	guest_errno[host_errno]) {
	148	return guest_errno[host_errno];
	149	} else {
	150	return TARGET_EINVAL;
	151	}
	152	}
	153
5aa37f48 MF	154	typedef struct XtensaSimConsole {
	155	CharBackend be;
	156	struct {
	157	char buffer[16];
	158	size_t offset;
	159	} input;
	160	} XtensaSimConsole;
	161
	162	static XtensaSimConsole *sim_console;
	163
	164	static IOCanReadHandler sim_console_can_read;
	165	static int sim_console_can_read(void *opaque)
	166	{
	167	XtensaSimConsole *p = opaque;
	168
	169	return sizeof(p->input.buffer) - p->input.offset;
	170	}
	171
	172	static IOReadHandler sim_console_read;
	173	static void sim_console_read(void opaque, const uint8_t buf, int size)
	174	{
	175	XtensaSimConsole *p = opaque;
	176	size_t copy = sizeof(p->input.buffer) - p->input.offset;
	177
	178	if (size < copy) {
	179	copy = size;
	180	}
	181	memcpy(p->input.buffer + p->input.offset, buf, copy);
	182	p->input.offset += copy;
	183	}
	184
8128b3e0 MF	185	void xtensa_sim_open_console(Chardev *chr)
8128b3e0 MF	186	{
5aa37f48	187	static XtensaSimConsole console;
8128b3e0	188
5aa37f48 MF	189	qemu_chr_fe_init(&console.be, chr, &error_abort);
	190	qemu_chr_fe_set_handlers(&console.be,
	191	sim_console_can_read,
	192	sim_console_read,
	193	NULL, NULL, &console,
	194	NULL, true);
	195	sim_console = &console;
8128b3e0 MF	196	}
8128b3e0 MF	197
d4a5b622	198	void HELPER(simcall)(CPUXtensaState *env)
1ddeaa5d	199	{
00b941e5	200	CPUState *cs = CPU(xtensa_env_get_cpu(env));
1ddeaa5d MF	201	uint32_t *regs = env->regs;
	202
	203	switch (regs[2]) {
	204	case TARGET_SYS_exit:
	205	qemu_log("exit(%d) simcall\n", regs[3]);
	206	exit(regs[3]);
	207	break;
	208
	209	case TARGET_SYS_read:
	210	case TARGET_SYS_write:
	211	{
	212	bool is_write = regs[2] == TARGET_SYS_write;
	213	uint32_t fd = regs[3];
	214	uint32_t vaddr = regs[4];
	215	uint32_t len = regs[5];
347ec030	216	uint32_t len_done = 0;
1ddeaa5d MF	217
1ddeaa5d MF	218	while (len > 0) {
00b941e5	219	hwaddr paddr = cpu_get_phys_page_debug(cs, vaddr);
1ddeaa5d MF	220	uint32_t page_left =
	221	TARGET_PAGE_SIZE - (vaddr & (TARGET_PAGE_SIZE - 1));
	222	uint32_t io_sz = page_left < len ? page_left : len;
a8170e5e	223	hwaddr sz = io_sz;
30c2afd1	224	void *buf = cpu_physical_memory_map(paddr, &sz, !is_write);
347ec030 MF	225	uint32_t io_done;
347ec030 MF	226	bool error = false;
1ddeaa5d MF	227
	228	if (buf) {
	229	vaddr += io_sz;
	230	len -= io_sz;
5aa37f48	231	if (fd < 3 && sim_console) {
8128b3e0	232	if (is_write && (fd == 1 \|\| fd == 2)) {
5aa37f48	233	io_done = qemu_chr_fe_write_all(&sim_console->be,
8128b3e0 MF	234	buf, io_sz);
8128b3e0 MF	235	regs[3] = errno_h2g(errno);
5aa37f48 MF	236	} else if (!is_write && fd == 0) {
	237	if (sim_console->input.offset) {
	238	io_done = sim_console->input.offset;
	239	if (io_sz < io_done) {
	240	io_done = io_sz;
	241	}
	242	memcpy(buf, sim_console->input.buffer, io_done);
	243	memmove(sim_console->input.buffer,
	244	sim_console->input.buffer + io_done,
	245	sim_console->input.offset - io_done);
	246	sim_console->input.offset -= io_done;
	247	qemu_chr_fe_accept_input(&sim_console->be);
	248	} else {
	249	io_done = -1;
	250	regs[3] = TARGET_EAGAIN;
	251	}
8128b3e0 MF	252	} else {
	253	qemu_log_mask(LOG_GUEST_ERROR,
	254	"%s fd %d is not supported with chardev console\n",
	255	is_write ?
	256	"writing to" : "reading from", fd);
	257	io_done = -1;
	258	regs[3] = TARGET_EBADF;
	259	}
	260	} else {
	261	io_done = is_write ?
	262	write(fd, buf, io_sz) :
	263	read(fd, buf, io_sz);
	264	regs[3] = errno_h2g(errno);
	265	}
347ec030 MF	266	if (io_done == -1) {
	267	error = true;
	268	io_done = 0;
1ddeaa5d	269	}
347ec030	270	cpu_physical_memory_unmap(buf, sz, !is_write, io_done);
1ddeaa5d	271	} else {
347ec030	272	error = true;
d6ce52c1	273	regs[3] = TARGET_EINVAL;
1ddeaa5d MF	274	break;
1ddeaa5d MF	275	}
347ec030 MF	276	if (error) {
	277	if (!len_done) {
	278	len_done = -1;
	279	}
	280	break;
	281	}
	282	len_done += io_done;
	283	if (io_done < io_sz) {
	284	break;
	285	}
1ddeaa5d	286	}
347ec030	287	regs[2] = len_done;
1ddeaa5d MF	288	}
	289	break;
	290
	291	case TARGET_SYS_open:
	292	{
	293	char name[1024];
	294	int rc;
	295	int i;
	296
	297	for (i = 0; i < ARRAY_SIZE(name); ++i) {
f17ec444 AF	298	rc = cpu_memory_rw_debug(cs, regs[3] + i,
f17ec444 AF	299	(uint8_t *)name + i, 1, 0);
1ddeaa5d MF	300	if (rc != 0 \|\| name[i] == 0) {
	301	break;
	302	}
	303	}
	304
	305	if (rc == 0 && i < ARRAY_SIZE(name)) {
	306	regs[2] = open(name, regs[4], regs[5]);
d6ce52c1	307	regs[3] = errno_h2g(errno);
1ddeaa5d MF	308	} else {
1ddeaa5d MF	309	regs[2] = -1;
d6ce52c1	310	regs[3] = TARGET_EINVAL;
1ddeaa5d MF	311	}
	312	}
	313	break;
	314
	315	case TARGET_SYS_close:
	316	if (regs[3] < 3) {
	317	regs[2] = regs[3] = 0;
	318	} else {
	319	regs[2] = close(regs[3]);
d6ce52c1	320	regs[3] = errno_h2g(errno);
1ddeaa5d MF	321	}
	322	break;
	323
	324	case TARGET_SYS_lseek:
	325	regs[2] = lseek(regs[3], (off_t)(int32_t)regs[4], regs[5]);
d6ce52c1	326	regs[3] = errno_h2g(errno);
1ddeaa5d MF	327	break;
	328
	329	case TARGET_SYS_select_one:
	330	{
	331	uint32_t fd = regs[3];
	332	uint32_t rq = regs[4];
	333	uint32_t target_tv = regs[5];
	334	uint32_t target_tvv[2];
	335
	336	struct timeval tv = {0};
1ddeaa5d MF	337
1ddeaa5d MF	338	if (target_tv) {
f17ec444	339	cpu_memory_rw_debug(cs, target_tv,
1ddeaa5d MF	340	(uint8_t *)target_tvv, sizeof(target_tvv), 0);
	341	tv.tv_sec = (int32_t)tswap32(target_tvv[0]);
	342	tv.tv_usec = (int32_t)tswap32(target_tvv[1]);
	343	}
5aa37f48	344	if (fd < 3 && sim_console) {
8128b3e0 MF	345	if ((fd == 1 \|\| fd == 2) && rq == SELECT_ONE_WRITE) {
8128b3e0 MF	346	regs[2] = 1;
5aa37f48 MF	347	} else if (fd == 0 && rq == SELECT_ONE_READ) {
5aa37f48 MF	348	regs[2] = sim_console->input.offset > 0;
8128b3e0 MF	349	} else {
	350	regs[2] = 0;
	351	}
	352	regs[3] = 0;
	353	} else {
	354	fd_set fdset;
	355
	356	FD_ZERO(&fdset);
	357	FD_SET(fd, &fdset);
	358	regs[2] = select(fd + 1,
	359	rq == SELECT_ONE_READ ? &fdset : NULL,
	360	rq == SELECT_ONE_WRITE ? &fdset : NULL,
	361	rq == SELECT_ONE_EXCEPT ? &fdset : NULL,
	362	target_tv ? &tv : NULL);
	363	regs[3] = errno_h2g(errno);
	364	}
1ddeaa5d MF	365	}
	366	break;
	367
	368	case TARGET_SYS_argc:
f289bb09	369	regs[2] = semihosting_get_argc();
1ddeaa5d MF	370	regs[3] = 0;
	371	break;
	372
	373	case TARGET_SYS_argv_sz:
f289bb09 MF	374	{
	375	int argc = semihosting_get_argc();
	376	int sz = (argc + 1) * sizeof(uint32_t);
	377	int i;
	378
	379	for (i = 0; i < argc; ++i) {
	380	sz += 1 + strlen(semihosting_get_arg(i));
	381	}
	382	regs[2] = sz;
	383	regs[3] = 0;
	384	}
1ddeaa5d MF	385	break;
	386
	387	case TARGET_SYS_argv:
	388	{
f289bb09 MF	389	int argc = semihosting_get_argc();
	390	int str_offset = (argc + 1) * sizeof(uint32_t);
	391	int i;
	392	uint32_t argptr;
	393
	394	for (i = 0; i < argc; ++i) {
	395	const char *str = semihosting_get_arg(i);
	396	int str_size = strlen(str) + 1;
	397
	398	argptr = tswap32(regs[3] + str_offset);
	399
	400	cpu_memory_rw_debug(cs,
	401	regs[3] + i * sizeof(uint32_t),
	402	(uint8_t *)&argptr, sizeof(argptr), 1);
	403	cpu_memory_rw_debug(cs,
	404	regs[3] + str_offset,
	405	(uint8_t *)str, str_size, 1);
	406	str_offset += str_size;
	407	}
	408	argptr = 0;
f17ec444	409	cpu_memory_rw_debug(cs,
f289bb09 MF	410	regs[3] + i * sizeof(uint32_t),
	411	(uint8_t *)&argptr, sizeof(argptr), 1);
	412	regs[3] = 0;
1ddeaa5d MF	413	}
	414	break;
	415
	416	case TARGET_SYS_memset:
	417	{
	418	uint32_t base = regs[3];
	419	uint32_t sz = regs[5];
	420
	421	while (sz) {
a8170e5e	422	hwaddr len = sz;
1ddeaa5d MF	423	void *buf = cpu_physical_memory_map(base, &len, 1);
	424
	425	if (buf && len) {
	426	memset(buf, regs[4], len);
	427	cpu_physical_memory_unmap(buf, len, 1, len);
	428	} else {
	429	len = 1;
	430	}
	431	base += len;
	432	sz -= len;
	433	}
	434	regs[2] = regs[3];
	435	regs[3] = 0;
	436	}
	437	break;
	438
	439	default:
c30f0d18	440	qemu_log_mask(LOG_GUEST_ERROR, "%s(%d): not implemented\n", __func__, regs[2]);
e7eee62a	441	regs[2] = -1;
d6ce52c1	442	regs[3] = TARGET_ENOSYS;
1ddeaa5d MF	443	break;
	444	}
	445	}