[qemu.git] / hw / net / fsl_etsec / etsec.c

/*
 * QEMU Freescale eTSEC Emulator
 *
 * Copyright (c) 2011-2013 AdaCore
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

/*
 * This implementation doesn't include ring priority, TCP/IP Off-Load, QoS.
 */

#include "qemu/osdep.h"
#include "sysemu/sysemu.h"
#include "hw/sysbus.h"
#include "trace.h"
#include "hw/ptimer.h"
#include "etsec.h"
#include "registers.h"
#include "qemu/log.h"

/* #define HEX_DUMP */
/* #define DEBUG_REGISTER */

#ifdef DEBUG_REGISTER
static const int debug_etsec = 1;
#else
static const int debug_etsec;
#endif

#define DPRINTF(fmt, ...) do {                 \
    if (debug_etsec) {                         \
        qemu_log(fmt , ## __VA_ARGS__);        \
    }                                          \
    } while (0)

static uint64_t etsec_read(void *opaque, hwaddr addr, unsigned size)
{
    eTSEC          *etsec     = opaque;
    uint32_t        reg_index = addr / 4;
    eTSEC_Register *reg       = NULL;
    uint32_t        ret       = 0x0;

    assert(reg_index < ETSEC_REG_NUMBER);

    reg = &etsec->regs[reg_index];


    switch (reg->access) {
    case ACC_WO:
        ret = 0x00000000;
        break;

    case ACC_RW:
    case ACC_W1C:
    case ACC_RO:
    default:
        ret = reg->value;
        break;
    }

    DPRINTF("Read  0x%08x @ 0x" TARGET_FMT_plx
            "                            : %s (%s)\n",
            ret, addr, reg->name, reg->desc);

    return ret;
}

static void write_tstat(eTSEC          *etsec,
                        eTSEC_Register *reg,
                        uint32_t        reg_index,
                        uint32_t        value)
{
    int i = 0;

    for (i = 0; i < 8; i++) {
        /* Check THLTi flag in TSTAT */
        if (value & (1 << (31 - i))) {
            etsec_walk_tx_ring(etsec, i);
        }
    }

    /* Write 1 to clear */
    reg->value &= ~value;
}

static void write_rstat(eTSEC          *etsec,
                        eTSEC_Register *reg,
                        uint32_t        reg_index,
                        uint32_t        value)
{
    int i = 0;

    for (i = 0; i < 8; i++) {
        /* Check QHLTi flag in RSTAT */
        if (value & (1 << (23 - i)) && !(reg->value & (1 << (23 - i)))) {
            etsec_walk_rx_ring(etsec, i);
        }
    }

    /* Write 1 to clear */
    reg->value &= ~value;
}

static void write_tbasex(eTSEC          *etsec,
                         eTSEC_Register *reg,
                         uint32_t        reg_index,
                         uint32_t        value)
{
    reg->value = value & ~0x7;

    /* Copy this value in the ring's TxBD pointer */
    etsec->regs[TBPTR0 + (reg_index - TBASE0)].value = value & ~0x7;
}

static void write_rbasex(eTSEC          *etsec,
                         eTSEC_Register *reg,
                         uint32_t        reg_index,
                         uint32_t        value)
{
    reg->value = value & ~0x7;

    /* Copy this value in the ring's RxBD pointer */
    etsec->regs[RBPTR0 + (reg_index - RBASE0)].value = value & ~0x7;
}

static void write_ievent(eTSEC          *etsec,
                         eTSEC_Register *reg,
                         uint32_t        reg_index,
                         uint32_t        value)
{
    /* Write 1 to clear */
    reg->value &= ~value;

    if (!(reg->value & (IEVENT_TXF | IEVENT_TXF))) {
        qemu_irq_lower(etsec->tx_irq);
    }
    if (!(reg->value & (IEVENT_RXF | IEVENT_RXF))) {
        qemu_irq_lower(etsec->rx_irq);
    }

    if (!(reg->value & (IEVENT_MAG | IEVENT_GTSC | IEVENT_GRSC | IEVENT_TXC |
                        IEVENT_RXC | IEVENT_BABR | IEVENT_BABT | IEVENT_LC |
                        IEVENT_CRL | IEVENT_FGPI | IEVENT_FIR | IEVENT_FIQ |
                        IEVENT_DPE | IEVENT_PERR | IEVENT_EBERR | IEVENT_TXE |
                        IEVENT_XFUN | IEVENT_BSY | IEVENT_MSRO | IEVENT_MMRD |
                        IEVENT_MMRW))) {
        qemu_irq_lower(etsec->err_irq);
    }
}

static void write_dmactrl(eTSEC          *etsec,
                          eTSEC_Register *reg,
                          uint32_t        reg_index,
                          uint32_t        value)
{
    reg->value = value;

    if (value & DMACTRL_GRS) {

        if (etsec->rx_buffer_len != 0) {
            /* Graceful receive stop delayed until end of frame */
        } else {
            /* Graceful receive stop now */
            etsec->regs[IEVENT].value |= IEVENT_GRSC;
            if (etsec->regs[IMASK].value & IMASK_GRSCEN) {
                qemu_irq_raise(etsec->err_irq);
            }
        }
    }

    if (value & DMACTRL_GTS) {

        if (etsec->tx_buffer_len != 0) {
            /* Graceful transmit stop delayed until end of frame */
        } else {
            /* Graceful transmit stop now */
            etsec->regs[IEVENT].value |= IEVENT_GTSC;
            if (etsec->regs[IMASK].value & IMASK_GTSCEN) {
                qemu_irq_raise(etsec->err_irq);
            }
        }
    }

    if (!(value & DMACTRL_WOP)) {
        /* Start polling */
        ptimer_stop(etsec->ptimer);
        ptimer_set_count(etsec->ptimer, 1);
        ptimer_run(etsec->ptimer, 1);
    }
}

static void etsec_write(void     *opaque,
                        hwaddr    addr,
                        uint64_t  value,
                        unsigned  size)
{
    eTSEC          *etsec     = opaque;
    uint32_t        reg_index = addr / 4;
    eTSEC_Register *reg       = NULL;
    uint32_t        before    = 0x0;

    assert(reg_index < ETSEC_REG_NUMBER);

    reg = &etsec->regs[reg_index];
    before = reg->value;

    switch (reg_index) {
    case IEVENT:
        write_ievent(etsec, reg, reg_index, value);
        break;

    case DMACTRL:
        write_dmactrl(etsec, reg, reg_index, value);
        break;

    case TSTAT:
        write_tstat(etsec, reg, reg_index, value);
        break;

    case RSTAT:
        write_rstat(etsec, reg, reg_index, value);
        break;

    case TBASE0 ... TBASE7:
        write_tbasex(etsec, reg, reg_index, value);
        break;

    case RBASE0 ... RBASE7:
        write_rbasex(etsec, reg, reg_index, value);
        break;

    case MIIMCFG ... MIIMIND:
        etsec_write_miim(etsec, reg, reg_index, value);
        break;

    default:
        /* Default handling */
        switch (reg->access) {

        case ACC_RW:
        case ACC_WO:
            reg->value = value;
            break;

        case ACC_W1C:
            reg->value &= ~value;
            break;

        case ACC_RO:
        default:
            /* Read Only or Unknown register */
            break;
        }
    }

    DPRINTF("Write 0x%08x @ 0x" TARGET_FMT_plx
            " val:0x%08x->0x%08x : %s (%s)\n",
            (unsigned int)value, addr, before, reg->value,
            reg->name, reg->desc);
}

static const MemoryRegionOps etsec_ops = {
    .read = etsec_read,
    .write = etsec_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .impl = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

static void etsec_timer_hit(void *opaque)
{
    eTSEC *etsec = opaque;

    ptimer_stop(etsec->ptimer);

    if (!(etsec->regs[DMACTRL].value & DMACTRL_WOP)) {

        if (!(etsec->regs[DMACTRL].value & DMACTRL_GTS)) {
            etsec_walk_tx_ring(etsec, 0);
        }
        ptimer_set_count(etsec->ptimer, 1);
        ptimer_run(etsec->ptimer, 1);
    }
}

static void etsec_reset(DeviceState *d)
{
    eTSEC *etsec = ETSEC_COMMON(d);
    int i = 0;
    int reg_index = 0;

    /* Default value for all registers */
    for (i = 0; i < ETSEC_REG_NUMBER; i++) {
        etsec->regs[i].name   = "Reserved";
        etsec->regs[i].desc   = "";
        etsec->regs[i].access = ACC_UNKNOWN;
        etsec->regs[i].value  = 0x00000000;
    }

    /* Set-up known registers */
    for (i = 0; eTSEC_registers_def[i].name != NULL; i++) {

        reg_index = eTSEC_registers_def[i].offset / 4;

        etsec->regs[reg_index].name   = eTSEC_registers_def[i].name;
        etsec->regs[reg_index].desc   = eTSEC_registers_def[i].desc;
        etsec->regs[reg_index].access = eTSEC_registers_def[i].access;
        etsec->regs[reg_index].value  = eTSEC_registers_def[i].reset;
    }

    etsec->tx_buffer     = NULL;
    etsec->tx_buffer_len = 0;
    etsec->rx_buffer     = NULL;
    etsec->rx_buffer_len = 0;

    etsec->phy_status =
        MII_SR_EXTENDED_CAPS    | MII_SR_LINK_STATUS   | MII_SR_AUTONEG_CAPS  |
        MII_SR_AUTONEG_COMPLETE | MII_SR_PREAMBLE_SUPPRESS |
        MII_SR_EXTENDED_STATUS  | MII_SR_100T2_HD_CAPS | MII_SR_100T2_FD_CAPS |
        MII_SR_10T_HD_CAPS      | MII_SR_10T_FD_CAPS   | MII_SR_100X_HD_CAPS  |
        MII_SR_100X_FD_CAPS     | MII_SR_100T4_CAPS;
}

static ssize_t etsec_receive(NetClientState *nc,
                             const uint8_t  *buf,
                             size_t          size)
{
    ssize_t ret;
    eTSEC *etsec = qemu_get_nic_opaque(nc);

#if defined(HEX_DUMP)
    fprintf(stderr, "%s receive size:%d\n", etsec->nic->nc.name, size);
    qemu_hexdump(buf, stderr, "", size);
#endif
    /* Flush is unnecessary as are already in receiving path */
    etsec->need_flush = false;
    ret = etsec_rx_ring_write(etsec, buf, size);
    if (ret == 0) {
        /* The packet will be queued, let's flush it when buffer is available
         * again. */
        etsec->need_flush = true;
    }
    return ret;
}


static void etsec_set_link_status(NetClientState *nc)
{
    eTSEC *etsec = qemu_get_nic_opaque(nc);

    etsec_miim_link_status(etsec, nc);
}

static NetClientInfo net_etsec_info = {
    .type = NET_CLIENT_OPTIONS_KIND_NIC,
    .size = sizeof(NICState),
    .receive = etsec_receive,
    .link_status_changed = etsec_set_link_status,
};

static void etsec_realize(DeviceState *dev, Error **errp)
{
    eTSEC        *etsec = ETSEC_COMMON(dev);

    etsec->nic = qemu_new_nic(&net_etsec_info, &etsec->conf,
                              object_get_typename(OBJECT(dev)), dev->id, etsec);
    qemu_format_nic_info_str(qemu_get_queue(etsec->nic), etsec->conf.macaddr.a);


    etsec->bh     = qemu_bh_new(etsec_timer_hit, etsec);
    etsec->ptimer = ptimer_init(etsec->bh);
    ptimer_set_freq(etsec->ptimer, 100);
}

static void etsec_instance_init(Object *obj)
{
    eTSEC        *etsec = ETSEC_COMMON(obj);
    SysBusDevice *sbd   = SYS_BUS_DEVICE(obj);

    memory_region_init_io(&etsec->io_area, OBJECT(etsec), &etsec_ops, etsec,
                          "eTSEC", 0x1000);
    sysbus_init_mmio(sbd, &etsec->io_area);

    sysbus_init_irq(sbd, &etsec->tx_irq);
    sysbus_init_irq(sbd, &etsec->rx_irq);
    sysbus_init_irq(sbd, &etsec->err_irq);
}

static Property etsec_properties[] = {
    DEFINE_NIC_PROPERTIES(eTSEC, conf),
    DEFINE_PROP_END_OF_LIST(),
};

static void etsec_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = etsec_realize;
    dc->reset = etsec_reset;
    dc->props = etsec_properties;
}

static TypeInfo etsec_info = {
    .name                  = "eTSEC",
    .parent                = TYPE_SYS_BUS_DEVICE,
    .instance_size         = sizeof(eTSEC),
    .class_init            = etsec_class_init,
    .instance_init         = etsec_instance_init,
};

static void etsec_register_types(void)
{
    type_register_static(&etsec_info);
}

type_init(etsec_register_types)

DeviceState *etsec_create(hwaddr         base,
                          MemoryRegion * mr,
                          NICInfo      * nd,
                          qemu_irq       tx_irq,
                          qemu_irq       rx_irq,
                          qemu_irq       err_irq)
{
    DeviceState *dev;

    dev = qdev_create(NULL, "eTSEC");
    qdev_set_nic_properties(dev, nd);
    qdev_init_nofail(dev);

    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, tx_irq);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, rx_irq);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, err_irq);

    memory_region_add_subregion(mr, base,
                                SYS_BUS_DEVICE(dev)->mmio[0].memory);

    return dev;
}
Commit	Line	Data
eb1e7c3e FC	1	/*
	2	* QEMU Freescale eTSEC Emulator
	3	*
	4	* Copyright (c) 2011-2013 AdaCore
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	/*
	26	* This implementation doesn't include ring priority, TCP/IP Off-Load, QoS.
	27	*/
	28
e8d40465	29	#include "qemu/osdep.h"
eb1e7c3e FC	30	#include "sysemu/sysemu.h"
	31	#include "hw/sysbus.h"
	32	#include "trace.h"
	33	#include "hw/ptimer.h"
	34	#include "etsec.h"
	35	#include "registers.h"
03dd024f	36	#include "qemu/log.h"
eb1e7c3e FC	37
	38	/* #define HEX_DUMP */
	39	/* #define DEBUG_REGISTER */
	40
	41	#ifdef DEBUG_REGISTER
	42	static const int debug_etsec = 1;
	43	#else
	44	static const int debug_etsec;
	45	#endif
	46
	47	#define DPRINTF(fmt, ...) do { \
	48	if (debug_etsec) { \
	49	qemu_log(fmt , ## __VA_ARGS__); \
	50	} \
	51	} while (0)
	52
	53	static uint64_t etsec_read(void *opaque, hwaddr addr, unsigned size)
	54	{
	55	eTSEC *etsec = opaque;
	56	uint32_t reg_index = addr / 4;
	57	eTSEC_Register *reg = NULL;
	58	uint32_t ret = 0x0;
	59
	60	assert(reg_index < ETSEC_REG_NUMBER);
	61
	62	reg = &etsec->regs[reg_index];
	63
	64
	65	switch (reg->access) {
	66	case ACC_WO:
	67	ret = 0x00000000;
	68	break;
	69
	70	case ACC_RW:
	71	case ACC_W1C:
	72	case ACC_RO:
	73	default:
	74	ret = reg->value;
	75	break;
	76	}
	77
	78	DPRINTF("Read 0x%08x @ 0x" TARGET_FMT_plx
	79	" : %s (%s)\n",
	80	ret, addr, reg->name, reg->desc);
	81
	82	return ret;
	83	}
	84
	85	static void write_tstat(eTSEC *etsec,
	86	eTSEC_Register *reg,
	87	uint32_t reg_index,
	88	uint32_t value)
	89	{
	90	int i = 0;
	91
	92	for (i = 0; i < 8; i++) {
	93	/* Check THLTi flag in TSTAT */
	94	if (value & (1 << (31 - i))) {
	95	etsec_walk_tx_ring(etsec, i);
	96	}
	97	}
	98
	99	/* Write 1 to clear */
	100	reg->value &= ~value;
101	}
102
103	static void write_rstat(eTSEC *etsec,
104	eTSEC_Register *reg,
105	uint32_t reg_index,
106	uint32_t value)
107	{
108	int i = 0;
109
110	for (i = 0; i < 8; i++) {
111	/* Check QHLTi flag in RSTAT */
112	if (value & (1 << (23 - i)) && !(reg->value & (1 << (23 - i)))) {
113	etsec_walk_rx_ring(etsec, i);
114	}
115	}
116
117	/* Write 1 to clear */
118	reg->value &= ~value;
119	}
120
121	static void write_tbasex(eTSEC *etsec,
122	eTSEC_Register *reg,
123	uint32_t reg_index,
124	uint32_t value)
125	{
126	reg->value = value & ~0x7;
127
128	/* Copy this value in the ring's TxBD pointer */
129	etsec->regs[TBPTR0 + (reg_index - TBASE0)].value = value & ~0x7;
130	}
131
132	static void write_rbasex(eTSEC *etsec,
133	eTSEC_Register *reg,
134	uint32_t reg_index,
135	uint32_t value)
136	{
137	reg->value = value & ~0x7;
138
139	/* Copy this value in the ring's RxBD pointer */
140	etsec->regs[RBPTR0 + (reg_index - RBASE0)].value = value & ~0x7;
141	}
142
143	static void write_ievent(eTSEC *etsec,
144	eTSEC_Register *reg,
145	uint32_t reg_index,
146	uint32_t value)
147	{
148	/* Write 1 to clear */
149	reg->value &= ~value;
150
151	if (!(reg->value & (IEVENT_TXF \| IEVENT_TXF))) {
152	qemu_irq_lower(etsec->tx_irq);
153	}
154	if (!(reg->value & (IEVENT_RXF \| IEVENT_RXF))) {
155	qemu_irq_lower(etsec->rx_irq);
156	}
157
158	if (!(reg->value & (IEVENT_MAG \| IEVENT_GTSC \| IEVENT_GRSC \| IEVENT_TXC \|
159	IEVENT_RXC \| IEVENT_BABR \| IEVENT_BABT \| IEVENT_LC \|
160	IEVENT_CRL \| IEVENT_FGPI \| IEVENT_FIR \| IEVENT_FIQ \|
161	IEVENT_DPE \| IEVENT_PERR \| IEVENT_EBERR \| IEVENT_TXE \|
162	IEVENT_XFUN \| IEVENT_BSY \| IEVENT_MSRO \| IEVENT_MMRD \|
163	IEVENT_MMRW))) {
164	qemu_irq_lower(etsec->err_irq);
165	}
166	}
167
168	static void write_dmactrl(eTSEC *etsec,
169	eTSEC_Register *reg,
170	uint32_t reg_index,
171	uint32_t value)
172	{
173	reg->value = value;
174
175	if (value & DMACTRL_GRS) {
176
177	if (etsec->rx_buffer_len != 0) {
178	/* Graceful receive stop delayed until end of frame */
179	} else {
180	/* Graceful receive stop now */
181	etsec->regs[IEVENT].value \|= IEVENT_GRSC;
182	if (etsec->regs[IMASK].value & IMASK_GRSCEN) {
183	qemu_irq_raise(etsec->err_irq);
184	}
185	}
186	}
187
188	if (value & DMACTRL_GTS) {
189
190	if (etsec->tx_buffer_len != 0) {
191	/* Graceful transmit stop delayed until end of frame */
192	} else {
193	/* Graceful transmit stop now */
194	etsec->regs[IEVENT].value \|= IEVENT_GTSC;
195	if (etsec->regs[IMASK].value & IMASK_GTSCEN) {
196	qemu_irq_raise(etsec->err_irq);
197	}
198	}
199	}
200
201	if (!(value & DMACTRL_WOP)) {
202	/* Start polling */
203	ptimer_stop(etsec->ptimer);
204	ptimer_set_count(etsec->ptimer, 1);
205	ptimer_run(etsec->ptimer, 1);
206	}
207	}
208
209	static void etsec_write(void *opaque,
210	hwaddr addr,
211	uint64_t value,
212	unsigned size)
213	{
214	eTSEC *etsec = opaque;
215	uint32_t reg_index = addr / 4;
216	eTSEC_Register *reg = NULL;
217	uint32_t before = 0x0;
218
219	assert(reg_index < ETSEC_REG_NUMBER);
220
221	reg = &etsec->regs[reg_index];
222	before = reg->value;
223
224	switch (reg_index) {
225	case IEVENT:
226	write_ievent(etsec, reg, reg_index, value);
227	break;
228
229	case DMACTRL:
230	write_dmactrl(etsec, reg, reg_index, value);
231	break;
232
233	case TSTAT:
234	write_tstat(etsec, reg, reg_index, value);
235	break;
236
237	case RSTAT:
238	write_rstat(etsec, reg, reg_index, value);
239	break;
240
241	case TBASE0 ... TBASE7:
242	write_tbasex(etsec, reg, reg_index, value);
243	break;
244
245	case RBASE0 ... RBASE7:
246	write_rbasex(etsec, reg, reg_index, value);
247	break;
248
249	case MIIMCFG ... MIIMIND:
250	etsec_write_miim(etsec, reg, reg_index, value);
251	break;
252
253	default:
254	/* Default handling */
255	switch (reg->access) {
256
257	case ACC_RW:
258	case ACC_WO:
259	reg->value = value;
260	break;
261
262	case ACC_W1C:
263	reg->value &= ~value;
264	break;
265
266	case ACC_RO:
267	default:
268	/* Read Only or Unknown register */
269	break;
270	}
271	}
272
273	DPRINTF("Write 0x%08x @ 0x" TARGET_FMT_plx
274	" val:0x%08x->0x%08x : %s (%s)\n",
275	(unsigned int)value, addr, before, reg->value,
276	reg->name, reg->desc);
277	}
278
279	static const MemoryRegionOps etsec_ops = {
280	.read = etsec_read,
281	.write = etsec_write,
282	.endianness = DEVICE_NATIVE_ENDIAN,
283	.impl = {
284	.min_access_size = 4,
285	.max_access_size = 4,
286	},
287	};
288
289	static void etsec_timer_hit(void *opaque)
290	{
291	eTSEC *etsec = opaque;
292
293	ptimer_stop(etsec->ptimer);
294
295	if (!(etsec->regs[DMACTRL].value & DMACTRL_WOP)) {
296
297	if (!(etsec->regs[DMACTRL].value & DMACTRL_GTS)) {
298	etsec_walk_tx_ring(etsec, 0);
299	}
300	ptimer_set_count(etsec->ptimer, 1);
301	ptimer_run(etsec->ptimer, 1);
302	}
303	}
304
305	static void etsec_reset(DeviceState *d)
306	{
307	eTSEC *etsec = ETSEC_COMMON(d);
308	int i = 0;
309	int reg_index = 0;
310
311	/* Default value for all registers */
312	for (i = 0; i < ETSEC_REG_NUMBER; i++) {
313	etsec->regs[i].name = "Reserved";
314	etsec->regs[i].desc = "";
315	etsec->regs[i].access = ACC_UNKNOWN;
316	etsec->regs[i].value = 0x00000000;
317	}
318
319	/* Set-up known registers */
320	for (i = 0; eTSEC_registers_def[i].name != NULL; i++) {
321
322	reg_index = eTSEC_registers_def[i].offset / 4;
323
324	etsec->regs[reg_index].name = eTSEC_registers_def[i].name;
325	etsec->regs[reg_index].desc = eTSEC_registers_def[i].desc;
326	etsec->regs[reg_index].access = eTSEC_registers_def[i].access;
327	etsec->regs[reg_index].value = eTSEC_registers_def[i].reset;
328	}
329
330	etsec->tx_buffer = NULL;
331	etsec->tx_buffer_len = 0;
332	etsec->rx_buffer = NULL;
333	etsec->rx_buffer_len = 0;
334
335	etsec->phy_status =
336	MII_SR_EXTENDED_CAPS \| MII_SR_LINK_STATUS \| MII_SR_AUTONEG_CAPS \|
337	MII_SR_AUTONEG_COMPLETE \| MII_SR_PREAMBLE_SUPPRESS \|
338	MII_SR_EXTENDED_STATUS \| MII_SR_100T2_HD_CAPS \| MII_SR_100T2_FD_CAPS \|
339	MII_SR_10T_HD_CAPS \| MII_SR_10T_FD_CAPS \| MII_SR_100X_HD_CAPS \|
340	MII_SR_100X_FD_CAPS \| MII_SR_100T4_CAPS;
341	}
342
eb1e7c3e FC	343	static ssize_t etsec_receive(NetClientState *nc,
	344	const uint8_t *buf,
	345	size_t size)
	346	{
575bafd1	347	ssize_t ret;
eb1e7c3e FC	348	eTSEC *etsec = qemu_get_nic_opaque(nc);
	349
	350	#if defined(HEX_DUMP)
	351	fprintf(stderr, "%s receive size:%d\n", etsec->nic->nc.name, size);
	352	qemu_hexdump(buf, stderr, "", size);
	353	#endif
575bafd1 FZ	354	/* Flush is unnecessary as are already in receiving path */
	355	etsec->need_flush = false;
	356	ret = etsec_rx_ring_write(etsec, buf, size);
	357	if (ret == 0) {
67cc32eb	358	/* The packet will be queued, let's flush it when buffer is available
575bafd1 FZ	359	* again. */
	360	etsec->need_flush = true;
	361	}
	362	return ret;
eb1e7c3e FC	363	}
	364
	365
	366	static void etsec_set_link_status(NetClientState *nc)
	367	{
	368	eTSEC *etsec = qemu_get_nic_opaque(nc);
	369
	370	etsec_miim_link_status(etsec, nc);
	371	}
	372
	373	static NetClientInfo net_etsec_info = {
	374	.type = NET_CLIENT_OPTIONS_KIND_NIC,
	375	.size = sizeof(NICState),
eb1e7c3e	376	.receive = etsec_receive,
eb1e7c3e FC	377	.link_status_changed = etsec_set_link_status,
	378	};
	379
	380	static void etsec_realize(DeviceState dev, Error *errp)
	381	{
	382	eTSEC *etsec = ETSEC_COMMON(dev);
	383
	384	etsec->nic = qemu_new_nic(&net_etsec_info, &etsec->conf,
	385	object_get_typename(OBJECT(dev)), dev->id, etsec);
	386	qemu_format_nic_info_str(qemu_get_queue(etsec->nic), etsec->conf.macaddr.a);
	387
	388
	389	etsec->bh = qemu_bh_new(etsec_timer_hit, etsec);
	390	etsec->ptimer = ptimer_init(etsec->bh);
	391	ptimer_set_freq(etsec->ptimer, 100);
	392	}
	393
	394	static void etsec_instance_init(Object *obj)
	395	{
	396	eTSEC *etsec = ETSEC_COMMON(obj);
	397	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
	398
	399	memory_region_init_io(&etsec->io_area, OBJECT(etsec), &etsec_ops, etsec,
	400	"eTSEC", 0x1000);
	401	sysbus_init_mmio(sbd, &etsec->io_area);
	402
	403	sysbus_init_irq(sbd, &etsec->tx_irq);
	404	sysbus_init_irq(sbd, &etsec->rx_irq);
	405	sysbus_init_irq(sbd, &etsec->err_irq);
	406	}
	407
	408	static Property etsec_properties[] = {
	409	DEFINE_NIC_PROPERTIES(eTSEC, conf),
	410	DEFINE_PROP_END_OF_LIST(),
	411	};
	412
	413	static void etsec_class_init(ObjectClass klass, void data)
	414	{
	415	DeviceClass *dc = DEVICE_CLASS(klass);
	416
	417	dc->realize = etsec_realize;
	418	dc->reset = etsec_reset;
	419	dc->props = etsec_properties;
	420	}
	421
	422	static TypeInfo etsec_info = {
	423	.name = "eTSEC",
	424	.parent = TYPE_SYS_BUS_DEVICE,
	425	.instance_size = sizeof(eTSEC),
	426	.class_init = etsec_class_init,
	427	.instance_init = etsec_instance_init,
	428	};
	429
	430	static void etsec_register_types(void)
	431	{
	432	type_register_static(&etsec_info);
	433	}
	434
	435	type_init(etsec_register_types)
	436
	437	DeviceState *etsec_create(hwaddr base,
	438	MemoryRegion * mr,
	439	NICInfo * nd,
	440	qemu_irq tx_irq,
441	qemu_irq rx_irq,
442	qemu_irq err_irq)
443	{
444	DeviceState *dev;
445
446	dev = qdev_create(NULL, "eTSEC");
447	qdev_set_nic_properties(dev, nd);
aef0d55a	448	qdev_init_nofail(dev);
eb1e7c3e FC	449
	450	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, tx_irq);
	451	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, rx_irq);
	452	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, err_irq);
	453
	454	memory_region_add_subregion(mr, base,
	455	SYS_BUS_DEVICE(dev)->mmio[0].memory);
	456
	457	return dev;
	458	}