[qemu.git] / hw / ide / piix.c

/*
 * QEMU IDE Emulation: PCI PIIX3/4 support.
 *
 * Copyright (c) 2003 Fabrice Bellard
 * Copyright (c) 2006 Openedhand Ltd.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include <hw/hw.h>
#include <hw/i386/pc.h>
#include <hw/pci/pci.h>
#include <hw/isa/isa.h>
#include "sysemu/blockdev.h"
#include "sysemu/sysemu.h"
#include "sysemu/dma.h"

#include <hw/ide/pci.h>

static uint64_t bmdma_read(void *opaque, hwaddr addr, unsigned size)
{
    BMDMAState *bm = opaque;
    uint32_t val;

    if (size != 1) {
        return ((uint64_t)1 << (size * 8)) - 1;
    }

    switch(addr & 3) {
    case 0:
        val = bm->cmd;
        break;
    case 2:
        val = bm->status;
        break;
    default:
        val = 0xff;
        break;
    }
#ifdef DEBUG_IDE
    printf("bmdma: readb 0x%02x : 0x%02x\n", (uint8_t)addr, val);
#endif
    return val;
}

static void bmdma_write(void *opaque, hwaddr addr,
                        uint64_t val, unsigned size)
{
    BMDMAState *bm = opaque;

    if (size != 1) {
        return;
    }

#ifdef DEBUG_IDE
    printf("bmdma: writeb 0x%02x : 0x%02x\n", (uint8_t)addr, (uint8_t)val);
#endif
    switch(addr & 3) {
    case 0:
        bmdma_cmd_writeb(bm, val);
        break;
    case 2:
        bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
        break;
    }
}

static const MemoryRegionOps piix_bmdma_ops = {
    .read = bmdma_read,
    .write = bmdma_write,
};

static void bmdma_setup_bar(PCIIDEState *d)
{
    int i;

    memory_region_init(&d->bmdma_bar, OBJECT(d), "piix-bmdma-container", 16);
    for(i = 0;i < 2; i++) {
        BMDMAState *bm = &d->bmdma[i];

        memory_region_init_io(&bm->extra_io, OBJECT(d), &piix_bmdma_ops, bm,
                              "piix-bmdma", 4);
        memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
        memory_region_init_io(&bm->addr_ioport, OBJECT(d),
                              &bmdma_addr_ioport_ops, bm, "bmdma", 4);
        memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
    }
}

static void piix3_reset(void *opaque)
{
    PCIIDEState *d = opaque;
    uint8_t *pci_conf = d->dev.config;
    int i;

    for (i = 0; i < 2; i++) {
        ide_bus_reset(&d->bus[i]);
    }

    /* TODO: this is the default. do not override. */
    pci_conf[PCI_COMMAND] = 0x00;
    /* TODO: this is the default. do not override. */
    pci_conf[PCI_COMMAND + 1] = 0x00;
    /* TODO: use pci_set_word */
    pci_conf[PCI_STATUS] = PCI_STATUS_FAST_BACK;
    pci_conf[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
    pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
}

static void pci_piix_init_ports(PCIIDEState *d) {
    static const struct {
        int iobase;
        int iobase2;
        int isairq;
    } port_info[] = {
        {0x1f0, 0x3f6, 14},
        {0x170, 0x376, 15},
    };
    int i;

    for (i = 0; i < 2; i++) {
        ide_bus_new(&d->bus[i], &d->dev.qdev, i, 2);
        ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
                        port_info[i].iobase2);
        ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));

        bmdma_init(&d->bus[i], &d->bmdma[i], d);
        d->bmdma[i].bus = &d->bus[i];
        qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
                                         &d->bmdma[i].dma);
    }
}

static int pci_piix_ide_initfn(PCIDevice *dev)
{
    PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
    uint8_t *pci_conf = d->dev.config;

    pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode

    qemu_register_reset(piix3_reset, d);

    bmdma_setup_bar(d);
    pci_register_bar(&d->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);

    vmstate_register(&d->dev.qdev, 0, &vmstate_ide_pci, d);

    pci_piix_init_ports(d);

    return 0;
}

static int pci_piix3_xen_ide_unplug(DeviceState *dev)
{
    PCIDevice *pci_dev;
    PCIIDEState *pci_ide;
    DriveInfo *di;
    int i = 0;

    pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
    pci_ide = DO_UPCAST(PCIIDEState, dev, pci_dev);

    for (; i < 3; i++) {
        di = drive_get_by_index(IF_IDE, i);
        if (di != NULL && !di->media_cd) {
            DeviceState *ds = bdrv_get_attached_dev(di->bdrv);
            if (ds) {
                bdrv_detach_dev(di->bdrv, ds);
            }
            bdrv_close(di->bdrv);
            pci_ide->bus[di->bus].ifs[di->unit].bs = NULL;
            drive_put_ref(di);
        }
    }
    qdev_reset_all(&(pci_ide->dev.qdev));
    return 0;
}

PCIDevice *pci_piix3_xen_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
{
    PCIDevice *dev;

    dev = pci_create_simple(bus, devfn, "piix3-ide-xen");
    pci_ide_create_devs(dev, hd_table);
    return dev;
}

static void pci_piix_ide_exitfn(PCIDevice *dev)
{
    PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
    unsigned i;

    for (i = 0; i < 2; ++i) {
        memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
        memory_region_destroy(&d->bmdma[i].extra_io);
        memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
        memory_region_destroy(&d->bmdma[i].addr_ioport);
    }
    memory_region_destroy(&d->bmdma_bar);
}

/* hd_table must contain 4 block drivers */
/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
PCIDevice *pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
{
    PCIDevice *dev;

    dev = pci_create_simple(bus, devfn, "piix3-ide");
    pci_ide_create_devs(dev, hd_table);
    return dev;
}

/* hd_table must contain 4 block drivers */
/* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
PCIDevice *pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
{
    PCIDevice *dev;

    dev = pci_create_simple(bus, devfn, "piix4-ide");
    pci_ide_create_devs(dev, hd_table);
    return dev;
}

static void piix3_ide_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->no_hotplug = 1;
    k->init = pci_piix_ide_initfn;
    k->exit = pci_piix_ide_exitfn;
    k->vendor_id = PCI_VENDOR_ID_INTEL;
    k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1;
    k->class_id = PCI_CLASS_STORAGE_IDE;
    set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
    dc->no_user = 1;
}

static const TypeInfo piix3_ide_info = {
    .name          = "piix3-ide",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIIDEState),
    .class_init    = piix3_ide_class_init,
};

static void piix3_ide_xen_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->init = pci_piix_ide_initfn;
    k->vendor_id = PCI_VENDOR_ID_INTEL;
    k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1;
    k->class_id = PCI_CLASS_STORAGE_IDE;
    set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
    dc->no_user = 1;
    dc->unplug = pci_piix3_xen_ide_unplug;
}

static const TypeInfo piix3_ide_xen_info = {
    .name          = "piix3-ide-xen",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIIDEState),
    .class_init    = piix3_ide_xen_class_init,
};

static void piix4_ide_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->no_hotplug = 1;
    k->init = pci_piix_ide_initfn;
    k->exit = pci_piix_ide_exitfn;
    k->vendor_id = PCI_VENDOR_ID_INTEL;
    k->device_id = PCI_DEVICE_ID_INTEL_82371AB;
    k->class_id = PCI_CLASS_STORAGE_IDE;
    set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
    dc->no_user = 1;
}

static const TypeInfo piix4_ide_info = {
    .name          = "piix4-ide",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIIDEState),
    .class_init    = piix4_ide_class_init,
};

static void piix_ide_register_types(void)
{
    type_register_static(&piix3_ide_info);
    type_register_static(&piix3_ide_xen_info);
    type_register_static(&piix4_ide_info);
}

type_init(piix_ide_register_types)
Commit	Line	Data
4c3df0ec JQ	1	/*
	2	* QEMU IDE Emulation: PCI PIIX3/4 support.
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	* Copyright (c) 2006 Openedhand Ltd.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
dfc65f1f	25
4c3df0ec	26	#include <hw/hw.h>
0d09e41a	27	#include <hw/i386/pc.h>
a2cb15b0	28	#include <hw/pci/pci.h>
0d09e41a	29	#include <hw/isa/isa.h>
9c17d615 PB	30	#include "sysemu/blockdev.h"
	31	#include "sysemu/sysemu.h"
	32	#include "sysemu/dma.h"
4c3df0ec JQ	33
	34	#include <hw/ide/pci.h>
	35
a8170e5e	36	static uint64_t bmdma_read(void *opaque, hwaddr addr, unsigned size)
4c3df0ec JQ	37	{
	38	BMDMAState *bm = opaque;
	39	uint32_t val;
	40
a9deb8c6 AK	41	if (size != 1) {
	42	return ((uint64_t)1 << (size * 8)) - 1;
	43	}
	44
4c3df0ec JQ	45	switch(addr & 3) {
	46	case 0:
	47	val = bm->cmd;
	48	break;
	49	case 2:
	50	val = bm->status;
	51	break;
	52	default:
	53	val = 0xff;
	54	break;
	55	}
	56	#ifdef DEBUG_IDE
cb67be85	57	printf("bmdma: readb 0x%02x : 0x%02x\n", (uint8_t)addr, val);
4c3df0ec JQ	58	#endif
	59	return val;
	60	}
	61
a8170e5e	62	static void bmdma_write(void *opaque, hwaddr addr,
a9deb8c6	63	uint64_t val, unsigned size)
4c3df0ec JQ	64	{
4c3df0ec JQ	65	BMDMAState *bm = opaque;
a9deb8c6 AK	66
	67	if (size != 1) {
	68	return;
	69	}
	70
4c3df0ec	71	#ifdef DEBUG_IDE
cb67be85	72	printf("bmdma: writeb 0x%02x : 0x%02x\n", (uint8_t)addr, (uint8_t)val);
4c3df0ec JQ	73	#endif
4c3df0ec JQ	74	switch(addr & 3) {
a9deb8c6	75	case 0:
0ed8b6f6 BS	76	bmdma_cmd_writeb(bm, val);
0ed8b6f6 BS	77	break;
4c3df0ec JQ	78	case 2:
	79	bm->status = (val & 0x60) \| (bm->status & 1) \| (bm->status & ~val & 0x06);
	80	break;
	81	}
	82	}
	83
a348f108	84	static const MemoryRegionOps piix_bmdma_ops = {
a9deb8c6 AK	85	.read = bmdma_read,
	86	.write = bmdma_write,
	87	};
	88
	89	static void bmdma_setup_bar(PCIIDEState *d)
4c3df0ec	90	{
4c3df0ec JQ	91	int i;
4c3df0ec JQ	92
1437c94b	93	memory_region_init(&d->bmdma_bar, OBJECT(d), "piix-bmdma-container", 16);
4c3df0ec JQ	94	for(i = 0;i < 2; i++) {
4c3df0ec JQ	95	BMDMAState *bm = &d->bmdma[i];
4c3df0ec	96
1437c94b	97	memory_region_init_io(&bm->extra_io, OBJECT(d), &piix_bmdma_ops, bm,
a9deb8c6 AK	98	"piix-bmdma", 4);
a9deb8c6 AK	99	memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
1437c94b PB	100	memory_region_init_io(&bm->addr_ioport, OBJECT(d),
1437c94b PB	101	&bmdma_addr_ioport_ops, bm, "bmdma", 4);
a9deb8c6	102	memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
4c3df0ec JQ	103	}
	104	}
	105
	106	static void piix3_reset(void *opaque)
	107	{
	108	PCIIDEState *d = opaque;
	109	uint8_t *pci_conf = d->dev.config;
	110	int i;
	111
4a643563 BS	112	for (i = 0; i < 2; i++) {
4a643563 BS	113	ide_bus_reset(&d->bus[i]);
4a643563	114	}
4c3df0ec	115
1e68f8c4 MT	116	/* TODO: this is the default. do not override. */
	117	pci_conf[PCI_COMMAND] = 0x00;
	118	/* TODO: this is the default. do not override. */
	119	pci_conf[PCI_COMMAND + 1] = 0x00;
	120	/* TODO: use pci_set_word */
	121	pci_conf[PCI_STATUS] = PCI_STATUS_FAST_BACK;
	122	pci_conf[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
4c3df0ec JQ	123	pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
	124	}
	125
61d9d6b0	126	static void pci_piix_init_ports(PCIIDEState *d) {
4a91d3b3	127	static const struct {
61d9d6b0 SH	128	int iobase;
	129	int iobase2;
	130	int isairq;
	131	} port_info[] = {
	132	{0x1f0, 0x3f6, 14},
	133	{0x170, 0x376, 15},
	134	};
4a91d3b3	135	int i;
61d9d6b0 SH	136
61d9d6b0 SH	137	for (i = 0; i < 2; i++) {
0ee20e66	138	ide_bus_new(&d->bus[i], &d->dev.qdev, i, 2);
4a91d3b3 RH	139	ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
4a91d3b3 RH	140	port_info[i].iobase2);
48a18b3c	141	ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));
61d9d6b0	142
a9deb8c6	143	bmdma_init(&d->bus[i], &d->bmdma[i], d);
61d9d6b0 SH	144	d->bmdma[i].bus = &d->bus[i];
	145	qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
	146	&d->bmdma[i].dma);
	147	}
	148	}
	149
25f8e2f5	150	static int pci_piix_ide_initfn(PCIDevice *dev)
4c3df0ec	151	{
25f8e2f5	152	PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
4c3df0ec JQ	153	uint8_t *pci_conf = d->dev.config;
4c3df0ec JQ	154
1e68f8c4	155	pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode
4c3df0ec JQ	156
4c3df0ec JQ	157	qemu_register_reset(piix3_reset, d);
4c3df0ec	158
a9deb8c6	159	bmdma_setup_bar(d);
e824b2cc	160	pci_register_bar(&d->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
4c3df0ec	161
0be71e32	162	vmstate_register(&d->dev.qdev, 0, &vmstate_ide_pci, d);
4c3df0ec	163
61d9d6b0	164	pci_piix_init_ports(d);
4c3df0ec	165
4c3df0ec JQ	166	return 0;
	167	}
	168
679f4f8b SS	169	static int pci_piix3_xen_ide_unplug(DeviceState *dev)
	170	{
	171	PCIDevice *pci_dev;
	172	PCIIDEState *pci_ide;
	173	DriveInfo *di;
	174	int i = 0;
	175
	176	pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
	177	pci_ide = DO_UPCAST(PCIIDEState, dev, pci_dev);
	178
	179	for (; i < 3; i++) {
	180	di = drive_get_by_index(IF_IDE, i);
f9e8fda4	181	if (di != NULL && !di->media_cd) {
fa879d62	182	DeviceState *ds = bdrv_get_attached_dev(di->bdrv);
679f4f8b	183	if (ds) {
fa879d62	184	bdrv_detach_dev(di->bdrv, ds);
679f4f8b SS	185	}
	186	bdrv_close(di->bdrv);
	187	pci_ide->bus[di->bus].ifs[di->unit].bs = NULL;
	188	drive_put_ref(di);
	189	}
	190	}
	191	qdev_reset_all(&(pci_ide->dev.qdev));
	192	return 0;
	193	}
	194
	195	PCIDevice pci_piix3_xen_ide_init(PCIBus bus, DriveInfo **hd_table, int devfn)
	196	{
	197	PCIDevice *dev;
	198
	199	dev = pci_create_simple(bus, devfn, "piix3-ide-xen");
679f4f8b SS	200	pci_ide_create_devs(dev, hd_table);
	201	return dev;
	202	}
	203
f90c2bcd	204	static void pci_piix_ide_exitfn(PCIDevice *dev)
a9deb8c6 AK	205	{
	206	PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
	207	unsigned i;
	208
	209	for (i = 0; i < 2; ++i) {
	210	memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
	211	memory_region_destroy(&d->bmdma[i].extra_io);
	212	memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
	213	memory_region_destroy(&d->bmdma[i].addr_ioport);
	214	}
	215	memory_region_destroy(&d->bmdma_bar);
a9deb8c6 AK	216	}
a9deb8c6 AK	217
4c3df0ec JQ	218	/* hd_table must contain 4 block drivers */
4c3df0ec JQ	219	/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
57c88866	220	PCIDevice pci_piix3_ide_init(PCIBus bus, DriveInfo **hd_table, int devfn)
4c3df0ec JQ	221	{
	222	PCIDevice *dev;
	223
556cd098	224	dev = pci_create_simple(bus, devfn, "piix3-ide");
4c3df0ec	225	pci_ide_create_devs(dev, hd_table);
57c88866	226	return dev;
4c3df0ec JQ	227	}
	228
	229	/* hd_table must contain 4 block drivers */
	230	/* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
57c88866	231	PCIDevice pci_piix4_ide_init(PCIBus bus, DriveInfo **hd_table, int devfn)
4c3df0ec JQ	232	{
	233	PCIDevice *dev;
	234
556cd098	235	dev = pci_create_simple(bus, devfn, "piix4-ide");
4c3df0ec	236	pci_ide_create_devs(dev, hd_table);
57c88866	237	return dev;
4c3df0ec JQ	238	}
4c3df0ec JQ	239
40021f08 AL	240	static void piix3_ide_class_init(ObjectClass klass, void data)
40021f08 AL	241	{
39bffca2	242	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	243	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	244
	245	k->no_hotplug = 1;
	246	k->init = pci_piix_ide_initfn;
	247	k->exit = pci_piix_ide_exitfn;
	248	k->vendor_id = PCI_VENDOR_ID_INTEL;
	249	k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1;
	250	k->class_id = PCI_CLASS_STORAGE_IDE;
125ee0ed	251	set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
39bffca2	252	dc->no_user = 1;
40021f08 AL	253	}
40021f08 AL	254
8c43a6f0	255	static const TypeInfo piix3_ide_info = {
39bffca2 AL	256	.name = "piix3-ide",
	257	.parent = TYPE_PCI_DEVICE,
	258	.instance_size = sizeof(PCIIDEState),
	259	.class_init = piix3_ide_class_init,
e855761c AL	260	};
e855761c AL	261
40021f08 AL	262	static void piix3_ide_xen_class_init(ObjectClass klass, void data)
40021f08 AL	263	{
39bffca2	264	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	265	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	266
	267	k->init = pci_piix_ide_initfn;
	268	k->vendor_id = PCI_VENDOR_ID_INTEL;
	269	k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1;
	270	k->class_id = PCI_CLASS_STORAGE_IDE;
125ee0ed	271	set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
39bffca2 AL	272	dc->no_user = 1;
39bffca2 AL	273	dc->unplug = pci_piix3_xen_ide_unplug;
40021f08 AL	274	}
40021f08 AL	275
8c43a6f0	276	static const TypeInfo piix3_ide_xen_info = {
39bffca2 AL	277	.name = "piix3-ide-xen",
	278	.parent = TYPE_PCI_DEVICE,
	279	.instance_size = sizeof(PCIIDEState),
	280	.class_init = piix3_ide_xen_class_init,
e855761c AL	281	};
e855761c AL	282
40021f08 AL	283	static void piix4_ide_class_init(ObjectClass klass, void data)
40021f08 AL	284	{
39bffca2	285	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	286	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	287
	288	k->no_hotplug = 1;
	289	k->init = pci_piix_ide_initfn;
	290	k->exit = pci_piix_ide_exitfn;
	291	k->vendor_id = PCI_VENDOR_ID_INTEL;
	292	k->device_id = PCI_DEVICE_ID_INTEL_82371AB;
	293	k->class_id = PCI_CLASS_STORAGE_IDE;
125ee0ed	294	set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
39bffca2	295	dc->no_user = 1;
40021f08 AL	296	}
40021f08 AL	297
8c43a6f0	298	static const TypeInfo piix4_ide_info = {
39bffca2 AL	299	.name = "piix4-ide",
	300	.parent = TYPE_PCI_DEVICE,
	301	.instance_size = sizeof(PCIIDEState),
	302	.class_init = piix4_ide_class_init,
4c3df0ec JQ	303	};
4c3df0ec JQ	304
83f7d43a	305	static void piix_ide_register_types(void)
4c3df0ec	306	{
39bffca2 AL	307	type_register_static(&piix3_ide_info);
	308	type_register_static(&piix3_ide_xen_info);
	309	type_register_static(&piix4_ide_info);
4c3df0ec	310	}
83f7d43a AF	311
83f7d43a AF	312	type_init(piix_ide_register_types)