[qemu.git] / hw / arm / aspeed.c

/*
 * OpenPOWER Palmetto BMC
 *
 * Andrew Jeffery <[email protected]>
 *
 * Copyright 2016 IBM Corp.
 *
 * This code is licensed under the GPL version 2 or later.  See
 * the COPYING file in the top-level directory.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "cpu.h"
#include "exec/address-spaces.h"
#include "hw/arm/arm.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/boards.h"
#include "qemu/log.h"
#include "sysemu/block-backend.h"
#include "sysemu/blockdev.h"
#include "hw/loader.h"
#include "qemu/error-report.h"

static struct arm_boot_info aspeed_board_binfo = {
    .board_id = -1, /* device-tree-only board */
    .nb_cpus = 1,
};

typedef struct AspeedBoardState {
    AspeedSoCState soc;
    MemoryRegion ram;
} AspeedBoardState;

typedef struct AspeedBoardConfig {
    const char *soc_name;
    uint32_t hw_strap1;
    const char *fmc_model;
    const char *spi_model;
    uint32_t num_cs;
    void (*i2c_init)(AspeedBoardState *bmc);
} AspeedBoardConfig;

enum {
    PALMETTO_BMC,
    AST2500_EVB,
    ROMULUS_BMC,
};

/* Palmetto hardware value: 0x120CE416 */
#define PALMETTO_BMC_HW_STRAP1 (                                        \
        SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) |               \
        SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
        SCU_AST2400_HW_STRAP_ACPI_DIS |                                 \
        SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) |       \
        SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
        SCU_HW_STRAP_LPC_RESET_PIN |                                    \
        SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) |                \
        SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
        SCU_HW_STRAP_SPI_WIDTH |                                        \
        SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
        SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))

/* AST2500 evb hardware value: 0xF100C2E6 */
#define AST2500_EVB_HW_STRAP1 ((                                        \
        AST2500_HW_STRAP1_DEFAULTS |                                    \
        SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
        SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
        SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
        SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
        SCU_HW_STRAP_MAC1_RGMII |                                       \
        SCU_HW_STRAP_MAC0_RGMII) &                                      \
        ~SCU_HW_STRAP_2ND_BOOT_WDT)

/* Romulus hardware value: 0xF10AD206 */
#define ROMULUS_BMC_HW_STRAP1 (                                         \
        AST2500_HW_STRAP1_DEFAULTS |                                    \
        SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
        SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
        SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
        SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
        SCU_AST2500_HW_STRAP_ACPI_ENABLE |                              \
        SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))

static void palmetto_bmc_i2c_init(AspeedBoardState *bmc);
static void ast2500_evb_i2c_init(AspeedBoardState *bmc);

static const AspeedBoardConfig aspeed_boards[] = {
    [PALMETTO_BMC] = {
        .soc_name  = "ast2400-a1",
        .hw_strap1 = PALMETTO_BMC_HW_STRAP1,
        .fmc_model = "n25q256a",
        .spi_model = "mx25l25635e",
        .num_cs    = 1,
        .i2c_init  = palmetto_bmc_i2c_init,
    },
    [AST2500_EVB]  = {
        .soc_name  = "ast2500-a1",
        .hw_strap1 = AST2500_EVB_HW_STRAP1,
        .fmc_model = "n25q256a",
        .spi_model = "mx25l25635e",
        .num_cs    = 1,
        .i2c_init  = ast2500_evb_i2c_init,
    },
    [ROMULUS_BMC]  = {
        .soc_name  = "ast2500-a1",
        .hw_strap1 = ROMULUS_BMC_HW_STRAP1,
        .fmc_model = "n25q256a",
        .spi_model = "mx66l1g45g",
        .num_cs    = 2,
    },
};

#define FIRMWARE_ADDR 0x0

static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
                           Error **errp)
{
    BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
    uint8_t *storage;
    int64_t size;

    /* The block backend size should have already been 'validated' by
     * the creation of the m25p80 object.
     */
    size = blk_getlength(blk);
    if (size <= 0) {
        error_setg(errp, "failed to get flash size");
        return;
    }

    if (rom_size > size) {
        rom_size = size;
    }

    storage = g_new0(uint8_t, rom_size);
    if (blk_pread(blk, 0, storage, rom_size) < 0) {
        error_setg(errp, "failed to read the initial flash content");
        return;
    }

    rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
    g_free(storage);
}

static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
                                      Error **errp)
{
    int i ;

    for (i = 0; i < s->num_cs; ++i) {
        AspeedSMCFlash *fl = &s->flashes[i];
        DriveInfo *dinfo = drive_get_next(IF_MTD);
        qemu_irq cs_line;

        fl->flash = ssi_create_slave_no_init(s->spi, flashtype);
        if (dinfo) {
            qdev_prop_set_drive(fl->flash, "drive", blk_by_legacy_dinfo(dinfo),
                                errp);
        }
        qdev_init_nofail(fl->flash);

        cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0);
        sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
    }
}

static void aspeed_board_init(MachineState *machine,
                              const AspeedBoardConfig *cfg)
{
    AspeedBoardState *bmc;
    AspeedSoCClass *sc;
    DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);

    bmc = g_new0(AspeedBoardState, 1);
    object_initialize(&bmc->soc, (sizeof(bmc->soc)), cfg->soc_name);
    object_property_add_child(OBJECT(machine), "soc", OBJECT(&bmc->soc),
                              &error_abort);

    sc = ASPEED_SOC_GET_CLASS(&bmc->soc);

    object_property_set_int(OBJECT(&bmc->soc), ram_size, "ram-size",
                           &error_abort);
    object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap1, "hw-strap1",
                            &error_abort);
    object_property_set_int(OBJECT(&bmc->soc), cfg->num_cs, "num-cs",
                            &error_abort);
    object_property_set_bool(OBJECT(&bmc->soc), true, "realized",
                             &error_abort);

    /*
     * Allocate RAM after the memory controller has checked the size
     * was valid. If not, a default value is used.
     */
    ram_size = object_property_get_int(OBJECT(&bmc->soc), "ram-size",
                                       &error_abort);

    memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size);
    memory_region_add_subregion(get_system_memory(), sc->info->sdram_base,
                                &bmc->ram);
    object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),
                                   &error_abort);

    aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort);
    aspeed_board_init_flashes(&bmc->soc.spi[0], cfg->spi_model, &error_abort);

    /* Install first FMC flash content as a boot rom. */
    if (drive0) {
        AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0];
        MemoryRegion *boot_rom = g_new(MemoryRegion, 1);

        /*
         * create a ROM region using the default mapping window size of
         * the flash module. The window size is 64MB for the AST2400
         * SoC and 128MB for the AST2500 SoC, which is twice as big as
         * needed by the flash modules of the Aspeed machines.
         */
        memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom",
                               fl->size, &error_abort);
        memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
                                    boot_rom);
        write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort);
    }

    aspeed_board_binfo.kernel_filename = machine->kernel_filename;
    aspeed_board_binfo.initrd_filename = machine->initrd_filename;
    aspeed_board_binfo.kernel_cmdline = machine->kernel_cmdline;
    aspeed_board_binfo.ram_size = ram_size;
    aspeed_board_binfo.loader_start = sc->info->sdram_base;

    if (cfg->i2c_init) {
        cfg->i2c_init(bmc);
    }

    arm_load_kernel(ARM_CPU(first_cpu), &aspeed_board_binfo);
}

static void palmetto_bmc_i2c_init(AspeedBoardState *bmc)
{
    AspeedSoCState *soc = &bmc->soc;

    /* The palmetto platform expects a ds3231 RTC but a ds1338 is
     * enough to provide basic RTC features. Alarms will be missing */
    i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68);
}

static void palmetto_bmc_init(MachineState *machine)
{
    aspeed_board_init(machine, &aspeed_boards[PALMETTO_BMC]);
}

static void palmetto_bmc_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
    mc->init = palmetto_bmc_init;
    mc->max_cpus = 1;
    mc->no_sdcard = 1;
    mc->no_floppy = 1;
    mc->no_cdrom = 1;
    mc->no_parallel = 1;
}

static const TypeInfo palmetto_bmc_type = {
    .name = MACHINE_TYPE_NAME("palmetto-bmc"),
    .parent = TYPE_MACHINE,
    .class_init = palmetto_bmc_class_init,
};

static void ast2500_evb_i2c_init(AspeedBoardState *bmc)
{
    AspeedSoCState *soc = &bmc->soc;

    /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
    i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "tmp105", 0x4d);
}

static void ast2500_evb_init(MachineState *machine)
{
    aspeed_board_init(machine, &aspeed_boards[AST2500_EVB]);
}

static void ast2500_evb_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "Aspeed AST2500 EVB (ARM1176)";
    mc->init = ast2500_evb_init;
    mc->max_cpus = 1;
    mc->no_sdcard = 1;
    mc->no_floppy = 1;
    mc->no_cdrom = 1;
    mc->no_parallel = 1;
}

static const TypeInfo ast2500_evb_type = {
    .name = MACHINE_TYPE_NAME("ast2500-evb"),
    .parent = TYPE_MACHINE,
    .class_init = ast2500_evb_class_init,
};

static void romulus_bmc_init(MachineState *machine)
{
    aspeed_board_init(machine, &aspeed_boards[ROMULUS_BMC]);
}

static void romulus_bmc_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "OpenPOWER Romulus BMC (ARM1176)";
    mc->init = romulus_bmc_init;
    mc->max_cpus = 1;
    mc->no_sdcard = 1;
    mc->no_floppy = 1;
    mc->no_cdrom = 1;
    mc->no_parallel = 1;
}

static const TypeInfo romulus_bmc_type = {
    .name = MACHINE_TYPE_NAME("romulus-bmc"),
    .parent = TYPE_MACHINE,
    .class_init = romulus_bmc_class_init,
};

static void aspeed_machine_init(void)
{
    type_register_static(&palmetto_bmc_type);
    type_register_static(&ast2500_evb_type);
    type_register_static(&romulus_bmc_type);
}

type_init(aspeed_machine_init)
Commit	Line	Data
327d8e4e AJ	1	/*
	2	* OpenPOWER Palmetto BMC
	3	*
	4	* Andrew Jeffery <[email protected]>
	5	*
	6	* Copyright 2016 IBM Corp.
	7	*
	8	* This code is licensed under the GPL version 2 or later. See
	9	* the COPYING file in the top-level directory.
	10	*/
	11
	12	#include "qemu/osdep.h"
da34e65c	13	#include "qapi/error.h"
4771d756 PB	14	#include "qemu-common.h"
4771d756 PB	15	#include "cpu.h"
327d8e4e AJ	16	#include "exec/address-spaces.h"
327d8e4e AJ	17	#include "hw/arm/arm.h"
00442402	18	#include "hw/arm/aspeed_soc.h"
327d8e4e	19	#include "hw/boards.h"
03dd024f	20	#include "qemu/log.h"
e1ad9bc4 CLG	21	#include "sysemu/block-backend.h"
e1ad9bc4 CLG	22	#include "sysemu/blockdev.h"
d769a1da CLG	23	#include "hw/loader.h"
d769a1da CLG	24	#include "qemu/error-report.h"
327d8e4e	25
74fb1f38	26	static struct arm_boot_info aspeed_board_binfo = {
b033271f	27	.board_id = -1, /* device-tree-only board */
327d8e4e AJ	28	.nb_cpus = 1,
	29	};
	30
74fb1f38	31	typedef struct AspeedBoardState {
ff90606f	32	AspeedSoCState soc;
327d8e4e	33	MemoryRegion ram;
74fb1f38	34	} AspeedBoardState;
327d8e4e	35
c3ba99f7 CLG	36	typedef struct AspeedBoardConfig {
	37	const char *soc_name;
	38	uint32_t hw_strap1;
6a0e947b CLG	39	const char *fmc_model;
6a0e947b CLG	40	const char *spi_model;
26d5df95	41	uint32_t num_cs;
2cf6cb50	42	void (i2c_init)(AspeedBoardState bmc);
c3ba99f7 CLG	43	} AspeedBoardConfig;
	44
	45	enum {
	46	PALMETTO_BMC,
9a7c1750	47	AST2500_EVB,
ef17f836	48	ROMULUS_BMC,
c3ba99f7 CLG	49	};
c3ba99f7 CLG	50
ef17f836	51	/* Palmetto hardware value: 0x120CE416 */
8da33ef7 CLG	52	#define PALMETTO_BMC_HW_STRAP1 ( \
	53	SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) \| \
	54	SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) \| \
	55	SCU_AST2400_HW_STRAP_ACPI_DIS \| \
	56	SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) \| \
	57	SCU_HW_STRAP_VGA_CLASS_CODE \| \
	58	SCU_HW_STRAP_LPC_RESET_PIN \| \
	59	SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) \| \
	60	SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) \| \
	61	SCU_HW_STRAP_SPI_WIDTH \| \
	62	SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) \| \
	63	SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
	64
ef17f836	65	/* AST2500 evb hardware value: 0xF100C2E6 */
9a7c1750 CLG	66	#define AST2500_EVB_HW_STRAP1 (( \
	67	AST2500_HW_STRAP1_DEFAULTS \| \
	68	SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE \| \
	69	SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE \| \
	70	SCU_AST2500_HW_STRAP_UART_DEBUG \| \
	71	SCU_AST2500_HW_STRAP_DDR4_ENABLE \| \
	72	SCU_HW_STRAP_MAC1_RGMII \| \
	73	SCU_HW_STRAP_MAC0_RGMII) & \
	74	~SCU_HW_STRAP_2ND_BOOT_WDT)
	75
ef17f836 CLG	76	/* Romulus hardware value: 0xF10AD206 */
	77	#define ROMULUS_BMC_HW_STRAP1 ( \
	78	AST2500_HW_STRAP1_DEFAULTS \| \
	79	SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE \| \
	80	SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE \| \
	81	SCU_AST2500_HW_STRAP_UART_DEBUG \| \
	82	SCU_AST2500_HW_STRAP_DDR4_ENABLE \| \
	83	SCU_AST2500_HW_STRAP_ACPI_ENABLE \| \
	84	SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
	85
2cf6cb50 CLG	86	static void palmetto_bmc_i2c_init(AspeedBoardState *bmc);
	87	static void ast2500_evb_i2c_init(AspeedBoardState *bmc);
	88
c3ba99f7	89	static const AspeedBoardConfig aspeed_boards[] = {
6a0e947b	90	[PALMETTO_BMC] = {
bd407a21	91	.soc_name = "ast2400-a1",
6a0e947b CLG	92	.hw_strap1 = PALMETTO_BMC_HW_STRAP1,
	93	.fmc_model = "n25q256a",
	94	.spi_model = "mx25l25635e",
26d5df95	95	.num_cs = 1,
2cf6cb50	96	.i2c_init = palmetto_bmc_i2c_init,
6a0e947b CLG	97	},
	98	[AST2500_EVB] = {
	99	.soc_name = "ast2500-a1",
	100	.hw_strap1 = AST2500_EVB_HW_STRAP1,
	101	.fmc_model = "n25q256a",
	102	.spi_model = "mx25l25635e",
26d5df95	103	.num_cs = 1,
2cf6cb50	104	.i2c_init = ast2500_evb_i2c_init,
6a0e947b	105	},
ef17f836 CLG	106	[ROMULUS_BMC] = {
	107	.soc_name = "ast2500-a1",
	108	.hw_strap1 = ROMULUS_BMC_HW_STRAP1,
	109	.fmc_model = "n25q256a",
	110	.spi_model = "mx66l1g45g",
26d5df95	111	.num_cs = 2,
ef17f836	112	},
c3ba99f7 CLG	113	};
c3ba99f7 CLG	114
d769a1da CLG	115	#define FIRMWARE_ADDR 0x0
	116
	117	static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
	118	Error **errp)
	119	{
	120	BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
	121	uint8_t *storage;
0c7209be CLG	122	int64_t size;
	123
	124	/* The block backend size should have already been 'validated' by
	125	* the creation of the m25p80 object.
	126	*/
	127	size = blk_getlength(blk);
	128	if (size <= 0) {
	129	error_setg(errp, "failed to get flash size");
	130	return;
	131	}
d769a1da	132
0c7209be CLG	133	if (rom_size > size) {
0c7209be CLG	134	rom_size = size;
d769a1da CLG	135	}
	136
	137	storage = g_new0(uint8_t, rom_size);
	138	if (blk_pread(blk, 0, storage, rom_size) < 0) {
	139	error_setg(errp, "failed to read the initial flash content");
	140	return;
	141	}
	142
	143	rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
	144	g_free(storage);
	145	}
	146
74fb1f38	147	static void aspeed_board_init_flashes(AspeedSMCState s, const char flashtype,
e1ad9bc4 CLG	148	Error **errp)
	149	{
	150	int i ;
	151
	152	for (i = 0; i < s->num_cs; ++i) {
	153	AspeedSMCFlash *fl = &s->flashes[i];
	154	DriveInfo *dinfo = drive_get_next(IF_MTD);
	155	qemu_irq cs_line;
	156
e1ad9bc4 CLG	157	fl->flash = ssi_create_slave_no_init(s->spi, flashtype);
	158	if (dinfo) {
	159	qdev_prop_set_drive(fl->flash, "drive", blk_by_legacy_dinfo(dinfo),
	160	errp);
	161	}
	162	qdev_init_nofail(fl->flash);
	163
	164	cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0);
	165	sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
	166	}
	167	}
	168
c3ba99f7 CLG	169	static void aspeed_board_init(MachineState *machine,
c3ba99f7 CLG	170	const AspeedBoardConfig *cfg)
327d8e4e	171	{
74fb1f38	172	AspeedBoardState *bmc;
b033271f	173	AspeedSoCClass *sc;
d769a1da	174	DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
327d8e4e	175
74fb1f38	176	bmc = g_new0(AspeedBoardState, 1);
c3ba99f7	177	object_initialize(&bmc->soc, (sizeof(bmc->soc)), cfg->soc_name);
327d8e4e AJ	178	object_property_add_child(OBJECT(machine), "soc", OBJECT(&bmc->soc),
	179	&error_abort);
	180
b033271f CLG	181	sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
b033271f CLG	182
c6c7cfb0 CLG	183	object_property_set_int(OBJECT(&bmc->soc), ram_size, "ram-size",
c6c7cfb0 CLG	184	&error_abort);
c3ba99f7	185	object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap1, "hw-strap1",
87e79af0	186	&error_abort);
26d5df95 CLG	187	object_property_set_int(OBJECT(&bmc->soc), cfg->num_cs, "num-cs",
26d5df95 CLG	188	&error_abort);
327d8e4e AJ	189	object_property_set_bool(OBJECT(&bmc->soc), true, "realized",
	190	&error_abort);
	191
de46f5f4 CLG	192	/*
	193	* Allocate RAM after the memory controller has checked the size
	194	* was valid. If not, a default value is used.
	195	*/
	196	ram_size = object_property_get_int(OBJECT(&bmc->soc), "ram-size",
	197	&error_abort);
	198
	199	memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size);
	200	memory_region_add_subregion(get_system_memory(), sc->info->sdram_base,
	201	&bmc->ram);
	202	object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),
	203	&error_abort);
	204
6a0e947b CLG	205	aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort);
6a0e947b CLG	206	aspeed_board_init_flashes(&bmc->soc.spi[0], cfg->spi_model, &error_abort);
74fb1f38	207
d769a1da CLG	208	/* Install first FMC flash content as a boot rom. */
	209	if (drive0) {
	210	AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0];
	211	MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
	212
	213	/*
	214	* create a ROM region using the default mapping window size of
93bf276d CLG	215	* the flash module. The window size is 64MB for the AST2400
	216	* SoC and 128MB for the AST2500 SoC, which is twice as big as
	217	* needed by the flash modules of the Aspeed machines.
d769a1da CLG	218	*/
	219	memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom",
	220	fl->size, &error_abort);
	221	memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
	222	boot_rom);
	223	write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort);
	224	}
	225
74fb1f38 CLG	226	aspeed_board_binfo.kernel_filename = machine->kernel_filename;
	227	aspeed_board_binfo.initrd_filename = machine->initrd_filename;
	228	aspeed_board_binfo.kernel_cmdline = machine->kernel_cmdline;
	229	aspeed_board_binfo.ram_size = ram_size;
	230	aspeed_board_binfo.loader_start = sc->info->sdram_base;
e1ad9bc4	231
2cf6cb50 CLG	232	if (cfg->i2c_init) {
	233	cfg->i2c_init(bmc);
	234	}
	235
74fb1f38 CLG	236	arm_load_kernel(ARM_CPU(first_cpu), &aspeed_board_binfo);
74fb1f38 CLG	237	}
b033271f	238
2cf6cb50 CLG	239	static void palmetto_bmc_i2c_init(AspeedBoardState *bmc)
	240	{
	241	AspeedSoCState *soc = &bmc->soc;
	242
	243	/* The palmetto platform expects a ds3231 RTC but a ds1338 is
	244	* enough to provide basic RTC features. Alarms will be missing */
	245	i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68);
	246	}
	247
74fb1f38 CLG	248	static void palmetto_bmc_init(MachineState *machine)
74fb1f38 CLG	249	{
c3ba99f7	250	aspeed_board_init(machine, &aspeed_boards[PALMETTO_BMC]);
327d8e4e AJ	251	}
327d8e4e AJ	252
74fb1f38	253	static void palmetto_bmc_class_init(ObjectClass oc, void data)
327d8e4e	254	{
74fb1f38 CLG	255	MachineClass *mc = MACHINE_CLASS(oc);
	256
	257	mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
327d8e4e AJ	258	mc->init = palmetto_bmc_init;
	259	mc->max_cpus = 1;
	260	mc->no_sdcard = 1;
	261	mc->no_floppy = 1;
	262	mc->no_cdrom = 1;
327d8e4e AJ	263	mc->no_parallel = 1;
	264	}
	265
74fb1f38 CLG	266	static const TypeInfo palmetto_bmc_type = {
	267	.name = MACHINE_TYPE_NAME("palmetto-bmc"),
	268	.parent = TYPE_MACHINE,
	269	.class_init = palmetto_bmc_class_init,
	270	};
	271
2cf6cb50 CLG	272	static void ast2500_evb_i2c_init(AspeedBoardState *bmc)
	273	{
	274	AspeedSoCState *soc = &bmc->soc;
	275
	276	/* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
	277	i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "tmp105", 0x4d);
	278	}
	279
9a7c1750 CLG	280	static void ast2500_evb_init(MachineState *machine)
	281	{
	282	aspeed_board_init(machine, &aspeed_boards[AST2500_EVB]);
	283	}
	284
	285	static void ast2500_evb_class_init(ObjectClass oc, void data)
	286	{
	287	MachineClass *mc = MACHINE_CLASS(oc);
	288
	289	mc->desc = "Aspeed AST2500 EVB (ARM1176)";
	290	mc->init = ast2500_evb_init;
	291	mc->max_cpus = 1;
	292	mc->no_sdcard = 1;
	293	mc->no_floppy = 1;
	294	mc->no_cdrom = 1;
	295	mc->no_parallel = 1;
	296	}
	297
	298	static const TypeInfo ast2500_evb_type = {
	299	.name = MACHINE_TYPE_NAME("ast2500-evb"),
	300	.parent = TYPE_MACHINE,
	301	.class_init = ast2500_evb_class_init,
	302	};
	303
ef17f836 CLG	304	static void romulus_bmc_init(MachineState *machine)
	305	{
	306	aspeed_board_init(machine, &aspeed_boards[ROMULUS_BMC]);
	307	}
	308
	309	static void romulus_bmc_class_init(ObjectClass oc, void data)
	310	{
	311	MachineClass *mc = MACHINE_CLASS(oc);
	312
	313	mc->desc = "OpenPOWER Romulus BMC (ARM1176)";
	314	mc->init = romulus_bmc_init;
	315	mc->max_cpus = 1;
	316	mc->no_sdcard = 1;
	317	mc->no_floppy = 1;
	318	mc->no_cdrom = 1;
	319	mc->no_parallel = 1;
	320	}
	321
	322	static const TypeInfo romulus_bmc_type = {
	323	.name = MACHINE_TYPE_NAME("romulus-bmc"),
	324	.parent = TYPE_MACHINE,
	325	.class_init = romulus_bmc_class_init,
	326	};
	327
74fb1f38 CLG	328	static void aspeed_machine_init(void)
	329	{
	330	type_register_static(&palmetto_bmc_type);
9a7c1750	331	type_register_static(&ast2500_evb_type);
ef17f836	332	type_register_static(&romulus_bmc_type);
74fb1f38 CLG	333	}
	334
	335	type_init(aspeed_machine_init)