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d4abd567
BS		 1/*
2 * These files from binutils are concatenated:
3 * include/opcode/sparc.h, opcodes/sparc-opc.c, opcodes/sparc-dis.c
4 */
5
6/* include/opcode/sparc.h */
7
46f42f29
BS		 8/* Definitions for opcode table for the sparc.
9 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002,
10 2003, 2005 Free Software Foundation, Inc.
11
12 This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
13 the GNU Binutils.
14
15 GAS/GDB is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; either version 2, or (at your option)
18 any later version.
aa0aa4fa 19
46f42f29
BS		 20 GAS/GDB is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 GNU General Public License for more details.
aa0aa4fa 24
46f42f29 25 You should have received a copy of the GNU General Public License
8167ee88
BS		 26 along with GAS or GDB; see the file COPYING. If not,
27 see <http://www.gnu.org/licenses/>. */
aa0aa4fa 28
aa0aa4fa 29#include <stdlib.h>
76cad711 30#include "disas/bfd.h"
aa0aa4fa
FB		 31
32/* The SPARC opcode table (and other related data) is defined in
33 the opcodes library in sparc-opc.c. If you change anything here, make
34 sure you fix up that file, and vice versa. */
35
36 /* FIXME-someday: perhaps the ,a's and such should be embedded in the
37 instruction's name rather than the args. This would make gas faster, pinsn
38 slower, but would mess up some macros a bit. xoxorich. */
39
40/* List of instruction sets variations.
41 These values are such that each element is either a superset of a
42 preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P
43 returns non-zero.
44 The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
45 Don't change this without updating sparc-opc.c. */
46
46f42f29
BS		 47enum sparc_opcode_arch_val
48{
aa0aa4fa
FB		 49 SPARC_OPCODE_ARCH_V6 = 0,
50 SPARC_OPCODE_ARCH_V7,
51 SPARC_OPCODE_ARCH_V8,
52 SPARC_OPCODE_ARCH_SPARCLET,
53 SPARC_OPCODE_ARCH_SPARCLITE,
46f42f29 54 /* V9 variants must appear last. */
aa0aa4fa 55 SPARC_OPCODE_ARCH_V9,
46f42f29
BS		 56 SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions. */
57 SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions. */
58 SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */
aa0aa4fa
FB		 59};
60
61/* The highest architecture in the table. */
62#define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)
63
64/* Given an enum sparc_opcode_arch_val, return the bitmask to use in
65 insn encoding/decoding. */
66#define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch))
67
68/* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */
69#define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9)
70
71/* Table of cpu variants. */
72
46f42f29
BS		 73typedef struct sparc_opcode_arch
74{
aa0aa4fa
FB		 75 const char *name;
76 /* Mask of sparc_opcode_arch_val's supported.
77 EG: For v7 this would be
78 (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).
79 These are short's because sparc_opcode.architecture is. */
80 short supported;
46f42f29 81} sparc_opcode_arch;
aa0aa4fa 82
f82a3d48 83static const struct sparc_opcode_arch sparc_opcode_archs[];
aa0aa4fa 84
aa0aa4fa
FB		 85/* Return the bitmask of supported architectures for ARCH. */
86#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)
87
88/* Non-zero if ARCH1 conflicts with ARCH2.
89 IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */
90#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
46f42f29
BS		 91 (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
92 != SPARC_OPCODE_SUPPORTED (ARCH1)) \
93 && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
aa0aa4fa
FB		 94 != SPARC_OPCODE_SUPPORTED (ARCH2)))
95
96/* Structure of an opcode table entry. */
97
46f42f29
BS		 98typedef struct sparc_opcode
99{
aa0aa4fa 100 const char *name;
46f42f29
BS		 101 unsigned long match; /* Bits that must be set. */
102 unsigned long lose; /* Bits that must not be set. */
aa0aa4fa 103 const char *args;
46f42f29 104 /* This was called "delayed" in versions before the flags. */
aa0aa4fa 105 char flags;
f930d07e 106 short architecture; /* Bitmask of sparc_opcode_arch_val's. */
46f42f29
BS		 107} sparc_opcode;
108
109#define F_DELAYED 1 /* Delayed branch. */
110#define F_ALIAS 2 /* Alias for a "real" instruction. */
111#define F_UNBR 4 /* Unconditional branch. */
112#define F_CONDBR 8 /* Conditional branch. */
113#define F_JSR 16 /* Subroutine call. */
114#define F_FLOAT 32 /* Floating point instruction (not a branch). */
115#define F_FBR 64 /* Floating point branch. */
aa0aa4fa
FB		 116/* FIXME: Add F_ANACHRONISTIC flag for v9. */
117
46f42f29
BS		 118/* All sparc opcodes are 32 bits, except for the `set' instruction (really a
119 macro), which is 64 bits. It is handled as a special case.
aa0aa4fa 120
46f42f29
BS		 121 The match component is a mask saying which bits must match a particular
122 opcode in order for an instruction to be an instance of that opcode.
aa0aa4fa 123
46f42f29
BS		 124 The args component is a string containing one character for each operand of the
125 instruction.
aa0aa4fa 126
46f42f29 127 Kinds of operands:
f930d07e
BS		 128 # Number used by optimizer. It is ignored.
129 1 rs1 register.
130 2 rs2 register.
131 d rd register.
132 e frs1 floating point register.
133 v frs1 floating point register (double/even).
134 V frs1 floating point register (quad/multiple of 4).
135 f frs2 floating point register.
136 B frs2 floating point register (double/even).
137 R frs2 floating point register (quad/multiple of 4).
138 g frsd floating point register.
139 H frsd floating point register (double/even).
140 J frsd floating point register (quad/multiple of 4).
141 b crs1 coprocessor register
142 c crs2 coprocessor register
143 D crsd coprocessor register
144 m alternate space register (asr) in rd
145 M alternate space register (asr) in rs1
146 h 22 high bits.
147 X 5 bit unsigned immediate
148 Y 6 bit unsigned immediate
149 3 SIAM mode (3 bits). (v9b)
150 K MEMBAR mask (7 bits). (v9)
151 j 10 bit Immediate. (v9)
152 I 11 bit Immediate. (v9)
153 i 13 bit Immediate.
154 n 22 bit immediate.
155 k 2+14 bit PC relative immediate. (v9)
156 G 19 bit PC relative immediate. (v9)
157 l 22 bit PC relative immediate.
158 L 30 bit PC relative immediate.
159 a Annul. The annul bit is set.
160 A Alternate address space. Stored as 8 bits.
161 C Coprocessor state register.
162 F floating point state register.
163 p Processor state register.
164 N Branch predict clear ",pn" (v9)
165 T Branch predict set ",pt" (v9)
166 z %icc. (v9)
167 Z %xcc. (v9)
168 q Floating point queue.
169 r Single register that is both rs1 and rd.
170 O Single register that is both rs2 and rd.
171 Q Coprocessor queue.
172 S Special case.
173 t Trap base register.
174 w Window invalid mask register.
175 y Y register.
176 u sparclet coprocessor registers in rd position
177 U sparclet coprocessor registers in rs1 position
178 E %ccr. (v9)
179 s %fprs. (v9)
180 P %pc. (v9)
181 W %tick. (v9)
182 o %asi. (v9)
183 6 %fcc0. (v9)
184 7 %fcc1. (v9)
185 8 %fcc2. (v9)
186 9 %fcc3. (v9)
187 ! Privileged Register in rd (v9)
188 ? Privileged Register in rs1 (v9)
189 * Prefetch function constant. (v9)
190 x OPF field (v9 impdep).
191 0 32/64 bit immediate for set or setx (v9) insns
192 _ Ancillary state register in rd (v9a)
193 / Ancillary state register in rs1 (v9a)
aa0aa4fa 194
46f42f29
BS		 195 The following chars are unused: (note: ,[] are used as punctuation)
196 [45]. */
197
198#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */
199#define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */
200#define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */
201#define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */
202#define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */
203#define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */
204#define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */
205#define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */
206#define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */
207#define F1(x) (OP (x))
208#define DISP30(x) ((x) & 0x3fffffff)
209#define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */
210#define RS2(x) ((x) & 0x1f) /* Rs2 field. */
211#define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */
212#define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */
213#define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */
214#define ASI_RS2(x) (SIMM13 (x))
215#define MEMBAR(x) ((x) & 0x7f)
216#define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */
217
218#define ANNUL (1 << 29)
219#define BPRED (1 << 19) /* V9. */
220#define IMMED F3I (1)
221#define RD_G0 RD (~0)
222#define RS1_G0 RS1 (~0)
223#define RS2_G0 RS2 (~0)
aa0aa4fa 224
f82a3d48 225static const struct sparc_opcode sparc_opcodes[];
aa0aa4fa 226
46f42f29
BS		 227static const char *sparc_decode_asi_v8 (int);
228static const char *sparc_decode_asi_v9 (int);
229static const char *sparc_decode_membar (int);
230static const char *sparc_decode_prefetch (int);
231static const char *sparc_decode_sparclet_cpreg (int);
232
233/* Local Variables:
234 fill-column: 131
235 comment-column: 0
236 End: */
aa0aa4fa 237
d4abd567
BS		 238/* opcodes/sparc-opc.c */
239
46f42f29
BS		 240/* Table of opcodes for the sparc.
241 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
242 2000, 2002, 2004, 2005
243 Free Software Foundation, Inc.
244
245 This file is part of the BFD library.
246
247 BFD is free software; you can redistribute it and/or modify it under
248 the terms of the GNU General Public License as published by the Free
249 Software Foundation; either version 2, or (at your option) any later
250 version.
251
252 BFD is distributed in the hope that it will be useful, but WITHOUT ANY
253 WARRANTY; without even the implied warranty of MERCHANTABILITY or
254 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
255 for more details.
256
257 You should have received a copy of the GNU General Public License
8167ee88
BS		 258 along with this software; see the file COPYING. If not,
259 see <http://www.gnu.org/licenses/>. */
46f42f29
BS		 260
261/* FIXME-someday: perhaps the ,a's and such should be embedded in the
262 instruction's name rather than the args. This would make gas faster, pinsn
263 slower, but would mess up some macros a bit. xoxorich. */
264
aa0aa4fa 265/* Some defines to make life easy. */
f930d07e
BS		 266#define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6)
267#define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7)
268#define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)
269#define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET)
270#define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
271#define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)
272#define MASK_V9A SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)
273#define MASK_V9B SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B)
aa0aa4fa
FB		 274
275/* Bit masks of architectures supporting the insn. */
276
f930d07e
BS		 277#define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \
278 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
46f42f29 279/* v6 insns not supported on the sparclet. */
f930d07e
BS		 280#define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 \
281 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
282#define v7 (MASK_V7 | MASK_V8 | MASK_SPARCLET \
283 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
aa0aa4fa
FB		 284/* Although not all insns are implemented in hardware, sparclite is defined
285 to be a superset of v8. Unimplemented insns trap and are then theoretically
286 implemented in software.
287 It's not clear that the same is true for sparclet, although the docs
288 suggest it is. Rather than complicating things, the sparclet assembler
289 recognizes all v8 insns. */
f930d07e
BS		 290#define v8 (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE \
291 | MASK_V9 | MASK_V9A | MASK_V9B)
292#define sparclet (MASK_SPARCLET)
293#define sparclite (MASK_SPARCLITE)
294#define v9 (MASK_V9 | MASK_V9A | MASK_V9B)
295#define v9a (MASK_V9A | MASK_V9B)
296#define v9b (MASK_V9B)
46f42f29 297/* v6 insns not supported by v9. */
f930d07e
BS		 298#define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 \
299 | MASK_SPARCLET | MASK_SPARCLITE)
aa0aa4fa 300/* v9a instructions which would appear to be aliases to v9's impdep's
46f42f29 301 otherwise. */
f930d07e 302#define v9notv9a (MASK_V9)
aa0aa4fa
FB		 303
304/* Table of opcode architectures.
305 The order is defined in opcode/sparc.h. */
306
46f42f29
BS		 307static const struct sparc_opcode_arch sparc_opcode_archs[] =
308{
aa0aa4fa
FB		 309 { "v6", MASK_V6 },
310 { "v7", MASK_V6 | MASK_V7 },
311 { "v8", MASK_V6 | MASK_V7 | MASK_V8 },
312 { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET },
313 { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE },
7f75ffd3 314 /* ??? Don't some v8 privileged insns conflict with v9? */
aa0aa4fa
FB		 315 { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 },
316 /* v9 with ultrasparc additions */
317 { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A },
318 /* v9 with cheetah additions */
319 { "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B },
320 { NULL, 0 }
321};
322
aa0aa4fa 323/* Branch condition field. */
46f42f29 324#define COND(x) (((x) & 0xf) << 25)
aa0aa4fa
FB		 325
326/* v9: Move (MOVcc and FMOVcc) condition field. */
46f42f29 327#define MCOND(x,i_or_f) ((((i_or_f) & 1) << 18) | (((x) >> 11) & (0xf << 14))) /* v9 */
aa0aa4fa
FB		 328
329/* v9: Move register (MOVRcc and FMOVRcc) condition field. */
46f42f29
BS		 330#define RCOND(x) (((x) & 0x7) << 10) /* v9 */
331
332#define CONDA (COND (0x8))
333#define CONDCC (COND (0xd))
334#define CONDCS (COND (0x5))
335#define CONDE (COND (0x1))
336#define CONDG (COND (0xa))
337#define CONDGE (COND (0xb))
338#define CONDGU (COND (0xc))
339#define CONDL (COND (0x3))
340#define CONDLE (COND (0x2))
341#define CONDLEU (COND (0x4))
342#define CONDN (COND (0x0))
343#define CONDNE (COND (0x9))
344#define CONDNEG (COND (0x6))
345#define CONDPOS (COND (0xe))
346#define CONDVC (COND (0xf))
347#define CONDVS (COND (0x7))
f930d07e
BS		 348
349#define CONDNZ CONDNE
350#define CONDZ CONDE
351#define CONDGEU CONDCC
352#define CONDLU CONDCS
353
46f42f29
BS		 354#define FCONDA (COND (0x8))
355#define FCONDE (COND (0x9))
356#define FCONDG (COND (0x6))
357#define FCONDGE (COND (0xb))
358#define FCONDL (COND (0x4))
359#define FCONDLE (COND (0xd))
360#define FCONDLG (COND (0x2))
361#define FCONDN (COND (0x0))
362#define FCONDNE (COND (0x1))
363#define FCONDO (COND (0xf))
364#define FCONDU (COND (0x7))
365#define FCONDUE (COND (0xa))
366#define FCONDUG (COND (0x5))
367#define FCONDUGE (COND (0xc))
368#define FCONDUL (COND (0x3))
369#define FCONDULE (COND (0xe))
f930d07e
BS		 370
371#define FCONDNZ FCONDNE
372#define FCONDZ FCONDE
373
46f42f29
BS		 374#define ICC (0) /* v9 */
375#define XCC (1 << 12) /* v9 */
376#define FCC(x) (((x) & 0x3) << 11) /* v9 */
377#define FBFCC(x) (((x) & 0x3) << 20) /* v9 */
aa0aa4fa
FB		 378\f
379/* The order of the opcodes in the table is significant:
5fafdf24 380
f930d07e
BS		 381 * The assembler requires that all instances of the same mnemonic must
382 be consecutive. If they aren't, the assembler will bomb at runtime.
aa0aa4fa 383
46f42f29 384 * The disassembler should not care about the order of the opcodes. */
aa0aa4fa
FB		 385
386/* Entries for commutative arithmetic operations. */
387/* ??? More entries can make use of this. */
388#define COMMUTEOP(opcode, op3, arch_mask) \
f930d07e
BS		 389{ opcode, F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0), "1,2,d", 0, arch_mask }, \
390{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "1,i,d", 0, arch_mask }, \
391{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "i,1,d", 0, arch_mask }
aa0aa4fa 392
f82a3d48 393static const struct sparc_opcode sparc_opcodes[] = {
aa0aa4fa 394
f930d07e
BS		 395{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", 0, v6 },
396{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", 0, v6 }, /* ld [rs1+%g0],d */
397{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", 0, v6 },
398{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", 0, v6 },
399{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", 0, v6 },
400{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ld [rs1+0],d */
401{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g", 0, v6 },
402{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0, "[1],g", 0, v6 }, /* ld [rs1+%g0],d */
403{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[1+i],g", 0, v6 },
404{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[i+1],g", 0, v6 },
405{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0, "[i],g", 0, v6 },
406{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0), "[1],g", 0, v6 }, /* ld [rs1+0],d */
407
408{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0), "[1+2],F", 0, v6 },
409{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+%g0],d */
410{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[1+i],F", 0, v6 },
411{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[i+1],F", 0, v6 },
412{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, v6 },
413{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+0],d */
414
415{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2],D", 0, v6notv9 },
416{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1],D", 0, v6notv9 }, /* ld [rs1+%g0],d */
417{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i],D", 0, v6notv9 },
418{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1],D", 0, v6notv9 },
419{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i],D", 0, v6notv9 },
420{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ld [rs1+0],d */
421{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0), "[1+2],C", 0, v6notv9 },
422{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0, "[1],C", 0, v6notv9 }, /* ld [rs1+%g0],d */
423{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[1+i],C", 0, v6notv9 },
424{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[i+1],C", 0, v6notv9 },
425{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0, "[i],C", 0, v6notv9 },
426{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0), "[1],C", 0, v6notv9 }, /* ld [rs1+0],d */
aa0aa4fa
FB		 427
428/* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the
429 'ld' pseudo-op in v9. */
f930d07e
BS		 430{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", F_ALIAS, v9 },
431{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", F_ALIAS, v9 }, /* ld [rs1+%g0],d */
432{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", F_ALIAS, v9 },
433{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", F_ALIAS, v9 },
434{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", F_ALIAS, v9 },
435{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", F_ALIAS, v9 }, /* ld [rs1+0],d */
436
437{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", 0, v6 },
438{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldd [rs1+%g0],d */
439{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", 0, v6 },
440{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", 0, v6 },
441{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0, "[i],d", 0, v6 },
442{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldd [rs1+0],d */
443{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0), "[1+2],H", 0, v6 },
444{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0), "[1],H", 0, v6 }, /* ldd [rs1+%g0],d */
445{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[1+i],H", 0, v6 },
446{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[i+1],H", 0, v6 },
447{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0, "[i],H", 0, v6 },
448{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0), "[1],H", 0, v6 }, /* ldd [rs1+0],d */
449
450{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0), "[1+2],D", 0, v6notv9 },
451{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+%g0],d */
452{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i],D", 0, v6notv9 },
453{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1],D", 0, v6notv9 },
454{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i],D", 0, v6notv9 },
455{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+0],d */
456
457{ "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0), "[1+2],J", 0, v9 },
458{ "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0), "[1],J", 0, v9 }, /* ldd [rs1+%g0],d */
459{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[1+i],J", 0, v9 },
460{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[i+1],J", 0, v9 },
461{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0, "[i],J", 0, v9 },
462{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0), "[1],J", 0, v9 }, /* ldd [rs1+0],d */
463
464{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0), "[1+2],d", 0, v6 },
465{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsb [rs1+%g0],d */
466{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[1+i],d", 0, v6 },
467{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[i+1],d", 0, v6 },
468{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0, "[i],d", 0, v6 },
469{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsb [rs1+0],d */
470
471{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsh [rs1+%g0],d */
472{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0), "[1+2],d", 0, v6 },
473{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[1+i],d", 0, v6 },
474{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[i+1],d", 0, v6 },
475{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0, "[i],d", 0, v6 },
476{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsh [rs1+0],d */
477
478{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0), "[1+2],d", 0, v6 },
479{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldstub [rs1+%g0],d */
480{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[1+i],d", 0, v6 },
481{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[i+1],d", 0, v6 },
482{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0, "[i],d", 0, v6 },
483{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldstub [rs1+0],d */
484
485{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0), "[1+2],d", 0, v9 },
486{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldsw [rs1+%g0],d */
487{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[1+i],d", 0, v9 },
488{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[i+1],d", 0, v9 },
489{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0, "[i],d", 0, v9 },
490{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldsw [rs1+0],d */
491
492{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0), "[1+2],d", 0, v6 },
493{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldub [rs1+%g0],d */
494{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[1+i],d", 0, v6 },
495{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[i+1],d", 0, v6 },
496{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0, "[i],d", 0, v6 },
497{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldub [rs1+0],d */
498
499{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0), "[1+2],d", 0, v6 },
500{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* lduh [rs1+%g0],d */
501{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[1+i],d", 0, v6 },
502{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[i+1],d", 0, v6 },
503{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0, "[i],d", 0, v6 },
504{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* lduh [rs1+0],d */
505
506{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0), "[1+2],d", 0, v9 },
507{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldx [rs1+%g0],d */
508{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[1+i],d", 0, v9 },
509{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[i+1],d", 0, v9 },
510{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0, "[i],d", 0, v9 },
511{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldx [rs1+0],d */
512
513{ "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0, v9 },
514{ "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1), "[1],F", 0, v9 }, /* ld [rs1+%g0],d */
515{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0, v9 },
516{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0, v9 },
517{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1), "[i],F", 0, v9 },
518{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, v9 }, /* ld [rs1+0],d */
519
520{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", 0, v6 },
521{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lda [rs1+%g0],d */
522{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", 0, v9 },
523{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", 0, v9 },
524{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", 0, v9 },
525{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
526{ "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2]A,g", 0, v9 },
527{ "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1]A,g", 0, v9 }, /* lda [rs1+%g0],d */
528{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i]o,g", 0, v9 },
529{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1]o,g", 0, v9 },
530{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i]o,g", 0, v9 },
531{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1]o,g", 0, v9 }, /* ld [rs1+0],d */
532
533{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", 0, v6 },
534{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldda [rs1+%g0],d */
535{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", 0, v9 },
536{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", 0, v9 },
537{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0, "[i]o,d", 0, v9 },
538{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
539
540{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0), "[1+2]A,H", 0, v9 },
541{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0, "[1]A,H", 0, v9 }, /* ldda [rs1+%g0],d */
542{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i]o,H", 0, v9 },
543{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1]o,H", 0, v9 },
544{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i]o,H", 0, v9 },
545{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1]o,H", 0, v9 }, /* ld [rs1+0],d */
546
547{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0), "[1+2]A,J", 0, v9 },
548{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0, "[1]A,J", 0, v9 }, /* ldd [rs1+%g0],d */
549{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[1+i]o,J", 0, v9 },
550{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[i+1]o,J", 0, v9 },
551{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0, "[i]o,J", 0, v9 },
552{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0), "[1]o,J", 0, v9 }, /* ldd [rs1+0],d */
553
554{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0), "[1+2]A,d", 0, v6 },
555{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsba [rs1+%g0],d */
556{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[1+i]o,d", 0, v9 },
557{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[i+1]o,d", 0, v9 },
558{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0, "[i]o,d", 0, v9 },
559{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
560
561{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0), "[1+2]A,d", 0, v6 },
562{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsha [rs1+%g0],d */
563{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[1+i]o,d", 0, v9 },
564{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[i+1]o,d", 0, v9 },
565{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0, "[i]o,d", 0, v9 },
566{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
567
568{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0), "[1+2]A,d", 0, v6 },
569{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldstuba [rs1+%g0],d */
570{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[1+i]o,d", 0, v9 },
571{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[i+1]o,d", 0, v9 },
572{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0, "[i]o,d", 0, v9 },
573{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
574
575{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0), "[1+2]A,d", 0, v9 },
576{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */
577{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[1+i]o,d", 0, v9 },
578{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[i+1]o,d", 0, v9 },
579{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0, "[i]o,d", 0, v9 },
580{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
581
582{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0), "[1+2]A,d", 0, v6 },
583{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduba [rs1+%g0],d */
584{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[1+i]o,d", 0, v9 },
585{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[i+1]o,d", 0, v9 },
586{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0, "[i]o,d", 0, v9 },
587{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
588
589{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0), "[1+2]A,d", 0, v6 },
590{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduha [rs1+%g0],d */
591{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[1+i]o,d", 0, v9 },
592{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[i+1]o,d", 0, v9 },
593{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0, "[i]o,d", 0, v9 },
594{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
595
596{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", F_ALIAS, v9 }, /* lduwa === lda */
597{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", F_ALIAS, v9 }, /* lda [rs1+%g0],d */
598{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", F_ALIAS, v9 },
599{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", F_ALIAS, v9 },
600{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", F_ALIAS, v9 },
601{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS, v9 }, /* ld [rs1+0],d */
602
603{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0), "[1+2]A,d", 0, v9 },
604{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */
605{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[1+i]o,d", 0, v9 },
606{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[i+1]o,d", 0, v9 },
607{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0, "[i]o,d", 0, v9 },
608{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
609
610{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", 0, v6 },
611{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* st d,[rs1+%g0] */
612{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", 0, v6 },
613{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", 0, v6 },
614{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", 0, v6 },
615{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* st d,[rs1+0] */
616{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0), "g,[1+2]", 0, v6 },
617{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0), "g,[1]", 0, v6 }, /* st d[rs1+%g0] */
618{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[1+i]", 0, v6 },
619{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[i+1]", 0, v6 },
620{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0, "g,[i]", 0, v6 },
621{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0), "g,[1]", 0, v6 }, /* st d,[rs1+0] */
622
623{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 },
624{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */
625{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[1+i]", 0, v6notv9 },
626{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[i+1]", 0, v6notv9 },
627{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "D,[i]", 0, v6notv9 },
628{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+0] */
629{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0), "C,[1+2]", 0, v6notv9 },
630{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */
631{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[1+i]", 0, v6notv9 },
632{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[i+1]", 0, v6notv9 },
633{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0, "C,[i]", 0, v6notv9 },
634{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+0] */
635
636{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0), "F,[1+2]", 0, v6 },
637{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0), "F,[1]", 0, v6 }, /* st d,[rs1+%g0] */
638{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[1+i]", 0, v6 },
639{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[i+1]", 0, v6 },
640{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0, "F,[i]", 0, v6 },
641{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0), "F,[1]", 0, v6 }, /* st d,[rs1+0] */
642
643{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 },
644{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */
645{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 },
646{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 },
647{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 },
648{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */
649{ "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 },
650{ "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */
651{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 },
652{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 },
653{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 },
654{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */
655{ "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 },
656{ "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */
657{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 },
658{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 },
659{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 },
660{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */
661
662{ "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
663{ "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+%g0] */
664{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v6 },
665{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v6 },
666{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
667{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+0] */
668
669{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", 0, v6 },
670{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* sta d,[rs1+%g0] */
671{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", 0, v9 },
672{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", 0, v9 },
673{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", 0, v9 },
674{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* st d,[rs1+0] */
675
676{ "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0), "g,[1+2]A", 0, v9 },
677{ "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0), "g,[1]A", 0, v9 }, /* sta d,[rs1+%g0] */
678{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[1+i]o", 0, v9 },
679{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[i+1]o", 0, v9 },
680{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "g,[i]o", 0, v9 },
681{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "g,[1]o", 0, v9 }, /* st d,[rs1+0] */
682
683{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 },
684{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */
685{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 },
686{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 },
687{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
688{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */
689{ "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 },
690{ "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */
691{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 },
692{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 },
693{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
694{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */
695{ "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 },
696{ "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */
697{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 },
698{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 },
699{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
700{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */
701
702{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", 0, v6 },
703{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+%g0] */
704{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", 0, v6 },
705{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", 0, v6 },
706{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", 0, v6 },
707{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+0] */
708
709{ "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
710{ "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */
711{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v6 },
712{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v6 },
713{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
714{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */
715{ "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
716{ "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */
717{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v6 },
718{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v6 },
719{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
720{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */
721
722{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", 0, v6 },
723{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stba d,[rs1+%g0] */
724{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", 0, v9 },
725{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", 0, v9 },
726{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", 0, v9 },
727{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stb d,[rs1+0] */
728
729{ "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v6 },
730{ "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */
731{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, v9 },
732{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, v9 },
733{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
734{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */
735{ "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v6 },
736{ "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */
737{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, v9 },
738{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, v9 },
739{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
740{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */
741
742{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", 0, v6 },
743{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* std d,[rs1+%g0] */
744{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", 0, v6 },
745{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", 0, v6 },
746{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", 0, v6 },
747{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* std d,[rs1+0] */
748
749{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "q,[1+2]", 0, v6notv9 },
750{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */
751{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[1+i]", 0, v6notv9 },
752{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[i+1]", 0, v6notv9 },
753{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "q,[i]", 0, v6notv9 },
754{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */
755{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0), "H,[1+2]", 0, v6 },
756{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0), "H,[1]", 0, v6 }, /* std d,[rs1+%g0] */
757{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[1+i]", 0, v6 },
758{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[i+1]", 0, v6 },
759{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0, "H,[i]", 0, v6 },
760{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0), "H,[1]", 0, v6 }, /* std d,[rs1+0] */
761
762{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "Q,[1+2]", 0, v6notv9 },
763{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */
764{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[1+i]", 0, v6notv9 },
765{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[i+1]", 0, v6notv9 },
766{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "Q,[i]", 0, v6notv9 },
767{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */
768{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 },
769{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */
770{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[1+i]", 0, v6notv9 },
771{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[i+1]", 0, v6notv9 },
772{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "D,[i]", 0, v6notv9 },
773{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+0] */
774
775{ "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
776{ "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+%g0] */
777{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", F_ALIAS, v6 },
778{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", F_ALIAS, v6 },
779{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
780{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+0] */
781
782{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", 0, v6 },
783{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stda d,[rs1+%g0] */
784{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", 0, v9 },
785{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", 0, v9 },
786{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0, "d,[i]o", 0, v9 },
787{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* std d,[rs1+0] */
788{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0), "H,[1+2]A", 0, v9 },
789{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0), "H,[1]A", 0, v9 }, /* stda d,[rs1+%g0] */
790{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[1+i]o", 0, v9 },
791{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[i+1]o", 0, v9 },
792{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "H,[i]o", 0, v9 },
793{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "H,[1]o", 0, v9 }, /* std d,[rs1+0] */
794
795{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", 0, v6 },
796{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+%g0] */
797{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", 0, v6 },
798{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", 0, v6 },
799{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", 0, v6 },
800{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+0] */
801
802{ "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
803{ "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */
804{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v6 },
805{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v6 },
806{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
807{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */
808{ "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
809{ "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */
810{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v6 },
811{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v6 },
812{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
813{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */
814
815{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", 0, v6 },
816{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stha ,[rs1+%g0] */
817{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", 0, v9 },
818{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", 0, v9 },
819{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", 0, v9 },
820{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* sth d,[rs1+0] */
821
822{ "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v6 },
823{ "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */
824{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, v9 },
825{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, v9 },
826{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
827{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */
828{ "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v6 },
829{ "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */
830{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, v9 },
831{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, v9 },
832{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
833{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */
834
835{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0), "d,[1+2]", 0, v9 },
836{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+%g0] */
837{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[1+i]", 0, v9 },
838{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[i+1]", 0, v9 },
839{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0, "d,[i]", 0, v9 },
840{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+0] */
841
842{ "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]", 0, v9 },
843{ "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+%g0] */
844{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[1+i]", 0, v9 },
845{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[i+1]", 0, v9 },
846{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1), "F,[i]", 0, v9 },
847{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+0] */
848
849{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0), "d,[1+2]A", 0, v9 },
850{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0), "d,[1]A", 0, v9 }, /* stxa d,[rs1+%g0] */
851{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[1+i]o", 0, v9 },
852{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[i+1]o", 0, v9 },
853{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0, "d,[i]o", 0, v9 },
854{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stx d,[rs1+0] */
855
856{ "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "J,[1+2]", 0, v9 },
857{ "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "J,[1]", 0, v9 }, /* stq [rs1+%g0] */
858{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[1+i]", 0, v9 },
859{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[i+1]", 0, v9 },
860{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "J,[i]", 0, v9 },
861{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "J,[1]", 0, v9 }, /* stq [rs1+0] */
862
863{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "J,[1+2]A", 0, v9 },
864{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "J,[1]A", 0, v9 }, /* stqa [rs1+%g0] */
865{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[1+i]o", 0, v9 },
866{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[i+1]o", 0, v9 },
867{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "J,[i]o", 0, v9 },
868{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "J,[1]o", 0, v9 }, /* stqa [rs1+0] */
869
870{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0), "[1+2],d", 0, v7 },
871{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0), "[1],d", 0, v7 }, /* swap [rs1+%g0],d */
872{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[1+i],d", 0, v7 },
873{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[i+1],d", 0, v7 },
874{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0, "[i],d", 0, v7 },
875{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0), "[1],d", 0, v7 }, /* swap [rs1+0],d */
876
877{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0), "[1+2]A,d", 0, v7 },
878{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0), "[1]A,d", 0, v7 }, /* swapa [rs1+%g0],d */
879{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[1+i]o,d", 0, v9 },
880{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[i+1]o,d", 0, v9 },
881{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0, "[i]o,d", 0, v9 },
882{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* swap [rs1+0],d */
883
884{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0), "1,2,d", 0, v6 },
885{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v6 }, /* restore %g0,%g0,%g0 */
886{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1), "1,i,d", 0, v6 },
887{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0), "", 0, v6 }, /* restore %g0,0,%g0 */
888
889{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* rett rs1+rs2 */
890{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1,%g0 */
891{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* rett rs1+X */
892{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */
893{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */
894{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X */
895{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1+0 */
896
897{ "save", F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d", 0, v6 },
898{ "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "1,i,d", 0, v6 },
899{ "save", 0x81e00000, ~0x81e00000, "", F_ALIAS, v6 },
900
901{ "ret", F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %i7+8,%g0 */
aa0aa4fa
FB		 902{ "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %o7+8,%g0 */
903
f930d07e
BS		 904{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0), "1+2,d", F_JSR|F_DELAYED, v6 },
905{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,d */
906{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,d */
907{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0, "i,d", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,d */
908{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "1+i,d", F_JSR|F_DELAYED, v6 },
909{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "i+1,d", F_JSR|F_DELAYED, v6 },
910
911{ "done", F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 },
912{ "retry", F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 },
913{ "saved", F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 },
914{ "restored", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 },
46f42f29
BS		 915{ "allclean", F3(2, 0x31, 0)|RD(2), F3(~2, ~0x31, ~0)|RD(~2)|RS1_G0|SIMM13(~0), "", 0, v9 },
916{ "otherw", F3(2, 0x31, 0)|RD(3), F3(~2, ~0x31, ~0)|RD(~3)|RS1_G0|SIMM13(~0), "", 0, v9 },
917{ "normalw", F3(2, 0x31, 0)|RD(4), F3(~2, ~0x31, ~0)|RD(~4)|RS1_G0|SIMM13(~0), "", 0, v9 },
918{ "invalw", F3(2, 0x31, 0)|RD(5), F3(~2, ~0x31, ~0)|RD(~5)|RS1_G0|SIMM13(~0), "", 0, v9 },
f930d07e
BS		 919{ "sir", F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0, "i", 0, v9 },
920
921{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", 0, v8 },
922{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", 0, v8 }, /* flush rs1+%g0 */
923{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", 0, v8 }, /* flush rs1+0 */
924{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", 0, v8 }, /* flush %g0+i */
925{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", 0, v8 },
926{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", 0, v8 },
aa0aa4fa
FB		 927
928/* IFLUSH was renamed to FLUSH in v8. */
f930d07e
BS		 929{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, v6 },
930{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS, v6 }, /* flush rs1+%g0 */
931{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, v6 }, /* flush rs1+0 */
932{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, v6 },
933{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS, v6 },
934{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS, v6 },
935
936{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0), "1+2", 0, v9 },
937{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0), "1", 0, v9 }, /* return rs1+%g0 */
938{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0), "1", 0, v9 }, /* return rs1+0 */
939{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0, "i", 0, v9 }, /* return %g0+i */
940{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "1+i", 0, v9 },
941{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "i+1", 0, v9 },
942
943{ "flushw", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v9 },
944
945{ "membar", F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K", 0, v9 },
946{ "stbar", F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, v8 },
947
948{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0), "[1+2],*", 0, v9 },
949{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0, "[1],*", 0, v9 }, /* prefetch [rs1+%g0],prefetch_fcn */
950{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[1+i],*", 0, v9 },
951{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[i+1],*", 0, v9 },
952{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0, "[i],*", 0, v9 },
953{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0), "[1],*", 0, v9 }, /* prefetch [rs1+0],prefetch_fcn */
954{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0), "[1+2]A,*", 0, v9 },
955{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0, "[1]A,*", 0, v9 }, /* prefetcha [rs1+%g0],prefetch_fcn */
956{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[1+i]o,*", 0, v9 },
957{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[i+1]o,*", 0, v9 },
958{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0, "[i]o,*", 0, v9 },
959{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0), "[1]o,*", 0, v9 }, /* prefetcha [rs1+0],d */
960
961{ "sll", F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 },
962{ "sll", F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 },
963{ "sra", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 },
964{ "sra", F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 },
965{ "srl", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 },
966{ "srl", F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 },
967
968{ "sllx", F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5), "1,2,d", 0, v9 },
969{ "sllx", F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6), "1,Y,d", 0, v9 },
970{ "srax", F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5), "1,2,d", 0, v9 },
971{ "srax", F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6), "1,Y,d", 0, v9 },
972{ "srlx", F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5), "1,2,d", 0, v9 },
973{ "srlx", F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6), "1,Y,d", 0, v9 },
974
975{ "mulscc", F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0), "1,2,d", 0, v6 },
976{ "mulscc", F3(2, 0x24, 1), F3(~2, ~0x24, ~1), "1,i,d", 0, v6 },
977
978{ "divscc", F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0), "1,2,d", 0, sparclite },
979{ "divscc", F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1), "1,i,d", 0, sparclite },
980
981{ "scan", F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0), "1,2,d", 0, sparclet|sparclite },
982{ "scan", F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1), "1,i,d", 0, sparclet|sparclite },
983
984{ "popc", F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0|ASI(~0),"2,d", 0, v9 },
985{ "popc", F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0, "i,d", 0, v9 },
986
987{ "clr", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "d", F_ALIAS, v6 }, /* or %g0,%g0,d */
988{ "clr", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0), "d", F_ALIAS, v6 }, /* or %g0,0,d */
989{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 },
990{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+%g0] */
991{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 },
992{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 },
993{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 },
994{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+0] */
995
996{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 },
997{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+%g0] */
998{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 },
999{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 },
1000{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 },
1001{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+0] */
1002
1003{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 },
1004{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+%g0] */
1005{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 },
1006{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 },
1007{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 },
1008{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+0] */
1009
1010{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v9 },
1011{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+%g0] */
1012{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[1+i]", F_ALIAS, v9 },
1013{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[i+1]", F_ALIAS, v9 },
1014{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v9 },
1015{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+0] */
1016
1017{ "orcc", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0), "1,2,d", 0, v6 },
1018{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "1,i,d", 0, v6 },
1019{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "i,1,d", 0, v6 },
aa0aa4fa
FB		 1020
1021/* This is not a commutative instruction. */
f930d07e
BS		 1022{ "orncc", F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0), "1,2,d", 0, v6 },
1023{ "orncc", F3(2, 0x16, 1), F3(~2, ~0x16, ~1), "1,i,d", 0, v6 },
aa0aa4fa
FB		 1024
1025/* This is not a commutative instruction. */
f930d07e
BS		 1026{ "orn", F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0), "1,2,d", 0, v6 },
1027{ "orn", F3(2, 0x06, 1), F3(~2, ~0x06, ~1), "1,i,d", 0, v6 },
1028
1029{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0), "1", 0, v6 }, /* orcc rs1, %g0, %g0 */
1030{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0), "2", 0, v6 }, /* orcc %g0, rs2, %g0 */
1031{ "tst", F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0), "1", 0, v6 }, /* orcc rs1, 0, %g0 */
1032
1033{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, v8 }, /* wr r,r,%asrX */
1034{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", 0, v8 }, /* wr r,i,%asrX */
1035{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */
1036{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", 0, v6 }, /* wr r,r,%y */
1037{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", 0, v6 }, /* wr r,i,%y */
1038{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */
1039{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", 0, v6notv9 }, /* wr r,r,%psr */
1040{ "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", 0, v6notv9 }, /* wr r,i,%psr */
1041{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */
1042{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", 0, v6notv9 }, /* wr r,r,%wim */
1043{ "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", 0, v6notv9 }, /* wr r,i,%wim */
1044{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */
1045{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", 0, v6notv9 }, /* wr r,r,%tbr */
1046{ "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", 0, v6notv9 }, /* wr r,i,%tbr */
1047{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */
1048
1049{ "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, v9 }, /* wr r,r,%ccr */
1050{ "wr", F3(2, 0x30, 1)|RD(2), F3(~2, ~0x30, ~1)|RD(~2), "1,i,E", 0, v9 }, /* wr r,i,%ccr */
1051{ "wr", F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,o", 0, v9 }, /* wr r,r,%asi */
1052{ "wr", F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3), "1,i,o", 0, v9 }, /* wr r,i,%asi */
1053{ "wr", F3(2, 0x30, 0)|RD(6), F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0), "1,2,s", 0, v9 }, /* wr r,r,%fprs */
1054{ "wr", F3(2, 0x30, 1)|RD(6), F3(~2, ~0x30, ~1)|RD(~6), "1,i,s", 0, v9 }, /* wr r,i,%fprs */
1055
1056{ "wr", F3(2, 0x30, 0)|RD(16), F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pcr */
1057{ "wr", F3(2, 0x30, 1)|RD(16), F3(~2, ~0x30, ~1)|RD(~16), "1,i,_", 0, v9a }, /* wr r,i,%pcr */
1058{ "wr", F3(2, 0x30, 0)|RD(17), F3(~2, ~0x30, ~0)|RD(~17)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pic */
1059{ "wr", F3(2, 0x30, 1)|RD(17), F3(~2, ~0x30, ~1)|RD(~17), "1,i,_", 0, v9a }, /* wr r,i,%pic */
1060{ "wr", F3(2, 0x30, 0)|RD(18), F3(~2, ~0x30, ~0)|RD(~18)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%dcr */
1061{ "wr", F3(2, 0x30, 1)|RD(18), F3(~2, ~0x30, ~1)|RD(~18), "1,i,_", 0, v9a }, /* wr r,i,%dcr */
1062{ "wr", F3(2, 0x30, 0)|RD(19), F3(~2, ~0x30, ~0)|RD(~19)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%gsr */
1063{ "wr", F3(2, 0x30, 1)|RD(19), F3(~2, ~0x30, ~1)|RD(~19), "1,i,_", 0, v9a }, /* wr r,i,%gsr */
1064{ "wr", F3(2, 0x30, 0)|RD(20), F3(~2, ~0x30, ~0)|RD(~20)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%set_softint */
1065{ "wr", F3(2, 0x30, 1)|RD(20), F3(~2, ~0x30, ~1)|RD(~20), "1,i,_", 0, v9a }, /* wr r,i,%set_softint */
1066{ "wr", F3(2, 0x30, 0)|RD(21), F3(~2, ~0x30, ~0)|RD(~21)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%clear_softint */
1067{ "wr", F3(2, 0x30, 1)|RD(21), F3(~2, ~0x30, ~1)|RD(~21), "1,i,_", 0, v9a }, /* wr r,i,%clear_softint */
1068{ "wr", F3(2, 0x30, 0)|RD(22), F3(~2, ~0x30, ~0)|RD(~22)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%softint */
1069{ "wr", F3(2, 0x30, 1)|RD(22), F3(~2, ~0x30, ~1)|RD(~22), "1,i,_", 0, v9a }, /* wr r,i,%softint */
1070{ "wr", F3(2, 0x30, 0)|RD(23), F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%tick_cmpr */
1071{ "wr", F3(2, 0x30, 1)|RD(23), F3(~2, ~0x30, ~1)|RD(~23), "1,i,_", 0, v9a }, /* wr r,i,%tick_cmpr */
1072{ "wr", F3(2, 0x30, 0)|RD(24), F3(~2, ~0x30, ~0)|RD(~24)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick */
1073{ "wr", F3(2, 0x30, 1)|RD(24), F3(~2, ~0x30, ~1)|RD(~24), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick */
1074{ "wr", F3(2, 0x30, 0)|RD(25), F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick_cmpr */
1075{ "wr", F3(2, 0x30, 1)|RD(25), F3(~2, ~0x30, ~1)|RD(~25), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick_cmpr */
1076
1077{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", 0, v8 }, /* rd %asrX,r */
1078{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", 0, v6 }, /* rd %y,r */
1079{ "rd", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", 0, v6notv9 }, /* rd %psr,r */
1080{ "rd", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", 0, v6notv9 }, /* rd %wim,r */
1081{ "rd", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", 0, v6notv9 }, /* rd %tbr,r */
1082
1083{ "rd", F3(2, 0x28, 0)|RS1(2), F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0), "E,d", 0, v9 }, /* rd %ccr,r */
1084{ "rd", F3(2, 0x28, 0)|RS1(3), F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0), "o,d", 0, v9 }, /* rd %asi,r */
1085{ "rd", F3(2, 0x28, 0)|RS1(4), F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0), "W,d", 0, v9 }, /* rd %tick,r */
1086{ "rd", F3(2, 0x28, 0)|RS1(5), F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0), "P,d", 0, v9 }, /* rd %pc,r */
1087{ "rd", F3(2, 0x28, 0)|RS1(6), F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0), "s,d", 0, v9 }, /* rd %fprs,r */
1088
1089{ "rd", F3(2, 0x28, 0)|RS1(16), F3(~2, ~0x28, ~0)|RS1(~16)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pcr,r */
1090{ "rd", F3(2, 0x28, 0)|RS1(17), F3(~2, ~0x28, ~0)|RS1(~17)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pic,r */
1091{ "rd", F3(2, 0x28, 0)|RS1(18), F3(~2, ~0x28, ~0)|RS1(~18)|SIMM13(~0), "/,d", 0, v9a }, /* rd %dcr,r */
1092{ "rd", F3(2, 0x28, 0)|RS1(19), F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0), "/,d", 0, v9a }, /* rd %gsr,r */
1093{ "rd", F3(2, 0x28, 0)|RS1(22), F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0), "/,d", 0, v9a }, /* rd %softint,r */
1094{ "rd", F3(2, 0x28, 0)|RS1(23), F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0), "/,d", 0, v9a }, /* rd %tick_cmpr,r */
1095{ "rd", F3(2, 0x28, 0)|RS1(24), F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick,r */
1096{ "rd", F3(2, 0x28, 0)|RS1(25), F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick_cmpr,r */
1097
1098{ "rdpr", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|SIMM13(~0), "?,d", 0, v9 }, /* rdpr %priv,r */
1099{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0), "1,2,!", 0, v9 }, /* wrpr r1,r2,%priv */
1100{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|SIMM13(~0), "1,!", 0, v9 }, /* wrpr r1,%priv */
1101{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "1,i,!", 0, v9 }, /* wrpr r1,i,%priv */
1102{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "i,1,!", F_ALIAS, v9 }, /* wrpr i,r1,%priv */
1103{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RS1(~0), "i,!", 0, v9 }, /* wrpr i,%priv */
aa0aa4fa 1104
46f42f29
BS		 1105{ "rdhpr", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|SIMM13(~0), "$,d", 0, v9 }, /* rdhpr %hpriv,r */
1106{ "wrhpr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0), "1,2,%", 0, v9 }, /* wrhpr r1,r2,%hpriv */
1107{ "wrhpr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|SIMM13(~0), "1,%", 0, v9 }, /* wrhpr r1,%hpriv */
1108{ "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1), "1,i,%", 0, v9 }, /* wrhpr r1,i,%hpriv */
1109{ "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1), "i,1,%", F_ALIAS, v9 }, /* wrhpr i,r1,%hpriv */
1110{ "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RS1(~0), "i,%", 0, v9 }, /* wrhpr i,%hpriv */
1111
aa0aa4fa 1112/* ??? This group seems wrong. A three operand move? */
f930d07e
BS		 1113{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", F_ALIAS, v8 }, /* wr r,r,%asrX */
1114{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", F_ALIAS, v8 }, /* wr r,i,%asrX */
1115{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", F_ALIAS, v6 }, /* wr r,r,%y */
1116{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", F_ALIAS, v6 }, /* wr r,i,%y */
1117{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", F_ALIAS, v6notv9 }, /* wr r,r,%psr */
1118{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", F_ALIAS, v6notv9 }, /* wr r,i,%psr */
1119{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", F_ALIAS, v6notv9 }, /* wr r,r,%wim */
1120{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", F_ALIAS, v6notv9 }, /* wr r,i,%wim */
1121{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", F_ALIAS, v6notv9 }, /* wr r,r,%tbr */
1122{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", F_ALIAS, v6notv9 }, /* wr r,i,%tbr */
1123
1124{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", F_ALIAS, v8 }, /* rd %asr1,r */
1125{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", F_ALIAS, v6 }, /* rd %y,r */
1126{ "mov", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", F_ALIAS, v6notv9 }, /* rd %psr,r */
1127{ "mov", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", F_ALIAS, v6notv9 }, /* rd %wim,r */
1128{ "mov", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", F_ALIAS, v6notv9 }, /* rd %tbr,r */
1129
1130{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */
1131{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "i,m", F_ALIAS, v8 }, /* wr %g0,i,%asrX */
1132{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,0,%asrX */
1133{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */
1134{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "i,y", F_ALIAS, v6 }, /* wr %g0,i,%y */
1135{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,0,%y */
1136{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */
1137{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "i,p", F_ALIAS, v6notv9 }, /* wr %g0,i,%psr */
1138{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,0,%psr */
1139{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */
1140{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "i,w", F_ALIAS, v6notv9 }, /* wr %g0,i,%wim */
1141{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,0,%wim */
1142{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */
1143{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "i,t", F_ALIAS, v6notv9 }, /* wr %g0,i,%tbr */
1144{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,0,%tbr */
1145
1146{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0), "2,d", 0, v6 }, /* or %g0,rs2,d */
1147{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0, "i,d", 0, v6 }, /* or %g0,i,d */
1148{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0), "1,d", 0, v6 }, /* or rs1,%g0,d */
1149{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0), "1,d", 0, v6 }, /* or rs1,0,d */
1150
1151{ "or", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "1,2,d", 0, v6 },
1152{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "1,i,d", 0, v6 },
1153{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,1,d", 0, v6 },
1154
1155{ "bset", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* or rd,rs2,rd */
1156{ "bset", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,r", F_ALIAS, v6 }, /* or rd,i,rd */
aa0aa4fa
FB		 1157
1158/* This is not a commutative instruction. */
f930d07e
BS		 1159{ "andn", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "1,2,d", 0, v6 },
1160{ "andn", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "1,i,d", 0, v6 },
aa0aa4fa
FB		 1161
1162/* This is not a commutative instruction. */
f930d07e
BS		 1163{ "andncc", F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0), "1,2,d", 0, v6 },
1164{ "andncc", F3(2, 0x15, 1), F3(~2, ~0x15, ~1), "1,i,d", 0, v6 },
1165
1166{ "bclr", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* andn rd,rs2,rd */
1167{ "bclr", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "i,r", F_ALIAS, v6 }, /* andn rd,i,rd */
1168
1169{ "cmp", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0), "1,2", 0, v6 }, /* subcc rs1,rs2,%g0 */
1170{ "cmp", F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0, "1,i", 0, v6 }, /* subcc rs1,i,%g0 */
1171
1172{ "sub", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0), "1,2,d", 0, v6 },
1173{ "sub", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "1,i,d", 0, v6 },
1174
1175{ "subcc", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0), "1,2,d", 0, v6 },
1176{ "subcc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "1,i,d", 0, v6 },
1177
c470b663
RH		 1178{ "subc", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v6 },
1179{ "subc", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v6 },
f930d07e 1180
c470b663
RH		 1181{ "subccc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v6 },
1182{ "subccc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v6 },
f930d07e
BS		 1183
1184{ "and", F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0), "1,2,d", 0, v6 },
1185{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "1,i,d", 0, v6 },
1186{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "i,1,d", 0, v6 },
1187
1188{ "andcc", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0), "1,2,d", 0, v6 },
1189{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "1,i,d", 0, v6 },
1190{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "i,1,d", 0, v6 },
1191
1192{ "dec", F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* sub rd,1,rd */
1193{ "dec", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "i,r", F_ALIAS, v8 }, /* sub rd,imm,rd */
1194{ "deccc", F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* subcc rd,1,rd */
1195{ "deccc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "i,r", F_ALIAS, v8 }, /* subcc rd,imm,rd */
1196{ "inc", F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* add rd,1,rd */
1197{ "inc", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,r", F_ALIAS, v8 }, /* add rd,imm,rd */
1198{ "inccc", F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* addcc rd,1,rd */
1199{ "inccc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,r", F_ALIAS, v8 }, /* addcc rd,imm,rd */
1200
1201{ "btst", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, v6 }, /* andcc rs1,rs2,%g0 */
1202{ "btst", F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, v6 }, /* andcc rs1,i,%g0 */
1203
1204{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, v6 }, /* sub %g0,rs2,rd */
1205{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "O", F_ALIAS, v6 }, /* sub %g0,rd,rd */
1206
1207{ "add", F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0), "1,2,d", 0, v6 },
1208{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "1,i,d", 0, v6 },
1209{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,1,d", 0, v6 },
1210{ "addcc", F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0), "1,2,d", 0, v6 },
1211{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "1,i,d", 0, v6 },
1212{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,1,d", 0, v6 },
1213
c470b663
RH		 1214{ "addc", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v6 },
1215{ "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v6 },
1216{ "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v6 },
1217
1218{ "addccc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v6 },
1219{ "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v6 },
1220{ "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v6 },
f930d07e
BS		 1221
1222{ "smul", F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0), "1,2,d", 0, v8 },
1223{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "1,i,d", 0, v8 },
1224{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "i,1,d", 0, v8 },
1225{ "smulcc", F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0), "1,2,d", 0, v8 },
1226{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "1,i,d", 0, v8 },
1227{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "i,1,d", 0, v8 },
1228{ "umul", F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0), "1,2,d", 0, v8 },
1229{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "1,i,d", 0, v8 },
1230{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "i,1,d", 0, v8 },
1231{ "umulcc", F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0), "1,2,d", 0, v8 },
1232{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "1,i,d", 0, v8 },
1233{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "i,1,d", 0, v8 },
1234{ "sdiv", F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0), "1,2,d", 0, v8 },
1235{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "1,i,d", 0, v8 },
1236{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "i,1,d", 0, v8 },
1237{ "sdivcc", F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0), "1,2,d", 0, v8 },
1238{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "1,i,d", 0, v8 },
1239{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "i,1,d", 0, v8 },
1240{ "udiv", F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0), "1,2,d", 0, v8 },
1241{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "1,i,d", 0, v8 },
1242{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "i,1,d", 0, v8 },
1243{ "udivcc", F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0), "1,2,d", 0, v8 },
1244{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "1,i,d", 0, v8 },
1245{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "i,1,d", 0, v8 },
1246
1247{ "mulx", F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0), "1,2,d", 0, v9 },
1248{ "mulx", F3(2, 0x09, 1), F3(~2, ~0x09, ~1), "1,i,d", 0, v9 },
1249{ "sdivx", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, v9 },
1250{ "sdivx", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, v9 },
1251{ "udivx", F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0), "1,2,d", 0, v9 },
1252{ "udivx", F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1), "1,i,d", 0, v9 },
1253
1254{ "call", F1(0x1), F1(~0x1), "L", F_JSR|F_DELAYED, v6 },
1255{ "call", F1(0x1), F1(~0x1), "L,#", F_JSR|F_DELAYED, v6 },
1256
1257{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%o7 */
1258{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2,#", F_JSR|F_DELAYED, v6 },
1259{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%o7 */
1260{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#", F_JSR|F_DELAYED, v6 },
1261{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+i,%o7 */
1262{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i,#", F_JSR|F_DELAYED, v6 },
1263{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1", F_JSR|F_DELAYED, v6 }, /* jmpl i+rs1,%o7 */
1264{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1,#", F_JSR|F_DELAYED, v6 },
1265{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,%o7 */
1266{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i,#", F_JSR|F_DELAYED, v6 },
1267{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,%o7 */
1268{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1,#", F_JSR|F_DELAYED, v6 },
aa0aa4fa
FB		 1269
1270
1271/* Conditional instructions.
1272
1273 Because this part of the table was such a mess earlier, I have
1274 macrofied it so that all the branches and traps are generated from
1275 a single-line description of each condition value. John Gilmore. */
1276
1277/* Define branches -- one annulled, one without, etc. */
1278#define br(opcode, mask, lose, flags) \
1279 { opcode, (mask)|ANNUL, (lose), ",a l", (flags), v6 }, \
1280 { opcode, (mask) , (lose)|ANNUL, "l", (flags), v6 }
1281
1282#define brx(opcode, mask, lose, flags) /* v9 */ \
1283 { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), "Z,G", (flags), v9 }, \
1284 { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), ",T Z,G", (flags), v9 }, \
1285 { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a Z,G", (flags), v9 }, \
1286 { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a,T Z,G", (flags), v9 }, \
1287 { opcode, (mask)|(2<<20), ANNUL|BPRED|(lose), ",N Z,G", (flags), v9 }, \
1288 { opcode, (mask)|(2<<20)|ANNUL, BPRED|(lose), ",a,N Z,G", (flags), v9 }, \
1289 { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), "z,G", (flags), v9 }, \
1290 { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), ",T z,G", (flags), v9 }, \
1291 { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a z,G", (flags), v9 }, \
1292 { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a,T z,G", (flags), v9 }, \
1293 { opcode, (mask), ANNUL|BPRED|(lose)|(2<<20), ",N z,G", (flags), v9 }, \
1294 { opcode, (mask)|ANNUL, BPRED|(lose)|(2<<20), ",a,N z,G", (flags), v9 }
1295
1296/* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */
1297#define tr(opcode, mask, lose, flags) \
f930d07e
BS		 1298 { opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0, "Z,i", (flags), v9 }, /* %g0 + imm */ \
1299 { opcode, (mask)|(2<<11)|IMMED, (lose), "Z,1+i", (flags), v9 }, /* rs1 + imm */ \
1300 { opcode, (mask)|(2<<11), IMMED|(lose), "Z,1+2", (flags), v9 }, /* rs1 + rs2 */ \
1301 { opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0, "Z,1", (flags), v9 }, /* rs1 + %g0 */ \
1302 { opcode, (mask)|IMMED, (lose)|RS1_G0, "z,i", (flags)|F_ALIAS, v9 }, /* %g0 + imm */ \
1303 { opcode, (mask)|IMMED, (lose), "z,1+i", (flags)|F_ALIAS, v9 }, /* rs1 + imm */ \
1304 { opcode, (mask), IMMED|(lose), "z,1+2", (flags)|F_ALIAS, v9 }, /* rs1 + rs2 */ \
1305 { opcode, (mask), IMMED|(lose)|RS2_G0, "z,1", (flags)|F_ALIAS, v9 }, /* rs1 + %g0 */ \
1306 { opcode, (mask)|IMMED, (lose)|RS1_G0, "i", (flags), v6 }, /* %g0 + imm */ \
1307 { opcode, (mask)|IMMED, (lose), "1+i", (flags), v6 }, /* rs1 + imm */ \
1308 { opcode, (mask), IMMED|(lose), "1+2", (flags), v6 }, /* rs1 + rs2 */ \
1309 { opcode, (mask), IMMED|(lose)|RS2_G0, "1", (flags), v6 } /* rs1 + %g0 */
aa0aa4fa
FB		 1310
1311/* v9: We must put `brx' before `br', to ensure that we never match something
1312 v9: against an expression unless it is an expression. Otherwise, we end
1313 v9: up with undefined symbol tables entries, because they get added, but
1314 v9: are not deleted if the pattern fails to match. */
1315
1316/* Define both branches and traps based on condition mask */
1317#define cond(bop, top, mask, flags) \
1318 brx(bop, F2(0, 1)|(mask), F2(~0, ~1)|((~mask)&COND(~0)), F_DELAYED|(flags)), /* v9 */ \
1319 br(bop, F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)), F_DELAYED|(flags)), \
1320 tr(top, F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), ((flags) & ~(F_UNBR|F_CONDBR)))
1321
1322/* Define all the conditions, all the branches, all the traps. */
1323
1324/* Standard branch, trap mnemonics */
f930d07e 1325cond ("b", "ta", CONDA, F_UNBR),
aa0aa4fa 1326/* Alternative form (just for assembly, not for disassembly) */
f930d07e
BS		 1327cond ("ba", "t", CONDA, F_UNBR|F_ALIAS),
1328
1329cond ("bcc", "tcc", CONDCC, F_CONDBR),
1330cond ("bcs", "tcs", CONDCS, F_CONDBR),
1331cond ("be", "te", CONDE, F_CONDBR),
1332cond ("beq", "teq", CONDE, F_CONDBR|F_ALIAS),
1333cond ("bg", "tg", CONDG, F_CONDBR),
1334cond ("bgt", "tgt", CONDG, F_CONDBR|F_ALIAS),
1335cond ("bge", "tge", CONDGE, F_CONDBR),
1336cond ("bgeu", "tgeu", CONDGEU, F_CONDBR|F_ALIAS), /* for cc */
1337cond ("bgu", "tgu", CONDGU, F_CONDBR),
1338cond ("bl", "tl", CONDL, F_CONDBR),
1339cond ("blt", "tlt", CONDL, F_CONDBR|F_ALIAS),
1340cond ("ble", "tle", CONDLE, F_CONDBR),
1341cond ("bleu", "tleu", CONDLEU, F_CONDBR),
1342cond ("blu", "tlu", CONDLU, F_CONDBR|F_ALIAS), /* for cs */
1343cond ("bn", "tn", CONDN, F_CONDBR),
1344cond ("bne", "tne", CONDNE, F_CONDBR),
1345cond ("bneg", "tneg", CONDNEG, F_CONDBR),
1346cond ("bnz", "tnz", CONDNZ, F_CONDBR|F_ALIAS), /* for ne */
1347cond ("bpos", "tpos", CONDPOS, F_CONDBR),
1348cond ("bvc", "tvc", CONDVC, F_CONDBR),
1349cond ("bvs", "tvs", CONDVS, F_CONDBR),
1350cond ("bz", "tz", CONDZ, F_CONDBR|F_ALIAS), /* for e */
aa0aa4fa
FB		 1351
1352#undef cond
1353#undef br
1354#undef brr /* v9 */
1355#undef tr
1356
1357#define brr(opcode, mask, lose, flags) /* v9 */ \
1358 { opcode, (mask)|BPRED, ANNUL|(lose), "1,k", F_DELAYED|(flags), v9 }, \
1359 { opcode, (mask)|BPRED, ANNUL|(lose), ",T 1,k", F_DELAYED|(flags), v9 }, \
1360 { opcode, (mask)|BPRED|ANNUL, (lose), ",a 1,k", F_DELAYED|(flags), v9 }, \
1361 { opcode, (mask)|BPRED|ANNUL, (lose), ",a,T 1,k", F_DELAYED|(flags), v9 }, \
1362 { opcode, (mask), ANNUL|BPRED|(lose), ",N 1,k", F_DELAYED|(flags), v9 }, \
1363 { opcode, (mask)|ANNUL, BPRED|(lose), ",a,N 1,k", F_DELAYED|(flags), v9 }
1364
1365#define condr(bop, mask, flags) /* v9 */ \
1366 brr(bop, F2(0, 3)|COND(mask), F2(~0, ~3)|COND(~(mask)), (flags)) /* v9 */
1367
1368/* v9 */ condr("brnz", 0x5, F_CONDBR),
1369/* v9 */ condr("brz", 0x1, F_CONDBR),
1370/* v9 */ condr("brgez", 0x7, F_CONDBR),
1371/* v9 */ condr("brlz", 0x3, F_CONDBR),
1372/* v9 */ condr("brlez", 0x2, F_CONDBR),
1373/* v9 */ condr("brgz", 0x6, F_CONDBR),
1374
1375#undef condr /* v9 */
1376#undef brr /* v9 */
1377
1378#define movr(opcode, mask, flags) /* v9 */ \
1379 { opcode, F3(2, 0x2f, 0)|RCOND(mask), F3(~2, ~0x2f, ~0)|RCOND(~(mask)), "1,2,d", (flags), v9 }, \
1380 { opcode, F3(2, 0x2f, 1)|RCOND(mask), F3(~2, ~0x2f, ~1)|RCOND(~(mask)), "1,j,d", (flags), v9 }
1381
1382#define fmrrs(opcode, mask, lose, flags) /* v9 */ \
1383 { opcode, (mask), (lose), "1,f,g", (flags) | F_FLOAT, v9 }
1384#define fmrrd(opcode, mask, lose, flags) /* v9 */ \
1385 { opcode, (mask), (lose), "1,B,H", (flags) | F_FLOAT, v9 }
1386#define fmrrq(opcode, mask, lose, flags) /* v9 */ \
1387 { opcode, (mask), (lose), "1,R,J", (flags) | F_FLOAT, v9 }
1388
1389#define fmovrs(mop, mask, flags) /* v9 */ \
1390 fmrrs(mop, F3(2, 0x35, 0)|OPF_LOW5(5)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~5)|RCOND(~(mask)), (flags)) /* v9 */
1391#define fmovrd(mop, mask, flags) /* v9 */ \
1392 fmrrd(mop, F3(2, 0x35, 0)|OPF_LOW5(6)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~6)|RCOND(~(mask)), (flags)) /* v9 */
1393#define fmovrq(mop, mask, flags) /* v9 */ \
1394 fmrrq(mop, F3(2, 0x35, 0)|OPF_LOW5(7)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~7)|RCOND(~(mask)), (flags)) /* v9 */
1395
1396/* v9 */ movr("movrne", 0x5, 0),
1397/* v9 */ movr("movre", 0x1, 0),
1398/* v9 */ movr("movrgez", 0x7, 0),
1399/* v9 */ movr("movrlz", 0x3, 0),
1400/* v9 */ movr("movrlez", 0x2, 0),
1401/* v9 */ movr("movrgz", 0x6, 0),
1402/* v9 */ movr("movrnz", 0x5, F_ALIAS),
1403/* v9 */ movr("movrz", 0x1, F_ALIAS),
1404
1405/* v9 */ fmovrs("fmovrsne", 0x5, 0),
1406/* v9 */ fmovrs("fmovrse", 0x1, 0),
1407/* v9 */ fmovrs("fmovrsgez", 0x7, 0),
1408/* v9 */ fmovrs("fmovrslz", 0x3, 0),
1409/* v9 */ fmovrs("fmovrslez", 0x2, 0),
1410/* v9 */ fmovrs("fmovrsgz", 0x6, 0),
1411/* v9 */ fmovrs("fmovrsnz", 0x5, F_ALIAS),
1412/* v9 */ fmovrs("fmovrsz", 0x1, F_ALIAS),
1413
1414/* v9 */ fmovrd("fmovrdne", 0x5, 0),
1415/* v9 */ fmovrd("fmovrde", 0x1, 0),
1416/* v9 */ fmovrd("fmovrdgez", 0x7, 0),
1417/* v9 */ fmovrd("fmovrdlz", 0x3, 0),
1418/* v9 */ fmovrd("fmovrdlez", 0x2, 0),
1419/* v9 */ fmovrd("fmovrdgz", 0x6, 0),
1420/* v9 */ fmovrd("fmovrdnz", 0x5, F_ALIAS),
1421/* v9 */ fmovrd("fmovrdz", 0x1, F_ALIAS),
1422
1423/* v9 */ fmovrq("fmovrqne", 0x5, 0),
1424/* v9 */ fmovrq("fmovrqe", 0x1, 0),
1425/* v9 */ fmovrq("fmovrqgez", 0x7, 0),
1426/* v9 */ fmovrq("fmovrqlz", 0x3, 0),
1427/* v9 */ fmovrq("fmovrqlez", 0x2, 0),
1428/* v9 */ fmovrq("fmovrqgz", 0x6, 0),
1429/* v9 */ fmovrq("fmovrqnz", 0x5, F_ALIAS),
1430/* v9 */ fmovrq("fmovrqz", 0x1, F_ALIAS),
1431
1432#undef movr /* v9 */
1433#undef fmovr /* v9 */
1434#undef fmrr /* v9 */
1435
1436#define movicc(opcode, cond, flags) /* v9 */ \
1437 { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|XCC|(1<<11), "z,2,d", flags, v9 }, \
1438 { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|XCC|(1<<11), "z,I,d", flags, v9 }, \
1439 { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|(1<<11), "Z,2,d", flags, v9 }, \
1440 { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|(1<<11), "Z,I,d", flags, v9 }
1441
1442#define movfcc(opcode, fcond, flags) /* v9 */ \
1443 { opcode, F3(2, 0x2c, 0)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~0), "6,2,d", flags, v9 }, \
1444 { opcode, F3(2, 0x2c, 1)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~1), "6,I,d", flags, v9 }, \
1445 { opcode, F3(2, 0x2c, 0)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~0), "7,2,d", flags, v9 }, \
1446 { opcode, F3(2, 0x2c, 1)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~1), "7,I,d", flags, v9 }, \
1447 { opcode, F3(2, 0x2c, 0)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~0), "8,2,d", flags, v9 }, \
1448 { opcode, F3(2, 0x2c, 1)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~1), "8,I,d", flags, v9 }, \
1449 { opcode, F3(2, 0x2c, 0)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~0), "9,2,d", flags, v9 }, \
1450 { opcode, F3(2, 0x2c, 1)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~1), "9,I,d", flags, v9 }
1451
1452#define movcc(opcode, cond, fcond, flags) /* v9 */ \
1453 movfcc (opcode, fcond, flags), /* v9 */ \
1454 movicc (opcode, cond, flags) /* v9 */
1455
f930d07e
BS		 1456/* v9 */ movcc ("mova", CONDA, FCONDA, 0),
1457/* v9 */ movicc ("movcc", CONDCC, 0),
1458/* v9 */ movicc ("movgeu", CONDGEU, F_ALIAS),
1459/* v9 */ movicc ("movcs", CONDCS, 0),
1460/* v9 */ movicc ("movlu", CONDLU, F_ALIAS),
1461/* v9 */ movcc ("move", CONDE, FCONDE, 0),
1462/* v9 */ movcc ("movg", CONDG, FCONDG, 0),
1463/* v9 */ movcc ("movge", CONDGE, FCONDGE, 0),
1464/* v9 */ movicc ("movgu", CONDGU, 0),
1465/* v9 */ movcc ("movl", CONDL, FCONDL, 0),
1466/* v9 */ movcc ("movle", CONDLE, FCONDLE, 0),
1467/* v9 */ movicc ("movleu", CONDLEU, 0),
1468/* v9 */ movfcc ("movlg", FCONDLG, 0),
1469/* v9 */ movcc ("movn", CONDN, FCONDN, 0),
1470/* v9 */ movcc ("movne", CONDNE, FCONDNE, 0),
1471/* v9 */ movicc ("movneg", CONDNEG, 0),
1472/* v9 */ movcc ("movnz", CONDNZ, FCONDNZ, F_ALIAS),
1473/* v9 */ movfcc ("movo", FCONDO, 0),
1474/* v9 */ movicc ("movpos", CONDPOS, 0),
1475/* v9 */ movfcc ("movu", FCONDU, 0),
1476/* v9 */ movfcc ("movue", FCONDUE, 0),
1477/* v9 */ movfcc ("movug", FCONDUG, 0),
1478/* v9 */ movfcc ("movuge", FCONDUGE, 0),
1479/* v9 */ movfcc ("movul", FCONDUL, 0),
1480/* v9 */ movfcc ("movule", FCONDULE, 0),
1481/* v9 */ movicc ("movvc", CONDVC, 0),
1482/* v9 */ movicc ("movvs", CONDVS, 0),
1483/* v9 */ movcc ("movz", CONDZ, FCONDZ, F_ALIAS),
aa0aa4fa
FB		 1484
1485#undef movicc /* v9 */
1486#undef movfcc /* v9 */
1487#undef movcc /* v9 */
1488
f930d07e
BS		 1489#define FM_SF 1 /* v9 - values for fpsize */
1490#define FM_DF 2 /* v9 */
1491#define FM_QF 3 /* v9 */
aa0aa4fa 1492
46f42f29
BS		 1493#define fmoviccx(opcode, fpsize, args, cond, flags) /* v9 */ \
1494{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags, v9 }, \
1495{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags, v9 }
aa0aa4fa 1496
46f42f29
BS		 1497#define fmovfccx(opcode, fpsize, args, fcond, flags) /* v9 */ \
1498{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags, v9 }, \
1499{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags, v9 }, \
1500{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags, v9 }, \
1501{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags, v9 }
aa0aa4fa
FB		 1502
1503/* FIXME: use fmovicc/fmovfcc? */ /* v9 */
46f42f29
BS		 1504#define fmovccx(opcode, fpsize, args, cond, fcond, flags) /* v9 */ \
1505{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags | F_FLOAT, v9 }, \
1506{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags | F_FLOAT, v9 }, \
1507{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags | F_FLOAT, v9 }, \
1508{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags | F_FLOAT, v9 }, \
1509{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags | F_FLOAT, v9 }, \
1510{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags | F_FLOAT, v9 }
1511
1512#define fmovicc(suffix, cond, flags) /* v9 */ \
1513fmoviccx("fmovd" suffix, FM_DF, "B,H", cond, flags), \
1514fmoviccx("fmovq" suffix, FM_QF, "R,J", cond, flags), \
1515fmoviccx("fmovs" suffix, FM_SF, "f,g", cond, flags)
1516
1517#define fmovfcc(suffix, fcond, flags) /* v9 */ \
1518fmovfccx("fmovd" suffix, FM_DF, "B,H", fcond, flags), \
1519fmovfccx("fmovq" suffix, FM_QF, "R,J", fcond, flags), \
1520fmovfccx("fmovs" suffix, FM_SF, "f,g", fcond, flags)
1521
1522#define fmovcc(suffix, cond, fcond, flags) /* v9 */ \
1523fmovccx("fmovd" suffix, FM_DF, "B,H", cond, fcond, flags), \
1524fmovccx("fmovq" suffix, FM_QF, "R,J", cond, fcond, flags), \
1525fmovccx("fmovs" suffix, FM_SF, "f,g", cond, fcond, flags)
1526
1527/* v9 */ fmovcc ("a", CONDA, FCONDA, 0),
1528/* v9 */ fmovicc ("cc", CONDCC, 0),
1529/* v9 */ fmovicc ("cs", CONDCS, 0),
1530/* v9 */ fmovcc ("e", CONDE, FCONDE, 0),
1531/* v9 */ fmovcc ("g", CONDG, FCONDG, 0),
1532/* v9 */ fmovcc ("ge", CONDGE, FCONDGE, 0),
1533/* v9 */ fmovicc ("geu", CONDGEU, F_ALIAS),
1534/* v9 */ fmovicc ("gu", CONDGU, 0),
1535/* v9 */ fmovcc ("l", CONDL, FCONDL, 0),
1536/* v9 */ fmovcc ("le", CONDLE, FCONDLE, 0),
1537/* v9 */ fmovicc ("leu", CONDLEU, 0),
1538/* v9 */ fmovfcc ("lg", FCONDLG, 0),
1539/* v9 */ fmovicc ("lu", CONDLU, F_ALIAS),
1540/* v9 */ fmovcc ("n", CONDN, FCONDN, 0),
1541/* v9 */ fmovcc ("ne", CONDNE, FCONDNE, 0),
1542/* v9 */ fmovicc ("neg", CONDNEG, 0),
1543/* v9 */ fmovcc ("nz", CONDNZ, FCONDNZ, F_ALIAS),
1544/* v9 */ fmovfcc ("o", FCONDO, 0),
1545/* v9 */ fmovicc ("pos", CONDPOS, 0),
1546/* v9 */ fmovfcc ("u", FCONDU, 0),
1547/* v9 */ fmovfcc ("ue", FCONDUE, 0),
1548/* v9 */ fmovfcc ("ug", FCONDUG, 0),
1549/* v9 */ fmovfcc ("uge", FCONDUGE, 0),
1550/* v9 */ fmovfcc ("ul", FCONDUL, 0),
1551/* v9 */ fmovfcc ("ule", FCONDULE, 0),
1552/* v9 */ fmovicc ("vc", CONDVC, 0),
1553/* v9 */ fmovicc ("vs", CONDVS, 0),
1554/* v9 */ fmovcc ("z", CONDZ, FCONDZ, F_ALIAS),
1555
1556#undef fmoviccx /* v9 */
1557#undef fmovfccx /* v9 */
1558#undef fmovccx /* v9 */
aa0aa4fa
FB		 1559#undef fmovicc /* v9 */
1560#undef fmovfcc /* v9 */
1561#undef fmovcc /* v9 */
1562#undef FM_DF /* v9 */
1563#undef FM_QF /* v9 */
1564#undef FM_SF /* v9 */
1565
1566/* Coprocessor branches. */
1567#define CBR(opcode, mask, lose, flags, arch) \
46f42f29
BS		 1568 { opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED, arch }, \
1569 { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED, arch }
aa0aa4fa
FB		 1570
1571/* Floating point branches. */
1572#define FBR(opcode, mask, lose, flags) \
46f42f29
BS		 1573 { opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED | F_FBR, v6 }, \
1574 { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED | F_FBR, v6 }
aa0aa4fa
FB		 1575
1576/* V9 extended floating point branches. */
1577#define FBRX(opcode, mask, lose, flags) /* v9 */ \
1578 { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G", flags|F_DELAYED|F_FBR, v9 }, \
1579 { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G", flags|F_DELAYED|F_FBR, v9 }, \
1580 { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G", flags|F_DELAYED|F_FBR, v9 }, \
1581 { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G", flags|F_DELAYED|F_FBR, v9 }, \
1582 { opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G", flags|F_DELAYED|F_FBR, v9 }, \
1583 { opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G", flags|F_DELAYED|F_FBR, v9 }, \
1584 { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), "7,G", flags|F_DELAYED|F_FBR, v9 }, \
1585 { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G", flags|F_DELAYED|F_FBR, v9 }, \
1586 { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a 7,G", flags|F_DELAYED|F_FBR, v9 }, \
1587 { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G", flags|F_DELAYED|F_FBR, v9 }, \
1588 { opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G", flags|F_DELAYED|F_FBR, v9 }, \
1589 { opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G", flags|F_DELAYED|F_FBR, v9 }, \
1590 { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), "8,G", flags|F_DELAYED|F_FBR, v9 }, \
1591 { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G", flags|F_DELAYED|F_FBR, v9 }, \
1592 { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a 8,G", flags|F_DELAYED|F_FBR, v9 }, \
1593 { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G", flags|F_DELAYED|F_FBR, v9 }, \
1594 { opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G", flags|F_DELAYED|F_FBR, v9 }, \
1595 { opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G", flags|F_DELAYED|F_FBR, v9 }, \
1596 { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), "9,G", flags|F_DELAYED|F_FBR, v9 }, \
1597 { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G", flags|F_DELAYED|F_FBR, v9 }, \
1598 { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a 9,G", flags|F_DELAYED|F_FBR, v9 }, \
1599 { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G", flags|F_DELAYED|F_FBR, v9 }, \
1600 { opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G", flags|F_DELAYED|F_FBR, v9 }, \
1601 { opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", flags|F_DELAYED|F_FBR, v9 }
1602
1603/* v9: We must put `FBRX' before `FBR', to ensure that we never match
1604 v9: something against an expression unless it is an expression. Otherwise,
1605 v9: we end up with undefined symbol tables entries, because they get added,
1606 v9: but are not deleted if the pattern fails to match. */
1607
1608#define CONDFC(fop, cop, mask, flags) \
1609 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1610 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
1611 CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6notlet)
1612
1613#define CONDFCL(fop, cop, mask, flags) \
1614 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1615 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
1616 CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6)
1617
1618#define CONDF(fop, mask, flags) \
1619 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1620 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags)
1621
1622CONDFC ("fb", "cb", 0x8, F_UNBR),
f930d07e
BS		 1623CONDFCL ("fba", "cba", 0x8, F_UNBR|F_ALIAS),
1624CONDFC ("fbe", "cb0", 0x9, F_CONDBR),
aa0aa4fa 1625CONDF ("fbz", 0x9, F_CONDBR|F_ALIAS),
f930d07e 1626CONDFC ("fbg", "cb2", 0x6, F_CONDBR),
aa0aa4fa 1627CONDFC ("fbge", "cb02", 0xb, F_CONDBR),
f930d07e 1628CONDFC ("fbl", "cb1", 0x4, F_CONDBR),
aa0aa4fa
FB		 1629CONDFC ("fble", "cb01", 0xd, F_CONDBR),
1630CONDFC ("fblg", "cb12", 0x2, F_CONDBR),
f930d07e 1631CONDFCL ("fbn", "cbn", 0x0, F_UNBR),
aa0aa4fa
FB		 1632CONDFC ("fbne", "cb123", 0x1, F_CONDBR),
1633CONDF ("fbnz", 0x1, F_CONDBR|F_ALIAS),
f930d07e
BS		 1634CONDFC ("fbo", "cb012", 0xf, F_CONDBR),
1635CONDFC ("fbu", "cb3", 0x7, F_CONDBR),
aa0aa4fa
FB		 1636CONDFC ("fbue", "cb03", 0xa, F_CONDBR),
1637CONDFC ("fbug", "cb23", 0x5, F_CONDBR),
1638CONDFC ("fbuge", "cb023", 0xc, F_CONDBR),
1639CONDFC ("fbul", "cb13", 0x3, F_CONDBR),
1640CONDFC ("fbule", "cb013", 0xe, F_CONDBR),
1641
1642#undef CONDFC
1643#undef CONDFCL
1644#undef CONDF
1645#undef CBR
1646#undef FBR
f930d07e 1647#undef FBRX /* v9 */
aa0aa4fa 1648
f930d07e
BS		 1649{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%g0 */
1650{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%g0 */
1651{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+i,%g0 */
1652{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* jmpl i+rs1,%g0 */
1653{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* jmpl %g0+i,%g0 */
1654{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+0,%g0 */
aa0aa4fa 1655
f930d07e 1656{ "nop", F2(0, 4), 0xfeffffff, "", 0, v6 }, /* sethi 0, %g0 */
aa0aa4fa 1657
f930d07e
BS		 1658{ "set", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v6 },
1659{ "setuw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 },
1660{ "setsw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 },
1661{ "setx", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS, v9 },
aa0aa4fa 1662
f930d07e 1663{ "sethi", F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, v6 },
aa0aa4fa 1664
f930d07e
BS		 1665{ "taddcc", F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0), "1,2,d", 0, v6 },
1666{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "1,i,d", 0, v6 },
1667{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "i,1,d", 0, v6 },
1668{ "taddcctv", F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0), "1,2,d", 0, v6 },
1669{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "1,i,d", 0, v6 },
1670{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "i,1,d", 0, v6 },
aa0aa4fa 1671
f930d07e
BS		 1672{ "tsubcc", F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0), "1,2,d", 0, v6 },
1673{ "tsubcc", F3(2, 0x21, 1), F3(~2, ~0x21, ~1), "1,i,d", 0, v6 },
1674{ "tsubcctv", F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0), "1,2,d", 0, v6 },
1675{ "tsubcctv", F3(2, 0x23, 1), F3(~2, ~0x23, ~1), "1,i,d", 0, v6 },
aa0aa4fa 1676
f930d07e
BS		 1677{ "unimp", F2(0x0, 0x0), 0xffc00000, "n", 0, v6notv9 },
1678{ "illtrap", F2(0, 0), F2(~0, ~0)|RD_G0, "n", 0, v9 },
aa0aa4fa
FB		 1679
1680/* This *is* a commutative instruction. */
f930d07e
BS		 1681{ "xnor", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,2,d", 0, v6 },
1682{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "1,i,d", 0, v6 },
1683{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "i,1,d", 0, v6 },
aa0aa4fa 1684/* This *is* a commutative instruction. */
f930d07e
BS		 1685{ "xnorcc", F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0), "1,2,d", 0, v6 },
1686{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "1,i,d", 0, v6 },
1687{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "i,1,d", 0, v6 },
1688{ "xor", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "1,2,d", 0, v6 },
1689{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "1,i,d", 0, v6 },
1690{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,1,d", 0, v6 },
1691{ "xorcc", F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0), "1,2,d", 0, v6 },
1692{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "1,i,d", 0, v6 },
1693{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "i,1,d", 0, v6 },
1694
1695{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, v6 }, /* xnor rs1,%0,rd */
1696{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, v6 }, /* xnor rd,%0,rd */
1697
1698{ "btog", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* xor rd,rs2,rd */
1699{ "btog", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,r", F_ALIAS, v6 }, /* xor rd,i,rd */
aa0aa4fa
FB		 1700
1701/* FPop1 and FPop2 are not instructions. Don't accept them. */
1702
f930d07e
BS		 1703{ "fdtoi", F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", F_FLOAT, v6 },
1704{ "fstoi", F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, v6 },
1705{ "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, v8 },
1706
46f42f29
BS		 1707{ "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,H", F_FLOAT, v9 },
1708{ "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,H", F_FLOAT, v9 },
1709{ "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,H", F_FLOAT, v9 },
f930d07e
BS		 1710
1711{ "fitod", F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, v6 },
1712{ "fitos", F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, v6 },
1713{ "fitoq", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, v8 },
1714
46f42f29
BS		 1715{ "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "B,H", F_FLOAT, v9 },
1716{ "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "B,g", F_FLOAT, v9 },
1717{ "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "B,J", F_FLOAT, v9 },
f930d07e
BS		 1718
1719{ "fdtoq", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, v8 },
1720{ "fdtos", F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, v6 },
1721{ "fqtod", F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", F_FLOAT, v8 },
1722{ "fqtos", F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", F_FLOAT, v8 },
1723{ "fstod", F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", F_FLOAT, v6 },
1724{ "fstoq", F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", F_FLOAT, v8 },
1725
1726{ "fdivd", F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT, v6 },
1727{ "fdivq", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT, v8 },
1728{ "fdivx", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT|F_ALIAS, v8 },
1729{ "fdivs", F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT, v6 },
1730{ "fmuld", F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT, v6 },
1731{ "fmulq", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT, v8 },
1732{ "fmulx", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT|F_ALIAS, v8 },
1733{ "fmuls", F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT, v6 },
1734
1735{ "fdmulq", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT, v8 },
1736{ "fdmulx", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT|F_ALIAS, v8 },
1737{ "fsmuld", F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT, v8 },
1738
1739{ "fsqrtd", F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", F_FLOAT, v7 },
1740{ "fsqrtq", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT, v8 },
1741{ "fsqrtx", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v8 },
1742{ "fsqrts", F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", F_FLOAT, v7 },
1743
1744{ "fabsd", F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H", F_FLOAT, v9 },
1745{ "fabsq", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT, v9 },
1746{ "fabsx", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 },
1747{ "fabss", F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", F_FLOAT, v6 },
1748{ "fmovd", F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", F_FLOAT, v9 },
1749{ "fmovq", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT, v9 },
1750{ "fmovx", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 },
1751{ "fmovs", F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", F_FLOAT, v6 },
1752{ "fnegd", F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H", F_FLOAT, v9 },
1753{ "fnegq", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT, v9 },
1754{ "fnegx", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 },
1755{ "fnegs", F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", F_FLOAT, v6 },
1756
1757{ "faddd", F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT, v6 },
1758{ "faddq", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT, v8 },
1759{ "faddx", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT|F_ALIAS, v8 },
1760{ "fadds", F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT, v6 },
1761{ "fsubd", F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT, v6 },
1762{ "fsubq", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT, v8 },
1763{ "fsubx", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT|F_ALIAS, v8 },
1764{ "fsubs", F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT, v6 },
1765
1766#define CMPFCC(x) (((x)&0x3)<<25)
1767
1768{ "fcmpd", F3F(2, 0x35, 0x052), F3F(~2, ~0x35, ~0x052)|RD_G0, "v,B", F_FLOAT, v6 },
1769{ "fcmpd", CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052), "6,v,B", F_FLOAT, v9 },
1770{ "fcmpd", CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052), "7,v,B", F_FLOAT, v9 },
1771{ "fcmpd", CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052), "8,v,B", F_FLOAT, v9 },
1772{ "fcmpd", CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052), "9,v,B", F_FLOAT, v9 },
1773{ "fcmped", F3F(2, 0x35, 0x056), F3F(~2, ~0x35, ~0x056)|RD_G0, "v,B", F_FLOAT, v6 },
1774{ "fcmped", CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056), "6,v,B", F_FLOAT, v9 },
1775{ "fcmped", CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056), "7,v,B", F_FLOAT, v9 },
1776{ "fcmped", CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056), "8,v,B", F_FLOAT, v9 },
1777{ "fcmped", CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056), "9,v,B", F_FLOAT, v9 },
1778{ "fcmpq", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT, v8 },
1779{ "fcmpq", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT, v9 },
1780{ "fcmpq", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT, v9 },
1781{ "fcmpq", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT, v9 },
1782{ "fcmpq", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT, v9 },
1783{ "fcmpeq", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT, v8 },
1784{ "fcmpeq", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT, v9 },
1785{ "fcmpeq", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT, v9 },
1786{ "fcmpeq", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT, v9 },
1787{ "fcmpeq", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT, v9 },
1788{ "fcmpx", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT|F_ALIAS, v8 },
1789{ "fcmpx", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT|F_ALIAS, v9 },
1790{ "fcmpx", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT|F_ALIAS, v9 },
1791{ "fcmpx", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT|F_ALIAS, v9 },
1792{ "fcmpx", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT|F_ALIAS, v9 },
1793{ "fcmpex", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT|F_ALIAS, v8 },
1794{ "fcmpex", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT|F_ALIAS, v9 },
1795{ "fcmpex", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT|F_ALIAS, v9 },
1796{ "fcmpex", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT|F_ALIAS, v9 },
1797{ "fcmpex", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT|F_ALIAS, v9 },
1798{ "fcmps", F3F(2, 0x35, 0x051), F3F(~2, ~0x35, ~0x051)|RD_G0, "e,f", F_FLOAT, v6 },
1799{ "fcmps", CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051), "6,e,f", F_FLOAT, v9 },
1800{ "fcmps", CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051), "7,e,f", F_FLOAT, v9 },
1801{ "fcmps", CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051), "8,e,f", F_FLOAT, v9 },
1802{ "fcmps", CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051), "9,e,f", F_FLOAT, v9 },
1803{ "fcmpes", F3F(2, 0x35, 0x055), F3F(~2, ~0x35, ~0x055)|RD_G0, "e,f", F_FLOAT, v6 },
1804{ "fcmpes", CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055), "6,e,f", F_FLOAT, v9 },
1805{ "fcmpes", CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055), "7,e,f", F_FLOAT, v9 },
1806{ "fcmpes", CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055), "8,e,f", F_FLOAT, v9 },
1807{ "fcmpes", CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055), "9,e,f", F_FLOAT, v9 },
aa0aa4fa
FB		 1808
1809/* These Extended FPop (FIFO) instructions are new in the Fujitsu
1810 MB86934, replacing the CPop instructions from v6 and later
1811 processors. */
1812
1813#define EFPOP1_2(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op)|RS1_G0, args, 0, sparclite }
1814#define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op), args, 0, sparclite }
1815#define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37, ~op)|RD_G0, args, 0, sparclite }
1816
f930d07e
BS		 1817EFPOP1_2 ("efitod", 0x0c8, "f,H"),
1818EFPOP1_2 ("efitos", 0x0c4, "f,g"),
1819EFPOP1_2 ("efdtoi", 0x0d2, "B,g"),
1820EFPOP1_2 ("efstoi", 0x0d1, "f,g"),
1821EFPOP1_2 ("efstod", 0x0c9, "f,H"),
1822EFPOP1_2 ("efdtos", 0x0c6, "B,g"),
1823EFPOP1_2 ("efmovs", 0x001, "f,g"),
1824EFPOP1_2 ("efnegs", 0x005, "f,g"),
1825EFPOP1_2 ("efabss", 0x009, "f,g"),
1826EFPOP1_2 ("efsqrtd", 0x02a, "B,H"),
1827EFPOP1_2 ("efsqrts", 0x029, "f,g"),
1828EFPOP1_3 ("efaddd", 0x042, "v,B,H"),
1829EFPOP1_3 ("efadds", 0x041, "e,f,g"),
1830EFPOP1_3 ("efsubd", 0x046, "v,B,H"),
1831EFPOP1_3 ("efsubs", 0x045, "e,f,g"),
1832EFPOP1_3 ("efdivd", 0x04e, "v,B,H"),
1833EFPOP1_3 ("efdivs", 0x04d, "e,f,g"),
1834EFPOP1_3 ("efmuld", 0x04a, "v,B,H"),
1835EFPOP1_3 ("efmuls", 0x049, "e,f,g"),
1836EFPOP1_3 ("efsmuld", 0x069, "e,f,H"),
1837EFPOP2_2 ("efcmpd", 0x052, "v,B"),
1838EFPOP2_2 ("efcmped", 0x056, "v,B"),
1839EFPOP2_2 ("efcmps", 0x051, "e,f"),
1840EFPOP2_2 ("efcmpes", 0x055, "e,f"),
aa0aa4fa
FB		 1841
1842#undef EFPOP1_2
1843#undef EFPOP1_3
1844#undef EFPOP2_2
1845
1846/* These are marked F_ALIAS, so that they won't conflict with sparclite insns
1847 present. Otherwise, the F_ALIAS flag is ignored. */
f930d07e
BS		 1848{ "cpop1", F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS, v6notv9 },
1849{ "cpop2", F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, v6notv9 },
aa0aa4fa
FB		 1850
1851/* sparclet specific insns */
1852
1853COMMUTEOP ("umac", 0x3e, sparclet),
1854COMMUTEOP ("smac", 0x3f, sparclet),
1855COMMUTEOP ("umacd", 0x2e, sparclet),
1856COMMUTEOP ("smacd", 0x2f, sparclet),
1857COMMUTEOP ("umuld", 0x09, sparclet),
1858COMMUTEOP ("smuld", 0x0d, sparclet),
1859
f930d07e
BS		 1860{ "shuffle", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, sparclet },
1861{ "shuffle", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, sparclet },
aa0aa4fa
FB		 1862
1863/* The manual isn't completely accurate on these insns. The `rs2' field is
1864 treated as being 6 bits to account for 6 bit immediates to cpush. It is
1865 assumed that it is intended that bit 5 is 0 when rs2 contains a reg. */
1866#define BIT5 (1<<5)
f930d07e
BS		 1867{ "crdcxt", F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0), "U,d", 0, sparclet },
1868{ "cwrcxt", F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0), "1,u", 0, sparclet },
1869{ "cpush", F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0), "1,2", 0, sparclet },
1870{ "cpush", F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0), "1,Y", 0, sparclet },
1871{ "cpusha", F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0), "1,2", 0, sparclet },
1872{ "cpusha", F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0), "1,Y", 0, sparclet },
1873{ "cpull", F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, sparclet },
aa0aa4fa
FB		 1874#undef BIT5
1875
1876/* sparclet coprocessor branch insns */
1877#define SLCBCC2(opcode, mask, lose) \
1878 { opcode, (mask), ANNUL|(lose), "l", F_DELAYED|F_CONDBR, sparclet }, \
1879 { opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR, sparclet }
1880#define SLCBCC(opcode, mask) \
1881 SLCBCC2(opcode, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)))
1882
1883/* cbn,cba can't be defined here because they're defined elsewhere and GAS
1884 requires all mnemonics of the same name to be consecutive. */
1885/*SLCBCC("cbn", 0), - already defined */
1886SLCBCC("cbe", 1),
1887SLCBCC("cbf", 2),
1888SLCBCC("cbef", 3),
1889SLCBCC("cbr", 4),
1890SLCBCC("cber", 5),
1891SLCBCC("cbfr", 6),
1892SLCBCC("cbefr", 7),
1893/*SLCBCC("cba", 8), - already defined */
1894SLCBCC("cbne", 9),
1895SLCBCC("cbnf", 10),
1896SLCBCC("cbnef", 11),
1897SLCBCC("cbnr", 12),
1898SLCBCC("cbner", 13),
1899SLCBCC("cbnfr", 14),
1900SLCBCC("cbnefr", 15),
1901
1902#undef SLCBCC2
1903#undef SLCBCC
1904
f930d07e
BS		 1905{ "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, v9 },
1906{ "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, v9 },
1907{ "casxa", F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, v9 },
1908{ "casxa", F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, v9 },
aa0aa4fa
FB		 1909
1910/* v9 synthetic insns */
f930d07e
BS		 1911{ "iprefetch", F2(0, 1)|(2<<20)|BPRED, F2(~0, ~1)|(1<<20)|ANNUL|COND(~0), "G", 0, v9 }, /* bn,a,pt %xcc,label */
1912{ "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* sra rs1,%g0,rd */
1913{ "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* sra rd,%g0,rd */
1914{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* srl rs1,%g0,rd */
1915{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* srl rd,%g0,rd */
1916{ "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P,rs2,rd */
1917{ "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */
1918{ "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P,rs2,rd */
1919{ "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */
aa0aa4fa
FB		 1920
1921/* Ultrasparc extensions */
f930d07e 1922{ "shutdown", F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0|RS1_G0|RS2_G0, "", 0, v9a },
aa0aa4fa
FB		 1923
1924/* FIXME: Do we want to mark these as F_FLOAT, or something similar? */
f930d07e
BS		 1925{ "fpadd16", F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H", 0, v9a },
1926{ "fpadd16s", F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g", 0, v9a },
1927{ "fpadd32", F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H", 0, v9a },
1928{ "fpadd32s", F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g", 0, v9a },
1929{ "fpsub16", F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H", 0, v9a },
1930{ "fpsub16s", F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g", 0, v9a },
1931{ "fpsub32", F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, v9a },
1932{ "fpsub32s", F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, v9a },
1933
1934{ "fpack32", F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, v9a },
1935{ "fpack16", F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0, "B,g", 0, v9a },
1936{ "fpackfix", F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0, "B,g", 0, v9a },
1937{ "fexpand", F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0, "f,H", 0, v9a },
1938{ "fpmerge", F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, v9a },
aa0aa4fa
FB		 1939
1940/* Note that the mixing of 32/64 bit regs is intentional. */
f930d07e
BS		 1941{ "fmul8x16", F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H", 0, v9a },
1942{ "fmul8x16au", F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H", 0, v9a },
1943{ "fmul8x16al", F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H", 0, v9a },
1944{ "fmul8sux16", F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H", 0, v9a },
1945{ "fmul8ulx16", F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H", 0, v9a },
1946{ "fmuld8sux16", F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H", 0, v9a },
1947{ "fmuld8ulx16", F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H", 0, v9a },
1948
1949{ "alignaddr", F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, v9a },
1950{ "alignaddrl", F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, v9a },
1951{ "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, v9a },
1952
1953{ "fzero", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, v9a },
1954{ "fzeros", F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, v9a },
1955{ "fone", F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, v9a },
1956{ "fones", F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, v9a },
1957{ "fsrc1", F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, v9a },
1958{ "fsrc1s", F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, v9a },
1959{ "fsrc2", F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, v9a },
1960{ "fsrc2s", F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, v9a },
1961{ "fnot1", F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, v9a },
1962{ "fnot1s", F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, v9a },
1963{ "fnot2", F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, v9a },
1964{ "fnot2s", F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, v9a },
1965{ "for", F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, v9a },
1966{ "fors", F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, v9a },
1967{ "fnor", F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, v9a },
1968{ "fnors", F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, v9a },
1969{ "fand", F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, v9a },
1970{ "fands", F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, v9a },
1971{ "fnand", F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, v9a },
1972{ "fnands", F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, v9a },
1973{ "fxor", F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, v9a },
1974{ "fxors", F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, v9a },
1975{ "fxnor", F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, v9a },
1976{ "fxnors", F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, v9a },
1977{ "fornot1", F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, v9a },
1978{ "fornot1s", F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, v9a },
1979{ "fornot2", F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, v9a },
1980{ "fornot2s", F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, v9a },
1981{ "fandnot1", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, v9a },
1982{ "fandnot1s", F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, v9a },
1983{ "fandnot2", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, v9a },
1984{ "fandnot2s", F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, v9a },
1985
1986{ "fcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, v9a },
1987{ "fcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, v9a },
1988{ "fcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, v9a },
1989{ "fcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, v9a },
1990{ "fcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, v9a },
1991{ "fcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, v9a },
1992{ "fcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, v9a },
1993{ "fcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, v9a },
1994
1995{ "edge8", F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, v9a },
1996{ "edge8l", F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, v9a },
1997{ "edge16", F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, v9a },
1998{ "edge16l", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, v9a },
1999{ "edge32", F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, v9a },
2000{ "edge32l", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, v9a },
2001
2002{ "pdist", F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, v9a },
2003
2004{ "array8", F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d", 0, v9a },
2005{ "array16", F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, v9a },
2006{ "array32", F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, v9a },
aa0aa4fa
FB		 2007
2008/* Cheetah instructions */
2009{ "edge8n", F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d", 0, v9b },
2010{ "edge8ln", F3F(2, 0x36, 0x003), F3F(~2, ~0x36, ~0x003), "1,2,d", 0, v9b },
2011{ "edge16n", F3F(2, 0x36, 0x005), F3F(~2, ~0x36, ~0x005), "1,2,d", 0, v9b },
2012{ "edge16ln", F3F(2, 0x36, 0x007), F3F(~2, ~0x36, ~0x007), "1,2,d", 0, v9b },
2013{ "edge32n", F3F(2, 0x36, 0x009), F3F(~2, ~0x36, ~0x009), "1,2,d", 0, v9b },
2014{ "edge32ln", F3F(2, 0x36, 0x00b), F3F(~2, ~0x36, ~0x00b), "1,2,d", 0, v9b },
2015
2016{ "bmask", F3F(2, 0x36, 0x019), F3F(~2, ~0x36, ~0x019), "1,2,d", 0, v9b },
2017{ "bshuffle", F3F(2, 0x36, 0x04c), F3F(~2, ~0x36, ~0x04c), "v,B,H", 0, v9b },
2018
2019{ "siam", F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0|RS1_G0|RS2(~7), "3", 0, v9b },
2020
2021/* More v9 specific insns, these need to come last so they do not clash
2022 with v9a instructions such as "edge8" which looks like impdep1. */
2023
2024#define IMPDEP(name, code) \
f930d07e
BS		 2025{ name, F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, v9notv9a }, \
2026{ name, F3(2, code, 1), F3(~2, ~code, ~1), "1,i,d", 0, v9notv9a }, \
aa0aa4fa
FB		 2027{ name, F3(2, code, 0), F3(~2, ~code, ~0), "x,1,2,d", 0, v9notv9a }, \
2028{ name, F3(2, code, 0), F3(~2, ~code, ~0), "x,e,f,g", 0, v9notv9a }
2029
2030IMPDEP ("impdep1", 0x36),
2031IMPDEP ("impdep2", 0x37),
2032
2033#undef IMPDEP
2034
90379ca8
RH		 2035{ "addxc", F3F(2, 0x36, 0x011), F3F(~2, ~0x36, ~0x011), "1,2,d", 0, v9b },
2036{ "addxccc", F3F(2, 0x36, 0x013), F3F(~2, ~0x36, ~0x013), "1,2,d", 0, v9b },
de8301e5 2037{ "umulxhi", F3F(2, 0x36, 0x016), F3F(~2, ~0x36, ~0x016), "1,2,d", 0, v9b },
90379ca8 2038
aa0aa4fa
FB		 2039};
2040
f82a3d48 2041static const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0]));
aa0aa4fa
FB		 2042\f
2043/* Utilities for argument parsing. */
2044
2045typedef struct
2046{
2047 int value;
2048 const char *name;
2049} arg;
2050
aa0aa4fa
FB		 2051/* Look up VALUE in TABLE. */
2052
2053static const char *
46f42f29 2054lookup_value (const arg *table, int value)
aa0aa4fa
FB		 2055{
2056 const arg *p;
2057
2058 for (p = table; p->name; ++p)
2059 if (value == p->value)
2060 return p->name;
2061
46f42f29 2062 return NULL;
aa0aa4fa
FB		 2063}
2064\f
2065/* Handle ASI's. */
2066
1983a395
FB		 2067static const arg asi_table_v8[] =
2068{
2069 { 0x00, "#ASI_M_RES00" },
2070 { 0x01, "#ASI_M_UNA01" },
2071 { 0x02, "#ASI_M_MXCC" },
2072 { 0x03, "#ASI_M_FLUSH_PROBE" },
2073 { 0x04, "#ASI_M_MMUREGS" },
2074 { 0x05, "#ASI_M_TLBDIAG" },
2075 { 0x06, "#ASI_M_DIAGS" },
2076 { 0x07, "#ASI_M_IODIAG" },
2077 { 0x08, "#ASI_M_USERTXT" },
2078 { 0x09, "#ASI_M_KERNELTXT" },
2079 { 0x0A, "#ASI_M_USERDATA" },
2080 { 0x0B, "#ASI_M_KERNELDATA" },
2081 { 0x0C, "#ASI_M_TXTC_TAG" },
2082 { 0x0D, "#ASI_M_TXTC_DATA" },
2083 { 0x0E, "#ASI_M_DATAC_TAG" },
2084 { 0x0F, "#ASI_M_DATAC_DATA" },
2085 { 0x10, "#ASI_M_FLUSH_PAGE" },
2086 { 0x11, "#ASI_M_FLUSH_SEG" },
2087 { 0x12, "#ASI_M_FLUSH_REGION" },
2088 { 0x13, "#ASI_M_FLUSH_CTX" },
2089 { 0x14, "#ASI_M_FLUSH_USER" },
2090 { 0x17, "#ASI_M_BCOPY" },
2091 { 0x18, "#ASI_M_IFLUSH_PAGE" },
2092 { 0x19, "#ASI_M_IFLUSH_SEG" },
2093 { 0x1A, "#ASI_M_IFLUSH_REGION" },
2094 { 0x1B, "#ASI_M_IFLUSH_CTX" },
2095 { 0x1C, "#ASI_M_IFLUSH_USER" },
2096 { 0x1F, "#ASI_M_BFILL" },
2097 { 0x20, "#ASI_M_BYPASS" },
2098 { 0x29, "#ASI_M_FBMEM" },
2099 { 0x2A, "#ASI_M_VMEUS" },
2100 { 0x2B, "#ASI_M_VMEPS" },
2101 { 0x2C, "#ASI_M_VMEUT" },
2102 { 0x2D, "#ASI_M_VMEPT" },
2103 { 0x2E, "#ASI_M_SBUS" },
2104 { 0x2F, "#ASI_M_CTL" },
2105 { 0x31, "#ASI_M_FLUSH_IWHOLE" },
2106 { 0x36, "#ASI_M_IC_FLCLEAR" },
2107 { 0x37, "#ASI_M_DC_FLCLEAR" },
2108 { 0x39, "#ASI_M_DCDR" },
2109 { 0x40, "#ASI_M_VIKING_TMP1" },
2110 { 0x41, "#ASI_M_VIKING_TMP2" },
2111 { 0x4c, "#ASI_M_ACTION" },
660f11be 2112 { 0, NULL }
1983a395
FB		 2113};
2114
2115static const arg asi_table_v9[] =
aa0aa4fa
FB		 2116{
2117 /* These are in the v9 architecture manual. */
2118 /* The shorter versions appear first, they're here because Sun's as has them.
2119 Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the
2120 UltraSPARC architecture manual). */
2121 { 0x04, "#ASI_N" },
2122 { 0x0c, "#ASI_N_L" },
2123 { 0x10, "#ASI_AIUP" },
2124 { 0x11, "#ASI_AIUS" },
2125 { 0x18, "#ASI_AIUP_L" },
2126 { 0x19, "#ASI_AIUS_L" },
2127 { 0x80, "#ASI_P" },
2128 { 0x81, "#ASI_S" },
2129 { 0x82, "#ASI_PNF" },
2130 { 0x83, "#ASI_SNF" },
2131 { 0x88, "#ASI_P_L" },
2132 { 0x89, "#ASI_S_L" },
2133 { 0x8a, "#ASI_PNF_L" },
2134 { 0x8b, "#ASI_SNF_L" },
2135 { 0x04, "#ASI_NUCLEUS" },
2136 { 0x0c, "#ASI_NUCLEUS_LITTLE" },
2137 { 0x10, "#ASI_AS_IF_USER_PRIMARY" },
2138 { 0x11, "#ASI_AS_IF_USER_SECONDARY" },
2139 { 0x18, "#ASI_AS_IF_USER_PRIMARY_LITTLE" },
2140 { 0x19, "#ASI_AS_IF_USER_SECONDARY_LITTLE" },
2141 { 0x80, "#ASI_PRIMARY" },
2142 { 0x81, "#ASI_SECONDARY" },
2143 { 0x82, "#ASI_PRIMARY_NOFAULT" },
2144 { 0x83, "#ASI_SECONDARY_NOFAULT" },
2145 { 0x88, "#ASI_PRIMARY_LITTLE" },
2146 { 0x89, "#ASI_SECONDARY_LITTLE" },
2147 { 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE" },
2148 { 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE" },
2149 /* These are UltraSPARC extensions. */
788686ec
IK		 2150 { 0x14, "#ASI_PHYS_USE_EC"},
2151 { 0x15, "#ASI_PHYS_BYPASS_EC_WITH_EBIT"},
2152 { 0x45, "#ASI_LSU_CONTROL_REG"},
2153 { 0x47, "#ASI_DCACHE_TAG"},
2154 { 0x4a, "#ASI_UPA_CONFIG_REG"},
2155 { 0x50, "#ASI_IMMU" },
2156 { 0x51, "#ASI_IMMU_TSB_8KB_PTR_REG" },
2157 { 0x52, "#ASI_IMMU_TSB_64KB_PTR_REG" },
2158 /*{ 0x53, "#reserved?" },*/
2159 { 0x54, "#ASI_ITLB_DATA_IN_REG" },
2160 { 0x55, "#ASI_ITLB_DATA_ACCESS_REG" },
2161 { 0x56, "#ASI_ITLB_TAG_READ_REG" },
2162 { 0x57, "#ASI_IMMU_DEMAP" },
2163 { 0x58, "#ASI_DMMU" },
2164 { 0x59, "#ASI_DMMU_TSB_8KB_PTR_REG" },
2165 { 0x5a, "#ASI_DMMU_TSB_64KB_PTR_REG" },
2166 { 0x5b, "#ASI_DMMU_TSB_DIRECT_PTR_REG" },
2167 { 0x5c, "#ASI_DTLB_DATA_IN_REG" },
2168 { 0x5d, "#ASI_DTLB_DATA_ACCESS_REG" },
2169 { 0x5e, "#ASI_DTLB_TAG_READ_REG" },
2170 { 0x5f, "#ASI_DMMU_DEMAP" },
2171 { 0x67, "#ASI_IC_TAG"},
aa0aa4fa
FB		 2172 /* FIXME: There are dozens of them. Not sure we want them all.
2173 Most are for kernel building but some are for vis type stuff. */
660f11be 2174 { 0, NULL }
aa0aa4fa
FB		 2175};
2176
1983a395 2177/* Return the name for ASI value VALUE or NULL if not found. */
aa0aa4fa 2178
1983a395
FB		 2179static const char *
2180sparc_decode_asi_v9 (int value)
aa0aa4fa 2181{
1983a395 2182 return lookup_value (asi_table_v9, value);
aa0aa4fa
FB		 2183}
2184
1983a395
FB		 2185static const char *
2186sparc_decode_asi_v8 (int value)
aa0aa4fa 2187{
1983a395 2188 return lookup_value (asi_table_v8, value);
aa0aa4fa
FB		 2189}
2190\f
2191/* Handle membar masks. */
2192
d88bbf95 2193static const arg membar_table[] =
aa0aa4fa
FB		 2194{
2195 { 0x40, "#Sync" },
2196 { 0x20, "#MemIssue" },
2197 { 0x10, "#Lookaside" },
2198 { 0x08, "#StoreStore" },
2199 { 0x04, "#LoadStore" },
2200 { 0x02, "#StoreLoad" },
2201 { 0x01, "#LoadLoad" },
660f11be 2202 { 0, NULL }
aa0aa4fa
FB		 2203};
2204
aa0aa4fa
FB		 2205/* Return the name for membar value VALUE or NULL if not found. */
2206
b1d8e52e 2207static const char *
46f42f29 2208sparc_decode_membar (int value)
aa0aa4fa
FB		 2209{
2210 return lookup_value (membar_table, value);
2211}
2212\f
2213/* Handle prefetch args. */
2214
d88bbf95 2215static const arg prefetch_table[] =
aa0aa4fa
FB		 2216{
2217 { 0, "#n_reads" },
2218 { 1, "#one_read" },
2219 { 2, "#n_writes" },
2220 { 3, "#one_write" },
2221 { 4, "#page" },
2222 { 16, "#invalidate" },
660f11be 2223 { 0, NULL }
aa0aa4fa
FB		 2224};
2225
aa0aa4fa
FB		 2226/* Return the name for prefetch value VALUE or NULL if not found. */
2227
b1d8e52e 2228static const char *
46f42f29 2229sparc_decode_prefetch (int value)
aa0aa4fa
FB		 2230{
2231 return lookup_value (prefetch_table, value);
2232}
2233\f
2234/* Handle sparclet coprocessor registers. */
2235
d88bbf95 2236static const arg sparclet_cpreg_table[] =
aa0aa4fa
FB		 2237{
2238 { 0, "%ccsr" },
2239 { 1, "%ccfr" },
2240 { 2, "%cccrcr" },
2241 { 3, "%ccpr" },
2242 { 4, "%ccsr2" },
2243 { 5, "%cccrr" },
2244 { 6, "%ccrstr" },
660f11be 2245 { 0, NULL }
aa0aa4fa
FB		 2246};
2247
aa0aa4fa
FB		 2248/* Return the name for sparclet cpreg value VALUE or NULL if not found. */
2249
b1d8e52e 2250static const char *
46f42f29 2251sparc_decode_sparclet_cpreg (int value)
aa0aa4fa
FB		 2252{
2253 return lookup_value (sparclet_cpreg_table, value);
2254}
2255
2256#undef MASK_V9
2257
d4abd567
BS		 2258/* opcodes/sparc-dis.c */
2259
46f42f29
BS		 2260/* Print SPARC instructions.
2261 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
2262 2000, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
2263
2264 This program is free software; you can redistribute it and/or modify
2265 it under the terms of the GNU General Public License as published by
2266 the Free Software Foundation; either version 2 of the License, or
2267 (at your option) any later version.
2268
2269 This program is distributed in the hope that it will be useful,
2270 but WITHOUT ANY WARRANTY; without even the implied warranty of
2271 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2272 GNU General Public License for more details.
2273
2274 You should have received a copy of the GNU General Public License
8167ee88 2275 along with this program; if not, see <http://www.gnu.org/licenses/>. */
46f42f29 2276
aa0aa4fa
FB		 2277/* Bitmask of v9 architectures. */
2278#define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
f930d07e
BS		 2279 | (1 << SPARC_OPCODE_ARCH_V9A) \
2280 | (1 << SPARC_OPCODE_ARCH_V9B))
aa0aa4fa
FB		 2281/* 1 if INSN is for v9 only. */
2282#define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
2283/* 1 if INSN is for v9. */
2284#define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
2285
2286/* The sorted opcode table. */
46f42f29 2287static const sparc_opcode **sorted_opcodes;
aa0aa4fa
FB		 2288
2289/* For faster lookup, after insns are sorted they are hashed. */
2290/* ??? I think there is room for even more improvement. */
2291
2292#define HASH_SIZE 256
2293/* It is important that we only look at insn code bits as that is how the
2294 opcode table is hashed. OPCODE_BITS is a table of valid bits for each
2295 of the main types (0,1,2,3). */
d88bbf95 2296static const int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
aa0aa4fa
FB		 2297#define HASH_INSN(INSN) \
2298 ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
46f42f29
BS		 2299typedef struct sparc_opcode_hash
2300{
2301 struct sparc_opcode_hash *next;
2302 const sparc_opcode *opcode;
2303} sparc_opcode_hash;
aa0aa4fa 2304
46f42f29 2305static sparc_opcode_hash *opcode_hash_table[HASH_SIZE];
aa0aa4fa
FB		 2306
2307/* Sign-extend a value which is N bits long. */
f930d07e
BS		 2308#define SEX(value, bits) \
2309 ((((int)(value)) << ((8 * sizeof (int)) - bits)) \
2310 >> ((8 * sizeof (int)) - bits) )
aa0aa4fa 2311
d88bbf95 2312static const char * const reg_names[] =
5fafdf24
TS		 2313{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2314 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2315 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2316 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2317 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2318 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
aa0aa4fa
FB		 2319 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2320 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5fafdf24
TS		 2321 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
2322 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
aa0aa4fa
FB		 2323 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
2324 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
2325/* psr, wim, tbr, fpsr, cpsr are v8 only. */
2326 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
2327};
2328
f930d07e 2329#define freg_names (&reg_names[4 * 8])
aa0aa4fa
FB		 2330
2331/* These are ordered according to there register number in
2332 rdpr and wrpr insns. */
d88bbf95 2333static const char * const v9_priv_reg_names[] =
aa0aa4fa
FB		 2334{
2335 "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
2336 "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
46f42f29 2337 "wstate", "fq", "gl"
aa0aa4fa
FB		 2338 /* "ver" - special cased */
2339};
2340
46f42f29
BS		 2341/* These are ordered according to there register number in
2342 rdhpr and wrhpr insns. */
2343static const char * const v9_hpriv_reg_names[] =
2344{
2345 "hpstate", "htstate", "resv2", "hintp", "resv4", "htba", "hver",
2346 "resv7", "resv8", "resv9", "resv10", "resv11", "resv12", "resv13",
2347 "resv14", "resv15", "resv16", "resv17", "resv18", "resv19", "resv20",
2348 "resv21", "resv22", "resv23", "resv24", "resv25", "resv26", "resv27",
2349 "resv28", "resv29", "resv30", "hstick_cmpr"
2350};
2351
aa0aa4fa
FB		 2352/* These are ordered according to there register number in
2353 rd and wr insns (-16). */
d88bbf95 2354static const char * const v9a_asr_reg_names[] =
aa0aa4fa
FB		 2355{
2356 "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
2357 "softint", "tick_cmpr", "sys_tick", "sys_tick_cmpr"
2358};
2359
2360/* Macros used to extract instruction fields. Not all fields have
2361 macros defined here, only those which are actually used. */
2362
46f42f29
BS		 2363#define X_RD(i) (((i) >> 25) & 0x1f)
2364#define X_RS1(i) (((i) >> 14) & 0x1f)
2365#define X_LDST_I(i) (((i) >> 13) & 1)
2366#define X_ASI(i) (((i) >> 5) & 0xff)
2367#define X_RS2(i) (((i) >> 0) & 0x1f)
2368#define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1))
2369#define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n))
2370#define X_DISP22(i) (((i) >> 0) & 0x3fffff)
2371#define X_IMM22(i) X_DISP22 (i)
2372#define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
aa0aa4fa
FB		 2373
2374/* These are for v9. */
46f42f29
BS		 2375#define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
2376#define X_DISP19(i) (((i) >> 0) & 0x7ffff)
2377#define X_MEMBAR(i) ((i) & 0x7f)
aa0aa4fa
FB		 2378
2379/* Here is the union which was used to extract instruction fields
2380 before the shift and mask macros were written.
2381
2382 union sparc_insn
2383 {
2384 unsigned long int code;
2385 struct
f930d07e
BS		 2386 {
2387 unsigned int anop:2;
2388 #define op ldst.anop
2389 unsigned int anrd:5;
2390 #define rd ldst.anrd
2391 unsigned int op3:6;
2392 unsigned int anrs1:5;
2393 #define rs1 ldst.anrs1
2394 unsigned int i:1;
2395 unsigned int anasi:8;
2396 #define asi ldst.anasi
2397 unsigned int anrs2:5;
2398 #define rs2 ldst.anrs2
2399 #define shcnt rs2
2400 } ldst;
aa0aa4fa 2401 struct
f930d07e
BS		 2402 {
2403 unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
2404 unsigned int IMM13:13;
2405 #define imm13 IMM13.IMM13
2406 } IMM13;
aa0aa4fa 2407 struct
f930d07e
BS		 2408 {
2409 unsigned int anop:2;
2410 unsigned int a:1;
2411 unsigned int cond:4;
2412 unsigned int op2:3;
2413 unsigned int DISP22:22;
2414 #define disp22 branch.DISP22
2415 #define imm22 disp22
2416 } branch;
aa0aa4fa 2417 struct
f930d07e
BS		 2418 {
2419 unsigned int anop:2;
2420 unsigned int a:1;
2421 unsigned int z:1;
2422 unsigned int rcond:3;
2423 unsigned int op2:3;
2424 unsigned int DISP16HI:2;
2425 unsigned int p:1;
2426 unsigned int _rs1:5;
2427 unsigned int DISP16LO:14;
2428 } branch16;
aa0aa4fa 2429 struct
f930d07e
BS		 2430 {
2431 unsigned int anop:2;
2432 unsigned int adisp30:30;
2433 #define disp30 call.adisp30
2434 } call;
46f42f29 2435 }; */
aa0aa4fa
FB		 2436
2437/* Nonzero if INSN is the opcode for a delayed branch. */
46f42f29 2438
aa0aa4fa 2439static int
46f42f29 2440is_delayed_branch (unsigned long insn)
aa0aa4fa 2441{
46f42f29 2442 sparc_opcode_hash *op;
aa0aa4fa
FB		 2443
2444 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
2445 {
46f42f29
BS		 2446 const sparc_opcode *opcode = op->opcode;
2447
aa0aa4fa 2448 if ((opcode->match & insn) == opcode->match
f930d07e 2449 && (opcode->lose & insn) == 0)
46f42f29 2450 return opcode->flags & F_DELAYED;
aa0aa4fa
FB		 2451 }
2452 return 0;
2453}
2454
2455/* extern void qsort (); */
2456
2457/* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value
2458 to compare_opcodes. */
2459static unsigned int current_arch_mask;
2460
46f42f29
BS		 2461/* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */
2462
2463static int
2464compute_arch_mask (unsigned long mach)
2465{
2466 switch (mach)
2467 {
2468 case 0 :
2469 case bfd_mach_sparc :
2470 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8);
2471 case bfd_mach_sparc_sparclet :
2472 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
2473 case bfd_mach_sparc_sparclite :
2474 case bfd_mach_sparc_sparclite_le :
2475 /* sparclites insns are recognized by default (because that's how
2476 they've always been treated, for better or worse). Kludge this by
2477 indicating generic v8 is also selected. */
2478 return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
2479 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8));
2480 case bfd_mach_sparc_v8plus :
2481 case bfd_mach_sparc_v9 :
2482 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
2483 case bfd_mach_sparc_v8plusa :
2484 case bfd_mach_sparc_v9a :
2485 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
2486 case bfd_mach_sparc_v8plusb :
2487 case bfd_mach_sparc_v9b :
2488 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);
2489 }
2490 abort ();
2491}
2492
2493/* Compare opcodes A and B. */
2494
2495static int
2496compare_opcodes (const void * a, const void * b)
2497{
2498 sparc_opcode *op0 = * (sparc_opcode **) a;
2499 sparc_opcode *op1 = * (sparc_opcode **) b;
2500 unsigned long int match0 = op0->match, match1 = op1->match;
2501 unsigned long int lose0 = op0->lose, lose1 = op1->lose;
2502 register unsigned int i;
2503
2504 /* If one (and only one) insn isn't supported by the current architecture,
2505 prefer the one that is. If neither are supported, but they're both for
2506 the same architecture, continue processing. Otherwise (both unsupported
2507 and for different architectures), prefer lower numbered arch's (fudged
2508 by comparing the bitmasks). */
2509 if (op0->architecture & current_arch_mask)
2510 {
2511 if (! (op1->architecture & current_arch_mask))
2512 return -1;
2513 }
2514 else
2515 {
2516 if (op1->architecture & current_arch_mask)
2517 return 1;
2518 else if (op0->architecture != op1->architecture)
2519 return op0->architecture - op1->architecture;
2520 }
2521
2522 /* If a bit is set in both match and lose, there is something
2523 wrong with the opcode table. */
2524 if (match0 & lose0)
2525 {
2526 fprintf
2527 (stderr,
2528 /* xgettext:c-format */
2529 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
2530 op0->name, match0, lose0);
2531 op0->lose &= ~op0->match;
2532 lose0 = op0->lose;
2533 }
2534
2535 if (match1 & lose1)
2536 {
2537 fprintf
2538 (stderr,
2539 /* xgettext:c-format */
2540 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
2541 op1->name, match1, lose1);
2542 op1->lose &= ~op1->match;
2543 lose1 = op1->lose;
2544 }
2545
2546 /* Because the bits that are variable in one opcode are constant in
2547 another, it is important to order the opcodes in the right order. */
2548 for (i = 0; i < 32; ++i)
2549 {
2550 unsigned long int x = 1 << i;
2551 int x0 = (match0 & x) != 0;
2552 int x1 = (match1 & x) != 0;
2553
2554 if (x0 != x1)
2555 return x1 - x0;
2556 }
2557
2558 for (i = 0; i < 32; ++i)
2559 {
2560 unsigned long int x = 1 << i;
2561 int x0 = (lose0 & x) != 0;
2562 int x1 = (lose1 & x) != 0;
2563
2564 if (x0 != x1)
2565 return x1 - x0;
2566 }
2567
2568 /* They are functionally equal. So as long as the opcode table is
2569 valid, we can put whichever one first we want, on aesthetic grounds. */
2570
2571 /* Our first aesthetic ground is that aliases defer to real insns. */
2572 {
2573 int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
2574
2575 if (alias_diff != 0)
2576 /* Put the one that isn't an alias first. */
2577 return alias_diff;
2578 }
2579
2580 /* Except for aliases, two "identical" instructions had
2581 better have the same opcode. This is a sanity check on the table. */
2582 i = strcmp (op0->name, op1->name);
2583 if (i)
2584 {
2585 if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */
2586 return i;
2587 else
2588 fprintf (stderr,
2589 /* xgettext:c-format */
2590 _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
2591 op0->name, op1->name);
2592 }
2593
2594 /* Fewer arguments are preferred. */
2595 {
2596 int length_diff = strlen (op0->args) - strlen (op1->args);
2597
2598 if (length_diff != 0)
2599 /* Put the one with fewer arguments first. */
2600 return length_diff;
2601 }
2602
2603 /* Put 1+i before i+1. */
2604 {
2605 char *p0 = (char *) strchr (op0->args, '+');
2606 char *p1 = (char *) strchr (op1->args, '+');
2607
2608 if (p0 && p1)
2609 {
2610 /* There is a plus in both operands. Note that a plus
2611 sign cannot be the first character in args,
2612 so the following [-1]'s are valid. */
2613 if (p0[-1] == 'i' && p1[1] == 'i')
2614 /* op0 is i+1 and op1 is 1+i, so op1 goes first. */
2615 return 1;
2616 if (p0[1] == 'i' && p1[-1] == 'i')
2617 /* op0 is 1+i and op1 is i+1, so op0 goes first. */
2618 return -1;
2619 }
2620 }
2621
2622 /* Put 1,i before i,1. */
2623 {
2624 int i0 = strncmp (op0->args, "i,1", 3) == 0;
2625 int i1 = strncmp (op1->args, "i,1", 3) == 0;
2626
2627 if (i0 ^ i1)
2628 return i0 - i1;
2629 }
2630
2631 /* They are, as far as we can tell, identical.
2632 Since qsort may have rearranged the table partially, there is
2633 no way to tell which one was first in the opcode table as
2634 written, so just say there are equal. */
2635 /* ??? This is no longer true now that we sort a vector of pointers,
2636 not the table itself. */
2637 return 0;
2638}
2639
2640/* Build a hash table from the opcode table.
2641 OPCODE_TABLE is a sorted list of pointers into the opcode table. */
2642
2643static void
2644build_hash_table (const sparc_opcode **opcode_table,
2645 sparc_opcode_hash **hash_table,
2646 int num_opcodes)
2647{
2648 int i;
2649 int hash_count[HASH_SIZE];
2650 static sparc_opcode_hash *hash_buf = NULL;
2651
2652 /* Start at the end of the table and work backwards so that each
2653 chain is sorted. */
2654
2655 memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
2656 memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
2657 if (hash_buf != NULL)
2658 free (hash_buf);
2659 hash_buf = malloc (sizeof (* hash_buf) * num_opcodes);
2660 for (i = num_opcodes - 1; i >= 0; --i)
2661 {
2662 int hash = HASH_INSN (opcode_table[i]->match);
2663 sparc_opcode_hash *h = &hash_buf[i];
2664
2665 h->next = hash_table[hash];
2666 h->opcode = opcode_table[i];
2667 hash_table[hash] = h;
2668 ++hash_count[hash];
2669 }
2670
2671#if 0 /* for debugging */
2672 {
2673 int min_count = num_opcodes, max_count = 0;
2674 int total;
2675
2676 for (i = 0; i < HASH_SIZE; ++i)
2677 {
2678 if (hash_count[i] < min_count)
2679 min_count = hash_count[i];
2680 if (hash_count[i] > max_count)
2681 max_count = hash_count[i];
2682 total += hash_count[i];
2683 }
2684
2685 printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
2686 min_count, max_count, (double) total / HASH_SIZE);
2687 }
2688#endif
2689}
2690
aa0aa4fa
FB		 2691/* Print one instruction from MEMADDR on INFO->STREAM.
2692
2693 We suffix the instruction with a comment that gives the absolute
2694 address involved, as well as its symbolic form, if the instruction
2695 is preceded by a findable `sethi' and it either adds an immediate
2696 displacement to that register, or it is an `add' or `or' instruction
2697 on that register. */
2698
2699int
46f42f29 2700print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
aa0aa4fa
FB		 2701{
2702 FILE *stream = info->stream;
2703 bfd_byte buffer[4];
2704 unsigned long insn;
46f42f29 2705 sparc_opcode_hash *op;
aa0aa4fa
FB		 2706 /* Nonzero of opcode table has been initialized. */
2707 static int opcodes_initialized = 0;
2708 /* bfd mach number of last call. */
2709 static unsigned long current_mach = 0;
46f42f29 2710 bfd_vma (*getword) (const unsigned char *);
aa0aa4fa
FB		 2711
2712 if (!opcodes_initialized
2713 || info->mach != current_mach)
2714 {
2715 int i;
2716
2717 current_arch_mask = compute_arch_mask (info->mach);
2718
2719 if (!opcodes_initialized)
46f42f29
BS		 2720 sorted_opcodes =
2721 malloc (sparc_num_opcodes * sizeof (sparc_opcode *));
aa0aa4fa
FB		 2722 /* Reset the sorted table so we can resort it. */
2723 for (i = 0; i < sparc_num_opcodes; ++i)
f930d07e 2724 sorted_opcodes[i] = &sparc_opcodes[i];
aa0aa4fa 2725 qsort ((char *) sorted_opcodes, sparc_num_opcodes,
f930d07e 2726 sizeof (sorted_opcodes[0]), compare_opcodes);
aa0aa4fa
FB		 2727
2728 build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes);
2729 current_mach = info->mach;
2730 opcodes_initialized = 1;
2731 }
2732
2733 {
2734 int status =
2735 (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
46f42f29 2736
aa0aa4fa
FB		 2737 if (status != 0)
2738 {
f930d07e
BS		 2739 (*info->memory_error_func) (status, memaddr, info);
2740 return -1;
aa0aa4fa
FB		 2741 }
2742 }
2743
2744 /* On SPARClite variants such as DANlite (sparc86x), instructions
46f42f29 2745 are always big-endian even when the machine is in little-endian mode. */
aa0aa4fa
FB		 2746 if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite)
2747 getword = bfd_getb32;
2748 else
2749 getword = bfd_getl32;
2750
2751 insn = getword (buffer);
2752
46f42f29
BS		 2753 info->insn_info_valid = 1; /* We do return this info. */
2754 info->insn_type = dis_nonbranch; /* Assume non branch insn. */
2755 info->branch_delay_insns = 0; /* Assume no delay. */
2756 info->target = 0; /* Assume no target known. */
aa0aa4fa
FB		 2757
2758 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
2759 {
46f42f29 2760 const sparc_opcode *opcode = op->opcode;
aa0aa4fa
FB		 2761
2762 /* If the insn isn't supported by the current architecture, skip it. */
2763 if (! (opcode->architecture & current_arch_mask))
f930d07e 2764 continue;
aa0aa4fa
FB		 2765
2766 if ((opcode->match & insn) == opcode->match
f930d07e
BS		 2767 && (opcode->lose & insn) == 0)
2768 {
2769 /* Nonzero means that we have found an instruction which has
2770 the effect of adding or or'ing the imm13 field to rs1. */
2771 int imm_added_to_rs1 = 0;
2772 int imm_ored_to_rs1 = 0;
aa0aa4fa 2773
f930d07e
BS		 2774 /* Nonzero means that we have found a plus sign in the args
2775 field of the opcode table. */
2776 int found_plus = 0;
3b46e624 2777
f930d07e 2778 /* Nonzero means we have an annulled branch. */
a9be79d6 2779 /* int is_annulled = 0; */ /* see FIXME below */
aa0aa4fa 2780
f930d07e 2781 /* Do we have an `add' or `or' instruction combining an
aa0aa4fa 2782 immediate with rs1? */
f930d07e
BS		 2783 if (opcode->match == 0x80102000) /* or */
2784 imm_ored_to_rs1 = 1;
2785 if (opcode->match == 0x80002000) /* add */
2786 imm_added_to_rs1 = 1;
2787
2788 if (X_RS1 (insn) != X_RD (insn)
660f11be 2789 && strchr (opcode->args, 'r') != NULL)
f930d07e
BS		 2790 /* Can't do simple format if source and dest are different. */
2791 continue;
2792 if (X_RS2 (insn) != X_RD (insn)
660f11be 2793 && strchr (opcode->args, 'O') != NULL)
f930d07e
BS		 2794 /* Can't do simple format if source and dest are different. */
2795 continue;
2796
452f58eb 2797 (*info->fprintf_func) (stream, "%s", opcode->name);
f930d07e
BS		 2798
2799 {
46f42f29 2800 const char *s;
f930d07e
BS		 2801
2802 if (opcode->args[0] != ',')
2803 (*info->fprintf_func) (stream, " ");
46f42f29 2804
f930d07e
BS		 2805 for (s = opcode->args; *s != '\0'; ++s)
2806 {
2807 while (*s == ',')
2808 {
2809 (*info->fprintf_func) (stream, ",");
2810 ++s;
46f42f29
BS		 2811 switch (*s)
2812 {
2813 case 'a':
2814 (*info->fprintf_func) (stream, "a");
a9be79d6 2815 /* is_annulled = 1; */ /* see FIXME below */
46f42f29
BS		 2816 ++s;
2817 continue;
2818 case 'N':
2819 (*info->fprintf_func) (stream, "pn");
2820 ++s;
2821 continue;
2822
2823 case 'T':
2824 (*info->fprintf_func) (stream, "pt");
2825 ++s;
2826 continue;
2827
2828 default:
2829 break;
2830 }
2831 }
f930d07e
BS		 2832
2833 (*info->fprintf_func) (stream, " ");
2834
2835 switch (*s)
2836 {
2837 case '+':
2838 found_plus = 1;
46f42f29 2839 /* Fall through. */
f930d07e 2840
f930d07e
BS		 2841 default:
2842 (*info->fprintf_func) (stream, "%c", *s);
2843 break;
2844
2845 case '#':
2846 (*info->fprintf_func) (stream, "0");
2847 break;
2848
2849#define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n])
2850 case '1':
2851 case 'r':
2852 reg (X_RS1 (insn));
2853 break;
2854
2855 case '2':
2856 case 'O':
2857 reg (X_RS2 (insn));
2858 break;
2859
2860 case 'd':
2861 reg (X_RD (insn));
2862 break;
2863#undef reg
2864
2865#define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n])
2866#define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)])
2867 case 'e':
2868 freg (X_RS1 (insn));
2869 break;
46f42f29
BS		 2870 case 'v': /* Double/even. */
2871 case 'V': /* Quad/multiple of 4. */
f930d07e
BS		 2872 fregx (X_RS1 (insn));
2873 break;
2874
2875 case 'f':
2876 freg (X_RS2 (insn));
2877 break;
46f42f29
BS		 2878 case 'B': /* Double/even. */
2879 case 'R': /* Quad/multiple of 4. */
f930d07e
BS		 2880 fregx (X_RS2 (insn));
2881 break;
2882
2883 case 'g':
2884 freg (X_RD (insn));
2885 break;
46f42f29
BS		 2886 case 'H': /* Double/even. */
2887 case 'J': /* Quad/multiple of 4. */
f930d07e
BS		 2888 fregx (X_RD (insn));
2889 break;
2890#undef freg
2891#undef fregx
2892
2893#define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
2894 case 'b':
2895 creg (X_RS1 (insn));
2896 break;
2897
2898 case 'c':
2899 creg (X_RS2 (insn));
2900 break;
2901
2902 case 'D':
2903 creg (X_RD (insn));
2904 break;
2905#undef creg
2906
2907 case 'h':
2908 (*info->fprintf_func) (stream, "%%hi(%#x)",
2909 ((unsigned) 0xFFFFFFFF
2910 & ((int) X_IMM22 (insn) << 10)));
2911 break;
2912
46f42f29
BS		 2913 case 'i': /* 13 bit immediate. */
2914 case 'I': /* 11 bit immediate. */
2915 case 'j': /* 10 bit immediate. */
f930d07e
BS		 2916 {
2917 int imm;
2918
2919 if (*s == 'i')
2920 imm = X_SIMM (insn, 13);
2921 else if (*s == 'I')
2922 imm = X_SIMM (insn, 11);
2923 else
2924 imm = X_SIMM (insn, 10);
2925
2926 /* Check to see whether we have a 1+i, and take
2927 note of that fact.
2928
2929 Note: because of the way we sort the table,
2930 we will be matching 1+i rather than i+1,
2931 so it is OK to assume that i is after +,
2932 not before it. */
2933 if (found_plus)
2934 imm_added_to_rs1 = 1;
2935
2936 if (imm <= 9)
2937 (*info->fprintf_func) (stream, "%d", imm);
2938 else
2939 (*info->fprintf_func) (stream, "%#x", imm);
2940 }
2941 break;
2942
46f42f29
BS		 2943 case 'X': /* 5 bit unsigned immediate. */
2944 case 'Y': /* 6 bit unsigned immediate. */
f930d07e
BS		 2945 {
2946 int imm = X_IMM (insn, *s == 'X' ? 5 : 6);
2947
2948 if (imm <= 9)
2949 (info->fprintf_func) (stream, "%d", imm);
2950 else
2951 (info->fprintf_func) (stream, "%#x", (unsigned) imm);
2952 }
2953 break;
2954
2955 case '3':
46f42f29 2956 (info->fprintf_func) (stream, "%ld", X_IMM (insn, 3));
f930d07e
BS		 2957 break;
2958
2959 case 'K':
2960 {
2961 int mask = X_MEMBAR (insn);
2962 int bit = 0x40, printed_one = 0;
2963 const char *name;
2964
2965 if (mask == 0)
2966 (info->fprintf_func) (stream, "0");
2967 else
2968 while (bit)
2969 {
2970 if (mask & bit)
2971 {
2972 if (printed_one)
2973 (info->fprintf_func) (stream, "|");
2974 name = sparc_decode_membar (bit);
2975 (info->fprintf_func) (stream, "%s", name);
2976 printed_one = 1;
2977 }
2978 bit >>= 1;
2979 }
2980 break;
2981 }
2982
2983 case 'k':
2984 info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4;
2985 (*info->print_address_func) (info->target, info);
2986 break;
2987
2988 case 'G':
2989 info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4;
2990 (*info->print_address_func) (info->target, info);
2991 break;
2992
2993 case '6':
2994 case '7':
2995 case '8':
2996 case '9':
2997 (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0');
2998 break;
2999
3000 case 'z':
3001 (*info->fprintf_func) (stream, "%%icc");
3002 break;
3003
3004 case 'Z':
3005 (*info->fprintf_func) (stream, "%%xcc");
3006 break;
3007
3008 case 'E':
3009 (*info->fprintf_func) (stream, "%%ccr");
3010 break;
3011
3012 case 's':
3013 (*info->fprintf_func) (stream, "%%fprs");
3014 break;
3015
3016 case 'o':
3017 (*info->fprintf_func) (stream, "%%asi");
3018 break;
3019
3020 case 'W':
3021 (*info->fprintf_func) (stream, "%%tick");
3022 break;
3023
3024 case 'P':
3025 (*info->fprintf_func) (stream, "%%pc");
3026 break;
3027
3028 case '?':
3029 if (X_RS1 (insn) == 31)
3030 (*info->fprintf_func) (stream, "%%ver");
46f42f29 3031 else if ((unsigned) X_RS1 (insn) < 17)
f930d07e
BS		 3032 (*info->fprintf_func) (stream, "%%%s",
3033 v9_priv_reg_names[X_RS1 (insn)]);
3034 else
3035 (*info->fprintf_func) (stream, "%%reserved");
3036 break;
3037
3038 case '!':
46f42f29 3039 if ((unsigned) X_RD (insn) < 17)
f930d07e
BS		 3040 (*info->fprintf_func) (stream, "%%%s",
3041 v9_priv_reg_names[X_RD (insn)]);
3042 else
3043 (*info->fprintf_func) (stream, "%%reserved");
3044 break;
3045
46f42f29
BS		 3046 case '$':
3047 if ((unsigned) X_RS1 (insn) < 32)
3048 (*info->fprintf_func) (stream, "%%%s",
3049 v9_hpriv_reg_names[X_RS1 (insn)]);
3050 else
3051 (*info->fprintf_func) (stream, "%%reserved");
3052 break;
3053
3054 case '%':
3055 if ((unsigned) X_RD (insn) < 32)
3056 (*info->fprintf_func) (stream, "%%%s",
3057 v9_hpriv_reg_names[X_RD (insn)]);
3058 else
3059 (*info->fprintf_func) (stream, "%%reserved");
3060 break;
3061
f930d07e
BS		 3062 case '/':
3063 if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25)
3064 (*info->fprintf_func) (stream, "%%reserved");
3065 else
3066 (*info->fprintf_func) (stream, "%%%s",
3067 v9a_asr_reg_names[X_RS1 (insn)-16]);
3068 break;
3069
3070 case '_':
3071 if (X_RD (insn) < 16 || X_RD (insn) > 25)
3072 (*info->fprintf_func) (stream, "%%reserved");
3073 else
3074 (*info->fprintf_func) (stream, "%%%s",
3075 v9a_asr_reg_names[X_RD (insn)-16]);
3076 break;
3077
3078 case '*':
3079 {
3080 const char *name = sparc_decode_prefetch (X_RD (insn));
3081
3082 if (name)
3083 (*info->fprintf_func) (stream, "%s", name);
3084 else
46f42f29 3085 (*info->fprintf_func) (stream, "%ld", X_RD (insn));
f930d07e
BS		 3086 break;
3087 }
3088
3089 case 'M':
46f42f29 3090 (*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn));
f930d07e
BS		 3091 break;
3092
3093 case 'm':
46f42f29 3094 (*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn));
f930d07e
BS		 3095 break;
3096
3097 case 'L':
3098 info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
3099 (*info->print_address_func) (info->target, info);
3100 break;
3101
3102 case 'n':
3103 (*info->fprintf_func)
3104 (stream, "%#x", SEX (X_DISP22 (insn), 22));
3105 break;
3106
3107 case 'l':
3108 info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4;
3109 (*info->print_address_func) (info->target, info);
3110 break;
3111
3112 case 'A':
3113 {
3114 const char *name;
3115
3116 if ((info->mach == bfd_mach_sparc_v8plusa) ||
725cb90b
FB		 3117 ((info->mach >= bfd_mach_sparc_v9) &&
3118 (info->mach <= bfd_mach_sparc_v9b)))
f930d07e
BS		 3119 name = sparc_decode_asi_v9 (X_ASI (insn));
3120 else
3121 name = sparc_decode_asi_v8 (X_ASI (insn));
3122
3123 if (name)
3124 (*info->fprintf_func) (stream, "%s", name);
3125 else
46f42f29 3126 (*info->fprintf_func) (stream, "(%ld)", X_ASI (insn));
f930d07e
BS		 3127 break;
3128 }
3129
3130 case 'C':
3131 (*info->fprintf_func) (stream, "%%csr");
3132 break;
3133
3134 case 'F':
3135 (*info->fprintf_func) (stream, "%%fsr");
3136 break;
3137
3138 case 'p':
3139 (*info->fprintf_func) (stream, "%%psr");
3140 break;
3141
3142 case 'q':
3143 (*info->fprintf_func) (stream, "%%fq");
3144 break;
3145
3146 case 'Q':
3147 (*info->fprintf_func) (stream, "%%cq");
3148 break;
3149
3150 case 't':
3151 (*info->fprintf_func) (stream, "%%tbr");
3152 break;
3153
3154 case 'w':
3155 (*info->fprintf_func) (stream, "%%wim");
3156 break;
3157
3158 case 'x':
46f42f29 3159 (*info->fprintf_func) (stream, "%ld",
f930d07e
BS		 3160 ((X_LDST_I (insn) << 8)
3161 + X_ASI (insn)));
3162 break;
3163
3164 case 'y':
3165 (*info->fprintf_func) (stream, "%%y");
3166 break;
3167
3168 case 'u':
3169 case 'U':
3170 {
3171 int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn);
3172 const char *name = sparc_decode_sparclet_cpreg (val);
3173
3174 if (name)
3175 (*info->fprintf_func) (stream, "%s", name);
3176 else
3177 (*info->fprintf_func) (stream, "%%cpreg(%d)", val);
3178 break;
3179 }
3180 }
3181 }
3182 }
3183
3184 /* If we are adding or or'ing something to rs1, then
3185 check to see whether the previous instruction was
3186 a sethi to the same register as in the sethi.
3187 If so, attempt to print the result of the add or
3188 or (in this context add and or do the same thing)
3189 and its symbolic value. */
3190 if (imm_ored_to_rs1 || imm_added_to_rs1)
3191 {
3192 unsigned long prev_insn;
3193 int errcode;
3194
46f42f29
BS		 3195 if (memaddr >= 4)
3196 errcode =
3197 (*info->read_memory_func)
f930d07e 3198 (memaddr - 4, buffer, sizeof (buffer), info);
46f42f29
BS		 3199 else
3200 errcode = 1;
3201
f930d07e
BS		 3202 prev_insn = getword (buffer);
3203
3204 if (errcode == 0)
3205 {
3206 /* If it is a delayed branch, we need to look at the
3207 instruction before the delayed branch. This handles
46f42f29 3208 sequences such as:
f930d07e
BS		 3209
3210 sethi %o1, %hi(_foo), %o1
3211 call _printf
46f42f29 3212 or %o1, %lo(_foo), %o1 */
f930d07e
BS		 3213
3214 if (is_delayed_branch (prev_insn))
3215 {
46f42f29
BS		 3216 if (memaddr >= 8)
3217 errcode = (*info->read_memory_func)
3218 (memaddr - 8, buffer, sizeof (buffer), info);
3219 else
3220 errcode = 1;
3221
f930d07e
BS		 3222 prev_insn = getword (buffer);
3223 }
3224 }
3225
3226 /* If there was a problem reading memory, then assume
3227 the previous instruction was not sethi. */
3228 if (errcode == 0)
3229 {
3230 /* Is it sethi to the same register? */
3231 if ((prev_insn & 0xc1c00000) == 0x01000000
3232 && X_RD (prev_insn) == X_RS1 (insn))
3233 {
3234 (*info->fprintf_func) (stream, "\t! ");
3235 info->target =
3236 ((unsigned) 0xFFFFFFFF
3237 & ((int) X_IMM22 (prev_insn) << 10));
3238 if (imm_added_to_rs1)
3239 info->target += X_SIMM (insn, 13);
3240 else
3241 info->target |= X_SIMM (insn, 13);
3242 (*info->print_address_func) (info->target, info);
3243 info->insn_type = dis_dref;
3244 info->data_size = 4; /* FIXME!!! */
3245 }
3246 }
3247 }
3248
3249 if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
3250 {
46f42f29 3251 /* FIXME -- check is_annulled flag. */
f930d07e
BS		 3252 if (opcode->flags & F_UNBR)
3253 info->insn_type = dis_branch;
3254 if (opcode->flags & F_CONDBR)
3255 info->insn_type = dis_condbranch;
3256 if (opcode->flags & F_JSR)
3257 info->insn_type = dis_jsr;
3258 if (opcode->flags & F_DELAYED)
3259 info->branch_delay_insns = 1;
3260 }
3261
3262 return sizeof (buffer);
3263 }
aa0aa4fa
FB		 3264 }
3265
46f42f29 3266 info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */
345ce423 3267 (*info->fprintf_func) (stream, ".long %#08lx", insn);
aa0aa4fa
FB		 3268 return sizeof (buffer);
3269}
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