[qemu.git] / hw / apb_pci.c

/*
 * QEMU Ultrasparc APB PCI host
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

/* XXX This file and most of its contents are somewhat misnamed.  The
   Ultrasparc PCI host is called the PCI Bus Module (PBM).  The APB is
   the secondary PCI bridge.  */

#include "sysbus.h"
#include "pci.h"
#include "pci_host.h"
#include "apb_pci.h"

/* debug APB */
//#define DEBUG_APB

#ifdef DEBUG_APB
#define APB_DPRINTF(fmt, ...) \
do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
#else
#define APB_DPRINTF(fmt, ...)
#endif

/*
 * Chipset docs:
 * PBM: "UltraSPARC IIi User's Manual",
 * http://www.sun.com/processors/manuals/805-0087.pdf
 *
 * APB: "Advanced PCI Bridge (APB) User's Manual",
 * http://www.sun.com/processors/manuals/805-1251.pdf
 */

#define PBM_PCI_IMR_MASK    0x7fffffff
#define PBM_PCI_IMR_ENABLED 0x80000000

#define POR          (1 << 31)
#define SOFT_POR     (1 << 30)
#define SOFT_XIR     (1 << 29)
#define BTN_POR      (1 << 28)
#define BTN_XIR      (1 << 27)
#define RESET_MASK   0xf8000000
#define RESET_WCMASK 0x98000000
#define RESET_WMASK  0x60000000

typedef struct APBState {
    SysBusDevice busdev;
    PCIHostState host_state;
    uint32_t iommu[4];
    uint32_t pci_control[16];
    uint32_t pci_irq_map[8];
    uint32_t obio_irq_map[32];
    qemu_irq pci_irqs[32];
    uint32_t reset_control;
} APBState;

static unsigned int nr_resets;

static void apb_config_writel (void *opaque, target_phys_addr_t addr,
                               uint32_t val)
{
    APBState *s = opaque;

    APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);

    switch (addr & 0xffff) {
    case 0x30 ... 0x4f: /* DMA error registers */
        /* XXX: not implemented yet */
        break;
    case 0x200 ... 0x20b: /* IOMMU */
        s->iommu[(addr & 0xf) >> 2] = val;
        break;
    case 0x20c ... 0x3ff: /* IOMMU flush */
        break;
    case 0xc00 ... 0xc3f: /* PCI interrupt control */
        if (addr & 4) {
            s->pci_irq_map[(addr & 0x3f) >> 3] &= PBM_PCI_IMR_MASK;
            s->pci_irq_map[(addr & 0x3f) >> 3] |= val & ~PBM_PCI_IMR_MASK;
        }
        break;
    case 0x2000 ... 0x202f: /* PCI control */
        s->pci_control[(addr & 0x3f) >> 2] = val;
        break;
    case 0xf020 ... 0xf027: /* Reset control */
        if (addr & 4) {
            val &= RESET_MASK;
            s->reset_control &= ~(val & RESET_WCMASK);
            s->reset_control |= val & RESET_WMASK;
            if (val & SOFT_POR) {
                nr_resets = 0;
                qemu_system_reset_request();
            } else if (val & SOFT_XIR) {
                qemu_system_reset_request();
            }
        }
        break;
    case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
    case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
    case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
    case 0xf000 ... 0xf01f: /* FFB config, memory control */
        /* we don't care */
    default:
        break;
    }
}

static uint32_t apb_config_readl (void *opaque,
                                  target_phys_addr_t addr)
{
    APBState *s = opaque;
    uint32_t val;

    switch (addr & 0xffff) {
    case 0x30 ... 0x4f: /* DMA error registers */
        val = 0;
        /* XXX: not implemented yet */
        break;
    case 0x200 ... 0x20b: /* IOMMU */
        val = s->iommu[(addr & 0xf) >> 2];
        break;
    case 0x20c ... 0x3ff: /* IOMMU flush */
        val = 0;
        break;
    case 0xc00 ... 0xc3f: /* PCI interrupt control */
        if (addr & 4) {
            val = s->pci_irq_map[(addr & 0x3f) >> 3];
        } else {
            val = 0;
        }
        break;
    case 0x2000 ... 0x202f: /* PCI control */
        val = s->pci_control[(addr & 0x3f) >> 2];
        break;
    case 0xf020 ... 0xf027: /* Reset control */
        if (addr & 4) {
            val = s->reset_control;
        } else {
            val = 0;
        }
        break;
    case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
    case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
    case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
    case 0xf000 ... 0xf01f: /* FFB config, memory control */
        /* we don't care */
    default:
        val = 0;
        break;
    }
    APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, val);

    return val;
}

static CPUWriteMemoryFunc * const apb_config_write[] = {
    &apb_config_writel,
    &apb_config_writel,
    &apb_config_writel,
};

static CPUReadMemoryFunc * const apb_config_read[] = {
    &apb_config_readl,
    &apb_config_readl,
    &apb_config_readl,
};

static void apb_pci_config_write(APBState *s, target_phys_addr_t addr,
                                 uint32_t val, int size)
{
    APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
    pci_data_write(s->host_state.bus, (addr & 0x00ffffff) | (1u << 31), val,
                   size);
}

static uint32_t apb_pci_config_read(APBState *s, target_phys_addr_t addr,
                                    int size)
{
    uint32_t ret;

    ret = pci_data_read(s->host_state.bus, (addr & 0x00ffffff) | (1u << 31),
                        size);
    APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, ret);
    return ret;
}

static void apb_pci_config_writel(void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    APBState *s = opaque;

    apb_pci_config_write(s, addr, bswap32(val), 4);
}

static void apb_pci_config_writew(void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    APBState *s = opaque;

    apb_pci_config_write(s, addr, bswap16(val), 2);
}

static void apb_pci_config_writeb(void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    APBState *s = opaque;

    apb_pci_config_write(s, addr, val, 1);
}

static uint32_t apb_pci_config_readl(void *opaque, target_phys_addr_t addr)
{
    APBState *s = opaque;

    return bswap32(apb_pci_config_read(s, addr, 4));
}

static uint32_t apb_pci_config_readw(void *opaque, target_phys_addr_t addr)
{
    APBState *s = opaque;

    return bswap16(apb_pci_config_read(s, addr, 2));
}

static uint32_t apb_pci_config_readb(void *opaque, target_phys_addr_t addr)
{
    APBState *s = opaque;

    return apb_pci_config_read(s, addr, 1);
}

static CPUWriteMemoryFunc * const apb_pci_config_writes[] = {
    &apb_pci_config_writeb,
    &apb_pci_config_writew,
    &apb_pci_config_writel,
};

static CPUReadMemoryFunc * const apb_pci_config_reads[] = {
    &apb_pci_config_readb,
    &apb_pci_config_readw,
    &apb_pci_config_readl,
};

static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    cpu_outb(addr & IOPORTS_MASK, val);
}

static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    cpu_outw(addr & IOPORTS_MASK, bswap16(val));
}

static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
                                uint32_t val)
{
    cpu_outl(addr & IOPORTS_MASK, bswap32(val));
}

static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
{
    uint32_t val;

    val = cpu_inb(addr & IOPORTS_MASK);
    return val;
}

static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
{
    uint32_t val;

    val = bswap16(cpu_inw(addr & IOPORTS_MASK));
    return val;
}

static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
{
    uint32_t val;

    val = bswap32(cpu_inl(addr & IOPORTS_MASK));
    return val;
}

static CPUWriteMemoryFunc * const pci_apb_iowrite[] = {
    &pci_apb_iowriteb,
    &pci_apb_iowritew,
    &pci_apb_iowritel,
};

static CPUReadMemoryFunc * const pci_apb_ioread[] = {
    &pci_apb_ioreadb,
    &pci_apb_ioreadw,
    &pci_apb_ioreadl,
};

/* The APB host has an IRQ line for each IRQ line of each slot.  */
static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
{
    return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
}

static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int bus_offset;
    if (pci_dev->devfn & 1)
        bus_offset = 16;
    else
        bus_offset = 0;
    return bus_offset + irq_num;
}

static void pci_apb_set_irq(void *opaque, int irq_num, int level)
{
    APBState *s = opaque;

    /* PCI IRQ map onto the first 32 INO.  */
    if (irq_num < 32) {
        if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
            APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
            qemu_set_irq(s->pci_irqs[irq_num], level);
        } else {
            APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);
            qemu_irq_lower(s->pci_irqs[irq_num]);
        }
    }
}

static void apb_pci_bridge_init(PCIBus *b)
{
    PCIDevice *dev = pci_bridge_get_device(b);

    /*
     * command register:
     * According to PCI bridge spec, after reset
     *   bus master bit is off
     *   memory space enable bit is off
     * According to manual (805-1251.pdf).
     *   the reset value should be zero unless the boot pin is tied high
     *   (which is true) and thus it should be PCI_COMMAND_MEMORY.
     */
    pci_set_word(dev->config + PCI_COMMAND,
                 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
    dev->config[PCI_LATENCY_TIMER] = 0x10;
    dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
}

PCIBus *pci_apb_init(target_phys_addr_t special_base,
                     target_phys_addr_t mem_base,
                     qemu_irq *pic, PCIBus **bus2, PCIBus **bus3)
{
    DeviceState *dev;
    SysBusDevice *s;
    APBState *d;
    unsigned int i;

    /* Ultrasparc PBM main bus */
    dev = qdev_create(NULL, "pbm");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    /* apb_config */
    sysbus_mmio_map(s, 0, special_base);
    /* pci_ioport */
    sysbus_mmio_map(s, 1, special_base + 0x2000000ULL);
    /* pci_config */
    sysbus_mmio_map(s, 2, special_base + 0x1000000ULL);
    /* mem_data */
    sysbus_mmio_map(s, 3, mem_base);
    d = FROM_SYSBUS(APBState, s);
    d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
                                         pci_apb_set_irq, pci_pbm_map_irq, d,
                                         0, 32);
    pci_bus_set_mem_base(d->host_state.bus, mem_base);

    for (i = 0; i < 32; i++) {
        sysbus_connect_irq(s, i, pic[i]);
    }

    pci_create_simple(d->host_state.bus, 0, "pbm");
    /* APB secondary busses */
    *bus2 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 0),
                            PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA,
                            pci_apb_map_irq,
                            "Advanced PCI Bus secondary bridge 1");
    apb_pci_bridge_init(*bus2);

    *bus3 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 1),
                            PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA,
                            pci_apb_map_irq,
                            "Advanced PCI Bus secondary bridge 2");
    apb_pci_bridge_init(*bus3);

    return d->host_state.bus;
}

static void pci_pbm_reset(DeviceState *d)
{
    unsigned int i;
    APBState *s = container_of(d, APBState, busdev.qdev);

    for (i = 0; i < 8; i++) {
        s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
    }

    if (nr_resets++ == 0) {
        /* Power on reset */
        s->reset_control = POR;
    }
}

static int pci_pbm_init_device(SysBusDevice *dev)
{
    APBState *s;
    int pci_mem_data, apb_config, pci_ioport, pci_config;
    unsigned int i;

    s = FROM_SYSBUS(APBState, dev);
    for (i = 0; i < 8; i++) {
        s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
    }
    for (i = 0; i < 32; i++) {
        sysbus_init_irq(dev, &s->pci_irqs[i]);
    }

    /* apb_config */
    apb_config = cpu_register_io_memory(apb_config_read,
                                        apb_config_write, s);
    sysbus_init_mmio(dev, 0x10000ULL, apb_config);
    /* pci_ioport */
    pci_ioport = cpu_register_io_memory(pci_apb_ioread,
                                          pci_apb_iowrite, s);
    sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);
    /* pci_config */
    pci_config = cpu_register_io_memory(apb_pci_config_reads,
                                        apb_pci_config_writes, s);
    sysbus_init_mmio(dev, 0x1000000ULL, pci_config);
    /* mem_data */
    pci_mem_data = pci_host_data_register_mmio(&s->host_state);
    sysbus_init_mmio(dev, 0x10000000ULL, pci_mem_data);
    return 0;
}

static int pbm_pci_host_init(PCIDevice *d)
{
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_SUN);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_SUN_SABRE);
    d->config[0x04] = 0x06; // command = bus master, pci mem
    d->config[0x05] = 0x00;
    d->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
    d->config[0x07] = 0x03; // status = medium devsel
    d->config[0x08] = 0x00; // revision
    d->config[0x09] = 0x00; // programming i/f
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
    d->config[0x0D] = 0x10; // latency_timer
    d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
    return 0;
}

static PCIDeviceInfo pbm_pci_host_info = {
    .qdev.name = "pbm",
    .qdev.size = sizeof(PCIDevice),
    .init      = pbm_pci_host_init,
    .header_type  = PCI_HEADER_TYPE_BRIDGE,
};

static SysBusDeviceInfo pbm_host_info = {
    .qdev.name = "pbm",
    .qdev.size = sizeof(APBState),
    .qdev.reset = pci_pbm_reset,
    .init = pci_pbm_init_device,
};
static void pbm_register_devices(void)
{
    sysbus_register_withprop(&pbm_host_info);
    pci_qdev_register(&pbm_pci_host_info);
}

device_init(pbm_register_devices)
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU Ultrasparc APB PCI host
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
80b3ada7	24
a94fd955	25	/* XXX This file and most of its contents are somewhat misnamed. The
80b3ada7 PB	26	Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is
	27	the secondary PCI bridge. */
	28
72f44c8c	29	#include "sysbus.h"
87ecb68b	30	#include "pci.h"
4f5e19e6	31	#include "pci_host.h"
18e08a55	32	#include "apb_pci.h"
a94fd955 BS	33
	34	/* debug APB */
	35	//#define DEBUG_APB
	36
	37	#ifdef DEBUG_APB
001faf32 BS	38	#define APB_DPRINTF(fmt, ...) \
001faf32 BS	39	do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
a94fd955	40	#else
001faf32	41	#define APB_DPRINTF(fmt, ...)
a94fd955 BS	42	#endif
a94fd955 BS	43
930f3fe1 BS	44	/*
	45	* Chipset docs:
	46	* PBM: "UltraSPARC IIi User's Manual",
	47	* http://www.sun.com/processors/manuals/805-0087.pdf
	48	*
	49	* APB: "Advanced PCI Bridge (APB) User's Manual",
	50	* http://www.sun.com/processors/manuals/805-1251.pdf
	51	*/
	52
95819af0 BS	53	#define PBM_PCI_IMR_MASK 0x7fffffff
	54	#define PBM_PCI_IMR_ENABLED 0x80000000
	55
	56	#define POR (1 << 31)
	57	#define SOFT_POR (1 << 30)
	58	#define SOFT_XIR (1 << 29)
	59	#define BTN_POR (1 << 28)
	60	#define BTN_XIR (1 << 27)
	61	#define RESET_MASK 0xf8000000
	62	#define RESET_WCMASK 0x98000000
	63	#define RESET_WMASK 0x60000000
	64
72f44c8c BS	65	typedef struct APBState {
	66	SysBusDevice busdev;
	67	PCIHostState host_state;
95819af0 BS	68	uint32_t iommu[4];
	69	uint32_t pci_control[16];
	70	uint32_t pci_irq_map[8];
	71	uint32_t obio_irq_map[32];
	72	qemu_irq pci_irqs[32];
	73	uint32_t reset_control;
72f44c8c	74	} APBState;
502a5395	75
95819af0 BS	76	static unsigned int nr_resets;
95819af0 BS	77
c227f099	78	static void apb_config_writel (void *opaque, target_phys_addr_t addr,
f930d07e	79	uint32_t val)
502a5395	80	{
95819af0 BS	81	APBState *s = opaque;
	82
	83	APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
	84
	85	switch (addr & 0xffff) {
	86	case 0x30 ... 0x4f: /* DMA error registers */
	87	/* XXX: not implemented yet */
	88	break;
	89	case 0x200 ... 0x20b: /* IOMMU */
	90	s->iommu[(addr & 0xf) >> 2] = val;
	91	break;
	92	case 0x20c ... 0x3ff: /* IOMMU flush */
	93	break;
	94	case 0xc00 ... 0xc3f: /* PCI interrupt control */
	95	if (addr & 4) {
	96	s->pci_irq_map[(addr & 0x3f) >> 3] &= PBM_PCI_IMR_MASK;
	97	s->pci_irq_map[(addr & 0x3f) >> 3] \|= val & ~PBM_PCI_IMR_MASK;
	98	}
	99	break;
	100	case 0x2000 ... 0x202f: /* PCI control */
	101	s->pci_control[(addr & 0x3f) >> 2] = val;
	102	break;
	103	case 0xf020 ... 0xf027: /* Reset control */
	104	if (addr & 4) {
	105	val &= RESET_MASK;
	106	s->reset_control &= ~(val & RESET_WCMASK);
	107	s->reset_control \|= val & RESET_WMASK;
	108	if (val & SOFT_POR) {
	109	nr_resets = 0;
	110	qemu_system_reset_request();
	111	} else if (val & SOFT_XIR) {
	112	qemu_system_reset_request();
	113	}
	114	}
	115	break;
	116	case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
	117	case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
	118	case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
	119	case 0xf000 ... 0xf01f: /* FFB config, memory control */
	120	/* we don't care */
502a5395	121	default:
f930d07e	122	break;
502a5395 PB	123	}
	124	}
	125
	126	static uint32_t apb_config_readl (void *opaque,
c227f099	127	target_phys_addr_t addr)
502a5395	128	{
95819af0	129	APBState *s = opaque;
502a5395 PB	130	uint32_t val;
502a5395 PB	131
95819af0 BS	132	switch (addr & 0xffff) {
	133	case 0x30 ... 0x4f: /* DMA error registers */
	134	val = 0;
	135	/* XXX: not implemented yet */
	136	break;
	137	case 0x200 ... 0x20b: /* IOMMU */
	138	val = s->iommu[(addr & 0xf) >> 2];
	139	break;
	140	case 0x20c ... 0x3ff: /* IOMMU flush */
	141	val = 0;
	142	break;
	143	case 0xc00 ... 0xc3f: /* PCI interrupt control */
	144	if (addr & 4) {
	145	val = s->pci_irq_map[(addr & 0x3f) >> 3];
	146	} else {
	147	val = 0;
	148	}
	149	break;
	150	case 0x2000 ... 0x202f: /* PCI control */
	151	val = s->pci_control[(addr & 0x3f) >> 2];
	152	break;
	153	case 0xf020 ... 0xf027: /* Reset control */
	154	if (addr & 4) {
	155	val = s->reset_control;
	156	} else {
	157	val = 0;
	158	}
	159	break;
	160	case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
	161	case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
	162	case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
	163	case 0xf000 ... 0xf01f: /* FFB config, memory control */
	164	/* we don't care */
502a5395	165	default:
f930d07e BS	166	val = 0;
f930d07e BS	167	break;
502a5395	168	}
95819af0 BS	169	APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, val);
95819af0 BS	170
502a5395 PB	171	return val;
	172	}
	173
d60efc6b	174	static CPUWriteMemoryFunc * const apb_config_write[] = {
502a5395 PB	175	&apb_config_writel,
	176	&apb_config_writel,
	177	&apb_config_writel,
	178	};
	179
d60efc6b	180	static CPUReadMemoryFunc * const apb_config_read[] = {
502a5395 PB	181	&apb_config_readl,
	182	&apb_config_readl,
	183	&apb_config_readl,
	184	};
	185
5a5d4a76 BS	186	static void apb_pci_config_write(APBState *s, target_phys_addr_t addr,
	187	uint32_t val, int size)
	188	{
	189	APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
	190	pci_data_write(s->host_state.bus, (addr & 0x00ffffff) \| (1u << 31), val,
	191	size);
	192	}
	193
	194	static uint32_t apb_pci_config_read(APBState *s, target_phys_addr_t addr,
	195	int size)
	196	{
	197	uint32_t ret;
	198
	199	ret = pci_data_read(s->host_state.bus, (addr & 0x00ffffff) \| (1u << 31),
	200	size);
	201	APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, ret);
	202	return ret;
	203	}
	204
	205	static void apb_pci_config_writel(void *opaque, target_phys_addr_t addr,
	206	uint32_t val)
	207	{
	208	APBState *s = opaque;
	209
204c7a39	210	apb_pci_config_write(s, addr, bswap32(val), 4);
5a5d4a76 BS	211	}
	212
	213	static void apb_pci_config_writew(void *opaque, target_phys_addr_t addr,
	214	uint32_t val)
	215	{
	216	APBState *s = opaque;
	217
204c7a39	218	apb_pci_config_write(s, addr, bswap16(val), 2);
5a5d4a76 BS	219	}
	220
	221	static void apb_pci_config_writeb(void *opaque, target_phys_addr_t addr,
	222	uint32_t val)
	223	{
	224	APBState *s = opaque;
	225
	226	apb_pci_config_write(s, addr, val, 1);
	227	}
	228
	229	static uint32_t apb_pci_config_readl(void *opaque, target_phys_addr_t addr)
	230	{
	231	APBState *s = opaque;
	232
204c7a39	233	return bswap32(apb_pci_config_read(s, addr, 4));
5a5d4a76 BS	234	}
	235
	236	static uint32_t apb_pci_config_readw(void *opaque, target_phys_addr_t addr)
	237	{
	238	APBState *s = opaque;
	239
204c7a39	240	return bswap16(apb_pci_config_read(s, addr, 2));
5a5d4a76 BS	241	}
	242
	243	static uint32_t apb_pci_config_readb(void *opaque, target_phys_addr_t addr)
	244	{
	245	APBState *s = opaque;
	246
	247	return apb_pci_config_read(s, addr, 1);
	248	}
	249
	250	static CPUWriteMemoryFunc * const apb_pci_config_writes[] = {
5a5d4a76	251	&apb_pci_config_writeb,
3eb26cc2 BS	252	&apb_pci_config_writew,
3eb26cc2 BS	253	&apb_pci_config_writel,
5a5d4a76 BS	254	};
	255
	256	static CPUReadMemoryFunc * const apb_pci_config_reads[] = {
5a5d4a76	257	&apb_pci_config_readb,
3eb26cc2 BS	258	&apb_pci_config_readw,
3eb26cc2 BS	259	&apb_pci_config_readl,
5a5d4a76 BS	260	};
5a5d4a76 BS	261
c227f099	262	static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
502a5395 PB	263	uint32_t val)
502a5395 PB	264	{
afcea8cb	265	cpu_outb(addr & IOPORTS_MASK, val);
502a5395 PB	266	}
502a5395 PB	267
c227f099	268	static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
502a5395 PB	269	uint32_t val)
502a5395 PB	270	{
a4d5f62c	271	cpu_outw(addr & IOPORTS_MASK, bswap16(val));
502a5395 PB	272	}
502a5395 PB	273
c227f099	274	static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
502a5395 PB	275	uint32_t val)
502a5395 PB	276	{
a4d5f62c	277	cpu_outl(addr & IOPORTS_MASK, bswap32(val));
502a5395 PB	278	}
502a5395 PB	279
c227f099	280	static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
502a5395 PB	281	{
	282	uint32_t val;
	283
afcea8cb	284	val = cpu_inb(addr & IOPORTS_MASK);
502a5395 PB	285	return val;
	286	}
	287
c227f099	288	static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
502a5395 PB	289	{
	290	uint32_t val;
	291
a4d5f62c	292	val = bswap16(cpu_inw(addr & IOPORTS_MASK));
502a5395 PB	293	return val;
	294	}
	295
c227f099	296	static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
502a5395 PB	297	{
	298	uint32_t val;
	299
a4d5f62c	300	val = bswap32(cpu_inl(addr & IOPORTS_MASK));
502a5395 PB	301	return val;
	302	}
	303
d60efc6b	304	static CPUWriteMemoryFunc * const pci_apb_iowrite[] = {
502a5395 PB	305	&pci_apb_iowriteb,
	306	&pci_apb_iowritew,
	307	&pci_apb_iowritel,
	308	};
	309
d60efc6b	310	static CPUReadMemoryFunc * const pci_apb_ioread[] = {
502a5395 PB	311	&pci_apb_ioreadb,
	312	&pci_apb_ioreadw,
	313	&pci_apb_ioreadl,
	314	};
	315
80b3ada7	316	/* The APB host has an IRQ line for each IRQ line of each slot. */
d2b59317	317	static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
502a5395	318	{
80b3ada7 PB	319	return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
	320	}
	321
	322	static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
	323	{
	324	int bus_offset;
	325	if (pci_dev->devfn & 1)
	326	bus_offset = 16;
	327	else
	328	bus_offset = 0;
	329	return bus_offset + irq_num;
d2b59317 PB	330	}
d2b59317 PB	331
5d4e84c8	332	static void pci_apb_set_irq(void *opaque, int irq_num, int level)
d2b59317	333	{
95819af0	334	APBState *s = opaque;
5d4e84c8	335
80b3ada7	336	/* PCI IRQ map onto the first 32 INO. */
95819af0 BS	337	if (irq_num < 32) {
	338	if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
	339	APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
	340	qemu_set_irq(s->pci_irqs[irq_num], level);
	341	} else {
	342	APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);
	343	qemu_irq_lower(s->pci_irqs[irq_num]);
	344	}
	345	}
502a5395 PB	346	}
502a5395 PB	347
d6318738 MT	348	static void apb_pci_bridge_init(PCIBus *b)
	349	{
	350	PCIDevice *dev = pci_bridge_get_device(b);
	351
	352	/*
	353	* command register:
	354	* According to PCI bridge spec, after reset
	355	* bus master bit is off
	356	* memory space enable bit is off
	357	* According to manual (805-1251.pdf).
	358	* the reset value should be zero unless the boot pin is tied high
	359	* (which is true) and thus it should be PCI_COMMAND_MEMORY.
	360	*/
	361	pci_set_word(dev->config + PCI_COMMAND,
	362	PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
	363	dev->config[PCI_LATENCY_TIMER] = 0x10;
	364	dev->config[PCI_HEADER_TYPE] \|= PCI_HEADER_TYPE_MULTI_FUNCTION;
	365	}
	366
c227f099 AL	367	PCIBus *pci_apb_init(target_phys_addr_t special_base,
c227f099 AL	368	target_phys_addr_t mem_base,
c190ea07	369	qemu_irq pic, PCIBus bus2, PCIBus *bus3)
502a5395	370	{
72f44c8c BS	371	DeviceState *dev;
	372	SysBusDevice *s;
	373	APBState *d;
95819af0	374	unsigned int i;
502a5395	375
80b3ada7	376	/* Ultrasparc PBM main bus */
72f44c8c	377	dev = qdev_create(NULL, "pbm");
e23a1b33	378	qdev_init_nofail(dev);
72f44c8c BS	379	s = sysbus_from_qdev(dev);
72f44c8c BS	380	/* apb_config */
bae7b517	381	sysbus_mmio_map(s, 0, special_base);
72f44c8c BS	382	/* pci_ioport */
72f44c8c BS	383	sysbus_mmio_map(s, 1, special_base + 0x2000000ULL);
204c7a39	384	/* pci_config */
72f44c8c BS	385	sysbus_mmio_map(s, 2, special_base + 0x1000000ULL);
72f44c8c BS	386	/* mem_data */
204c7a39	387	sysbus_mmio_map(s, 3, mem_base);
72f44c8c	388	d = FROM_SYSBUS(APBState, s);
c5ff6d54	389	d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
95819af0	390	pci_apb_set_irq, pci_pbm_map_irq, d,
72f44c8c	391	0, 32);
f6b6f1bc BS	392	pci_bus_set_mem_base(d->host_state.bus, mem_base);
f6b6f1bc BS	393
95819af0 BS	394	for (i = 0; i < 32; i++) {
	395	sysbus_connect_irq(s, i, pic[i]);
	396	}
	397
72f44c8c BS	398	pci_create_simple(d->host_state.bus, 0, "pbm");
72f44c8c BS	399	/* APB secondary busses */
2217dcff IY	400	*bus2 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 0),
	401	PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA,
	402	pci_apb_map_irq,
72f44c8c	403	"Advanced PCI Bus secondary bridge 1");
d6318738 MT	404	apb_pci_bridge_init(*bus2);
d6318738 MT	405
2217dcff IY	406	*bus3 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 1),
	407	PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA,
	408	pci_apb_map_irq,
72f44c8c	409	"Advanced PCI Bus secondary bridge 2");
d6318738	410	apb_pci_bridge_init(*bus3);
502a5395	411
72f44c8c BS	412	return d->host_state.bus;
	413	}
	414
95819af0	415	static void pci_pbm_reset(DeviceState *d)
72f44c8c	416	{
95819af0 BS	417	unsigned int i;
95819af0 BS	418	APBState *s = container_of(d, APBState, busdev.qdev);
72f44c8c	419
95819af0 BS	420	for (i = 0; i < 8; i++) {
	421	s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
	422	}
	423
	424	if (nr_resets++ == 0) {
	425	/* Power on reset */
	426	s->reset_control = POR;
	427	}
	428	}
	429
	430	static int pci_pbm_init_device(SysBusDevice *dev)
	431	{
72f44c8c	432	APBState *s;
204c7a39	433	int pci_mem_data, apb_config, pci_ioport, pci_config;
95819af0	434	unsigned int i;
72f44c8c BS	435
72f44c8c BS	436	s = FROM_SYSBUS(APBState, dev);
95819af0 BS	437	for (i = 0; i < 8; i++) {
	438	s->pci_irq_map[i] = (0x1f << 6) \| (i << 2);
	439	}
	440	for (i = 0; i < 32; i++) {
	441	sysbus_init_irq(dev, &s->pci_irqs[i]);
	442	}
	443
72f44c8c	444	/* apb_config */
1eed09cb	445	apb_config = cpu_register_io_memory(apb_config_read,
f930d07e	446	apb_config_write, s);
bae7b517	447	sysbus_init_mmio(dev, 0x10000ULL, apb_config);
72f44c8c	448	/* pci_ioport */
1eed09cb	449	pci_ioport = cpu_register_io_memory(pci_apb_ioread,
502a5395	450	pci_apb_iowrite, s);
72f44c8c	451	sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);
5a5d4a76 BS	452	/* pci_config */
	453	pci_config = cpu_register_io_memory(apb_pci_config_reads,
	454	apb_pci_config_writes, s);
	455	sysbus_init_mmio(dev, 0x1000000ULL, pci_config);
72f44c8c	456	/* mem_data */
f08b32fe	457	pci_mem_data = pci_host_data_register_mmio(&s->host_state);
72f44c8c	458	sysbus_init_mmio(dev, 0x10000000ULL, pci_mem_data);
81a322d4	459	return 0;
72f44c8c	460	}
502a5395	461
81a322d4	462	static int pbm_pci_host_init(PCIDevice *d)
72f44c8c	463	{
deb54399 AL	464	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_SUN);
deb54399 AL	465	pci_config_set_device_id(d->config, PCI_DEVICE_ID_SUN_SABRE);
502a5395 PB	466	d->config[0x04] = 0x06; // command = bus master, pci mem
	467	d->config[0x05] = 0x00;
	468	d->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
	469	d->config[0x07] = 0x03; // status = medium devsel
	470	d->config[0x08] = 0x00; // revision
	471	d->config[0x09] = 0x00; // programming i/f
173a543b	472	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
502a5395	473	d->config[0x0D] = 0x10; // latency_timer
110c50fd	474	d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
81a322d4	475	return 0;
72f44c8c	476	}
80b3ada7	477
72f44c8c BS	478	static PCIDeviceInfo pbm_pci_host_info = {
	479	.qdev.name = "pbm",
	480	.qdev.size = sizeof(PCIDevice),
	481	.init = pbm_pci_host_init,
776e1bbb	482	.header_type = PCI_HEADER_TYPE_BRIDGE,
72f44c8c BS	483	};
72f44c8c BS	484
95819af0 BS	485	static SysBusDeviceInfo pbm_host_info = {
	486	.qdev.name = "pbm",
	487	.qdev.size = sizeof(APBState),
	488	.qdev.reset = pci_pbm_reset,
	489	.init = pci_pbm_init_device,
	490	};
72f44c8c BS	491	static void pbm_register_devices(void)
72f44c8c BS	492	{
95819af0	493	sysbus_register_withprop(&pbm_host_info);
72f44c8c	494	pci_qdev_register(&pbm_pci_host_info);
502a5395	495	}
72f44c8c BS	496
72f44c8c BS	497	device_init(pbm_register_devices)