[qemu.git] / target-mips / machine.c

#include "hw/hw.h"
#include "hw/boards.h"

#include "cpu.h"

static void save_tc(QEMUFile *f, TCState *tc)
{
    int i;

    /* Save active TC */
    for(i = 0; i < 32; i++)
        qemu_put_betls(f, &tc->gpr[i]);
    qemu_put_betls(f, &tc->PC);
    for(i = 0; i < MIPS_DSP_ACC; i++)
        qemu_put_betls(f, &tc->HI[i]);
    for(i = 0; i < MIPS_DSP_ACC; i++)
        qemu_put_betls(f, &tc->LO[i]);
    for(i = 0; i < MIPS_DSP_ACC; i++)
        qemu_put_betls(f, &tc->ACX[i]);
    qemu_put_betls(f, &tc->DSPControl);
    qemu_put_sbe32s(f, &tc->CP0_TCStatus);
    qemu_put_sbe32s(f, &tc->CP0_TCBind);
    qemu_put_betls(f, &tc->CP0_TCHalt);
    qemu_put_betls(f, &tc->CP0_TCContext);
    qemu_put_betls(f, &tc->CP0_TCSchedule);
    qemu_put_betls(f, &tc->CP0_TCScheFBack);
    qemu_put_sbe32s(f, &tc->CP0_Debug_tcstatus);
    qemu_put_betls(f, &tc->CP0_UserLocal);
}

static void save_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)
{
    int i;

    for(i = 0; i < 32; i++)
        qemu_put_be64s(f, &fpu->fpr[i].d);
    qemu_put_s8s(f, &fpu->fp_status.float_detect_tininess);
    qemu_put_s8s(f, &fpu->fp_status.float_rounding_mode);
    qemu_put_s8s(f, &fpu->fp_status.float_exception_flags);
    qemu_put_be32s(f, &fpu->fcr0);
    qemu_put_be32s(f, &fpu->fcr31);
}

void cpu_save(QEMUFile *f, void *opaque)
{
    CPUMIPSState *env = opaque;
    int i;

    /* Save active TC */
    save_tc(f, &env->active_tc);

    /* Save active FPU */
    save_fpu(f, &env->active_fpu);

    /* Save MVP */
    qemu_put_sbe32s(f, &env->mvp->CP0_MVPControl);
    qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf0);
    qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf1);

    /* Save TLB */
    qemu_put_be32s(f, &env->tlb->nb_tlb);
    qemu_put_be32s(f, &env->tlb->tlb_in_use);
    for(i = 0; i < MIPS_TLB_MAX; i++) {
        uint16_t flags = ((env->tlb->mmu.r4k.tlb[i].EHINV << 15) |
                          (env->tlb->mmu.r4k.tlb[i].RI1 << 14) |
                          (env->tlb->mmu.r4k.tlb[i].RI0 << 13) |
                          (env->tlb->mmu.r4k.tlb[i].XI1 << 12) |
                          (env->tlb->mmu.r4k.tlb[i].XI0 << 11) |
                          (env->tlb->mmu.r4k.tlb[i].G << 10) |
                          (env->tlb->mmu.r4k.tlb[i].C0 << 7) |
                          (env->tlb->mmu.r4k.tlb[i].C1 << 4) |
                          (env->tlb->mmu.r4k.tlb[i].V0 << 3) |
                          (env->tlb->mmu.r4k.tlb[i].V1 << 2) |
                          (env->tlb->mmu.r4k.tlb[i].D0 << 1) |
                          (env->tlb->mmu.r4k.tlb[i].D1 << 0));
        uint8_t asid;

        qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN);
        qemu_put_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask);
        asid = env->tlb->mmu.r4k.tlb[i].ASID;
        qemu_put_8s(f, &asid);
        qemu_put_be16s(f, &flags);
        qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]);
        qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]);
    }

    /* Save CPU metastate */
    qemu_put_be32s(f, &env->current_tc);
    qemu_put_be32s(f, &env->current_fpu);
    qemu_put_sbe32s(f, &env->error_code);
    qemu_put_be32s(f, &env->hflags);
    qemu_put_betls(f, &env->btarget);
    i = env->bcond;
    qemu_put_sbe32s(f, &i);

    /* Save remaining CP1 registers */
    qemu_put_sbe32s(f, &env->CP0_Index);
    qemu_put_sbe32s(f, &env->CP0_Random);
    qemu_put_sbe32s(f, &env->CP0_VPEControl);
    qemu_put_sbe32s(f, &env->CP0_VPEConf0);
    qemu_put_sbe32s(f, &env->CP0_VPEConf1);
    qemu_put_betls(f, &env->CP0_YQMask);
    qemu_put_betls(f, &env->CP0_VPESchedule);
    qemu_put_betls(f, &env->CP0_VPEScheFBack);
    qemu_put_sbe32s(f, &env->CP0_VPEOpt);
    qemu_put_betls(f, &env->CP0_EntryLo0);
    qemu_put_betls(f, &env->CP0_EntryLo1);
    qemu_put_betls(f, &env->CP0_Context);
    qemu_put_sbe32s(f, &env->CP0_PageMask);
    qemu_put_sbe32s(f, &env->CP0_PageGrain);
    qemu_put_sbe32s(f, &env->CP0_Wired);
    qemu_put_sbe32s(f, &env->CP0_SRSConf0);
    qemu_put_sbe32s(f, &env->CP0_SRSConf1);
    qemu_put_sbe32s(f, &env->CP0_SRSConf2);
    qemu_put_sbe32s(f, &env->CP0_SRSConf3);
    qemu_put_sbe32s(f, &env->CP0_SRSConf4);
    qemu_put_sbe32s(f, &env->CP0_HWREna);
    qemu_put_betls(f, &env->CP0_BadVAddr);
    qemu_put_be32s(f, &env->CP0_BadInstr);
    qemu_put_be32s(f, &env->CP0_BadInstrP);
    qemu_put_sbe32s(f, &env->CP0_Count);
    qemu_put_betls(f, &env->CP0_EntryHi);
    qemu_put_sbe32s(f, &env->CP0_Compare);
    qemu_put_sbe32s(f, &env->CP0_Status);
    qemu_put_sbe32s(f, &env->CP0_IntCtl);
    qemu_put_sbe32s(f, &env->CP0_SRSCtl);
    qemu_put_sbe32s(f, &env->CP0_SRSMap);
    qemu_put_sbe32s(f, &env->CP0_Cause);
    qemu_put_betls(f, &env->CP0_EPC);
    qemu_put_sbe32s(f, &env->CP0_PRid);
    qemu_put_sbe32s(f, &env->CP0_EBase);
    qemu_put_sbe32s(f, &env->CP0_Config0);
    qemu_put_sbe32s(f, &env->CP0_Config1);
    qemu_put_sbe32s(f, &env->CP0_Config2);
    qemu_put_sbe32s(f, &env->CP0_Config3);
    qemu_put_sbe32s(f, &env->CP0_Config6);
    qemu_put_sbe32s(f, &env->CP0_Config7);
    qemu_put_betls(f, &env->lladdr);
    for(i = 0; i < 8; i++)
        qemu_put_betls(f, &env->CP0_WatchLo[i]);
    for(i = 0; i < 8; i++)
        qemu_put_sbe32s(f, &env->CP0_WatchHi[i]);
    qemu_put_betls(f, &env->CP0_XContext);
    qemu_put_sbe32s(f, &env->CP0_Framemask);
    qemu_put_sbe32s(f, &env->CP0_Debug);
    qemu_put_betls(f, &env->CP0_DEPC);
    qemu_put_sbe32s(f, &env->CP0_Performance0);
    qemu_put_sbe32s(f, &env->CP0_TagLo);
    qemu_put_sbe32s(f, &env->CP0_DataLo);
    qemu_put_sbe32s(f, &env->CP0_TagHi);
    qemu_put_sbe32s(f, &env->CP0_DataHi);
    qemu_put_betls(f, &env->CP0_ErrorEPC);
    qemu_put_sbe32s(f, &env->CP0_DESAVE);
    for (i = 0; i < MIPS_KSCRATCH_NUM; i++) {
        qemu_put_betls(f, &env->CP0_KScratch[i]);
    }

    /* Save inactive TC state */
    for (i = 0; i < MIPS_SHADOW_SET_MAX; i++)
        save_tc(f, &env->tcs[i]);
    for (i = 0; i < MIPS_FPU_MAX; i++)
        save_fpu(f, &env->fpus[i]);
}

static void load_tc(QEMUFile *f, TCState *tc, int version_id)
{
    int i;

    /* Save active TC */
    for(i = 0; i < 32; i++)
        qemu_get_betls(f, &tc->gpr[i]);
    qemu_get_betls(f, &tc->PC);
    for(i = 0; i < MIPS_DSP_ACC; i++)
        qemu_get_betls(f, &tc->HI[i]);
    for(i = 0; i < MIPS_DSP_ACC; i++)
        qemu_get_betls(f, &tc->LO[i]);
    for(i = 0; i < MIPS_DSP_ACC; i++)
        qemu_get_betls(f, &tc->ACX[i]);
    qemu_get_betls(f, &tc->DSPControl);
    qemu_get_sbe32s(f, &tc->CP0_TCStatus);
    qemu_get_sbe32s(f, &tc->CP0_TCBind);
    qemu_get_betls(f, &tc->CP0_TCHalt);
    qemu_get_betls(f, &tc->CP0_TCContext);
    qemu_get_betls(f, &tc->CP0_TCSchedule);
    qemu_get_betls(f, &tc->CP0_TCScheFBack);
    qemu_get_sbe32s(f, &tc->CP0_Debug_tcstatus);
    if (version_id >= 4) {
        qemu_get_betls(f, &tc->CP0_UserLocal);
    }
}

static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)
{
    int i;

    for(i = 0; i < 32; i++)
        qemu_get_be64s(f, &fpu->fpr[i].d);
    qemu_get_s8s(f, &fpu->fp_status.float_detect_tininess);
    qemu_get_s8s(f, &fpu->fp_status.float_rounding_mode);
    qemu_get_s8s(f, &fpu->fp_status.float_exception_flags);
    qemu_get_be32s(f, &fpu->fcr0);
    qemu_get_be32s(f, &fpu->fcr31);
}

int cpu_load(QEMUFile *f, void *opaque, int version_id)
{
    CPUMIPSState *env = opaque;
    MIPSCPU *cpu = mips_env_get_cpu(env);
    int i;

    if (version_id < 3) {
        return -EINVAL;
    }

    /* Load active TC */
    load_tc(f, &env->active_tc, version_id);

    /* Load active FPU */
    load_fpu(f, &env->active_fpu);

    /* Load MVP */
    qemu_get_sbe32s(f, &env->mvp->CP0_MVPControl);
    qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf0);
    qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf1);

    /* Load TLB */
    qemu_get_be32s(f, &env->tlb->nb_tlb);
    qemu_get_be32s(f, &env->tlb->tlb_in_use);
    for(i = 0; i < MIPS_TLB_MAX; i++) {
        uint16_t flags;
        uint8_t asid;

        qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN);
        qemu_get_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask);
        qemu_get_8s(f, &asid);
        env->tlb->mmu.r4k.tlb[i].ASID = asid;
        qemu_get_be16s(f, &flags);
        env->tlb->mmu.r4k.tlb[i].G = (flags >> 10) & 1;
        env->tlb->mmu.r4k.tlb[i].C0 = (flags >> 7) & 3;
        env->tlb->mmu.r4k.tlb[i].C1 = (flags >> 4) & 3;
        env->tlb->mmu.r4k.tlb[i].V0 = (flags >> 3) & 1;
        env->tlb->mmu.r4k.tlb[i].V1 = (flags >> 2) & 1;
        env->tlb->mmu.r4k.tlb[i].D0 = (flags >> 1) & 1;
        env->tlb->mmu.r4k.tlb[i].D1 = (flags >> 0) & 1;
        if (version_id >= 5) {
            env->tlb->mmu.r4k.tlb[i].EHINV = (flags >> 15) & 1;
            env->tlb->mmu.r4k.tlb[i].RI1 = (flags >> 14) & 1;
            env->tlb->mmu.r4k.tlb[i].RI0 = (flags >> 13) & 1;
            env->tlb->mmu.r4k.tlb[i].XI1 = (flags >> 12) & 1;
            env->tlb->mmu.r4k.tlb[i].XI0 = (flags >> 11) & 1;
        }
        qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]);
        qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]);
    }

    /* Load CPU metastate */
    qemu_get_be32s(f, &env->current_tc);
    qemu_get_be32s(f, &env->current_fpu);
    qemu_get_sbe32s(f, &env->error_code);
    qemu_get_be32s(f, &env->hflags);
    qemu_get_betls(f, &env->btarget);
    qemu_get_sbe32s(f, &i);
    env->bcond = i;

    /* Load remaining CP1 registers */
    qemu_get_sbe32s(f, &env->CP0_Index);
    qemu_get_sbe32s(f, &env->CP0_Random);
    qemu_get_sbe32s(f, &env->CP0_VPEControl);
    qemu_get_sbe32s(f, &env->CP0_VPEConf0);
    qemu_get_sbe32s(f, &env->CP0_VPEConf1);
    qemu_get_betls(f, &env->CP0_YQMask);
    qemu_get_betls(f, &env->CP0_VPESchedule);
    qemu_get_betls(f, &env->CP0_VPEScheFBack);
    qemu_get_sbe32s(f, &env->CP0_VPEOpt);
    qemu_get_betls(f, &env->CP0_EntryLo0);
    qemu_get_betls(f, &env->CP0_EntryLo1);
    qemu_get_betls(f, &env->CP0_Context);
    qemu_get_sbe32s(f, &env->CP0_PageMask);
    qemu_get_sbe32s(f, &env->CP0_PageGrain);
    qemu_get_sbe32s(f, &env->CP0_Wired);
    qemu_get_sbe32s(f, &env->CP0_SRSConf0);
    qemu_get_sbe32s(f, &env->CP0_SRSConf1);
    qemu_get_sbe32s(f, &env->CP0_SRSConf2);
    qemu_get_sbe32s(f, &env->CP0_SRSConf3);
    qemu_get_sbe32s(f, &env->CP0_SRSConf4);
    qemu_get_sbe32s(f, &env->CP0_HWREna);
    qemu_get_betls(f, &env->CP0_BadVAddr);
    qemu_get_sbe32s(f, &env->CP0_Count);
    qemu_get_betls(f, &env->CP0_EntryHi);
    qemu_get_sbe32s(f, &env->CP0_Compare);
    qemu_get_sbe32s(f, &env->CP0_Status);
    qemu_get_sbe32s(f, &env->CP0_IntCtl);
    qemu_get_sbe32s(f, &env->CP0_SRSCtl);
    qemu_get_sbe32s(f, &env->CP0_SRSMap);
    qemu_get_sbe32s(f, &env->CP0_Cause);
    qemu_get_betls(f, &env->CP0_EPC);
    qemu_get_sbe32s(f, &env->CP0_PRid);
    qemu_get_sbe32s(f, &env->CP0_EBase);
    qemu_get_sbe32s(f, &env->CP0_Config0);
    qemu_get_sbe32s(f, &env->CP0_Config1);
    qemu_get_sbe32s(f, &env->CP0_Config2);
    qemu_get_sbe32s(f, &env->CP0_Config3);
    qemu_get_sbe32s(f, &env->CP0_Config6);
    qemu_get_sbe32s(f, &env->CP0_Config7);
    qemu_get_betls(f, &env->lladdr);
    for(i = 0; i < 8; i++)
        qemu_get_betls(f, &env->CP0_WatchLo[i]);
    for(i = 0; i < 8; i++)
        qemu_get_sbe32s(f, &env->CP0_WatchHi[i]);
    qemu_get_betls(f, &env->CP0_XContext);
    qemu_get_sbe32s(f, &env->CP0_Framemask);
    qemu_get_sbe32s(f, &env->CP0_Debug);
    qemu_get_betls(f, &env->CP0_DEPC);
    qemu_get_sbe32s(f, &env->CP0_Performance0);
    qemu_get_sbe32s(f, &env->CP0_TagLo);
    qemu_get_sbe32s(f, &env->CP0_DataLo);
    qemu_get_sbe32s(f, &env->CP0_TagHi);
    qemu_get_sbe32s(f, &env->CP0_DataHi);
    qemu_get_betls(f, &env->CP0_ErrorEPC);
    qemu_get_sbe32s(f, &env->CP0_DESAVE);
    if (version_id >= 5) {
        qemu_get_be32s(f, &env->CP0_BadInstr);
        qemu_get_be32s(f, &env->CP0_BadInstrP);
        for (i = 0; i < MIPS_KSCRATCH_NUM; i++) {
            qemu_get_betls(f, &env->CP0_KScratch[i]);
        }
    }

    /* Load inactive TC state */
    for (i = 0; i < MIPS_SHADOW_SET_MAX; i++) {
        load_tc(f, &env->tcs[i], version_id);
    }
    for (i = 0; i < MIPS_FPU_MAX; i++)
        load_fpu(f, &env->fpus[i]);

    /* XXX: ensure compatibility for halted bit ? */
    tlb_flush(CPU(cpu), 1);
    return 0;
}
Commit	Line	Data
8dd3dca3 AJ	1	#include "hw/hw.h"
	2	#include "hw/boards.h"
	3
2b41f10e	4	#include "cpu.h"
33a84765	5
33a84765 TS	6	static void save_tc(QEMUFile f, TCState tc)
	7	{
	8	int i;
	9
	10	/* Save active TC */
	11	for(i = 0; i < 32; i++)
	12	qemu_put_betls(f, &tc->gpr[i]);
	13	qemu_put_betls(f, &tc->PC);
	14	for(i = 0; i < MIPS_DSP_ACC; i++)
	15	qemu_put_betls(f, &tc->HI[i]);
	16	for(i = 0; i < MIPS_DSP_ACC; i++)
	17	qemu_put_betls(f, &tc->LO[i]);
	18	for(i = 0; i < MIPS_DSP_ACC; i++)
	19	qemu_put_betls(f, &tc->ACX[i]);
	20	qemu_put_betls(f, &tc->DSPControl);
	21	qemu_put_sbe32s(f, &tc->CP0_TCStatus);
	22	qemu_put_sbe32s(f, &tc->CP0_TCBind);
	23	qemu_put_betls(f, &tc->CP0_TCHalt);
	24	qemu_put_betls(f, &tc->CP0_TCContext);
	25	qemu_put_betls(f, &tc->CP0_TCSchedule);
	26	qemu_put_betls(f, &tc->CP0_TCScheFBack);
	27	qemu_put_sbe32s(f, &tc->CP0_Debug_tcstatus);
d279279e	28	qemu_put_betls(f, &tc->CP0_UserLocal);
33a84765 TS	29	}
	30
	31	static void save_fpu(QEMUFile f, CPUMIPSFPUContext fpu)
	32	{
	33	int i;
	34
	35	for(i = 0; i < 32; i++)
	36	qemu_put_be64s(f, &fpu->fpr[i].d);
	37	qemu_put_s8s(f, &fpu->fp_status.float_detect_tininess);
	38	qemu_put_s8s(f, &fpu->fp_status.float_rounding_mode);
	39	qemu_put_s8s(f, &fpu->fp_status.float_exception_flags);
	40	qemu_put_be32s(f, &fpu->fcr0);
	41	qemu_put_be32s(f, &fpu->fcr31);
	42	}
	43
8dd3dca3 AJ	44	void cpu_save(QEMUFile f, void opaque)
8dd3dca3 AJ	45	{
7db13fae	46	CPUMIPSState *env = opaque;
33a84765 TS	47	int i;
	48
	49	/* Save active TC */
	50	save_tc(f, &env->active_tc);
	51
	52	/* Save active FPU */
	53	save_fpu(f, &env->active_fpu);
	54
	55	/* Save MVP */
	56	qemu_put_sbe32s(f, &env->mvp->CP0_MVPControl);
	57	qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf0);
	58	qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf1);
	59
	60	/* Save TLB */
	61	qemu_put_be32s(f, &env->tlb->nb_tlb);
	62	qemu_put_be32s(f, &env->tlb->tlb_in_use);
	63	for(i = 0; i < MIPS_TLB_MAX; i++) {
460c81f1 LA	64	uint16_t flags = ((env->tlb->mmu.r4k.tlb[i].EHINV << 15) \|
	65	(env->tlb->mmu.r4k.tlb[i].RI1 << 14) \|
	66	(env->tlb->mmu.r4k.tlb[i].RI0 << 13) \|
	67	(env->tlb->mmu.r4k.tlb[i].XI1 << 12) \|
	68	(env->tlb->mmu.r4k.tlb[i].XI0 << 11) \|
	69	(env->tlb->mmu.r4k.tlb[i].G << 10) \|
33a84765 TS	70	(env->tlb->mmu.r4k.tlb[i].C0 << 7) \|
	71	(env->tlb->mmu.r4k.tlb[i].C1 << 4) \|
	72	(env->tlb->mmu.r4k.tlb[i].V0 << 3) \|
	73	(env->tlb->mmu.r4k.tlb[i].V1 << 2) \|
	74	(env->tlb->mmu.r4k.tlb[i].D0 << 1) \|
	75	(env->tlb->mmu.r4k.tlb[i].D1 << 0));
95bed643	76	uint8_t asid;
33a84765 TS	77
	78	qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN);
	79	qemu_put_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask);
95bed643 BS	80	asid = env->tlb->mmu.r4k.tlb[i].ASID;
95bed643 BS	81	qemu_put_8s(f, &asid);
33a84765 TS	82	qemu_put_be16s(f, &flags);
	83	qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]);
	84	qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]);
	85	}
	86
	87	/* Save CPU metastate */
	88	qemu_put_be32s(f, &env->current_tc);
	89	qemu_put_be32s(f, &env->current_fpu);
	90	qemu_put_sbe32s(f, &env->error_code);
	91	qemu_put_be32s(f, &env->hflags);
	92	qemu_put_betls(f, &env->btarget);
1ba74fb8 AJ	93	i = env->bcond;
1ba74fb8 AJ	94	qemu_put_sbe32s(f, &i);
33a84765 TS	95
	96	/* Save remaining CP1 registers */
	97	qemu_put_sbe32s(f, &env->CP0_Index);
	98	qemu_put_sbe32s(f, &env->CP0_Random);
	99	qemu_put_sbe32s(f, &env->CP0_VPEControl);
	100	qemu_put_sbe32s(f, &env->CP0_VPEConf0);
	101	qemu_put_sbe32s(f, &env->CP0_VPEConf1);
	102	qemu_put_betls(f, &env->CP0_YQMask);
	103	qemu_put_betls(f, &env->CP0_VPESchedule);
	104	qemu_put_betls(f, &env->CP0_VPEScheFBack);
	105	qemu_put_sbe32s(f, &env->CP0_VPEOpt);
	106	qemu_put_betls(f, &env->CP0_EntryLo0);
	107	qemu_put_betls(f, &env->CP0_EntryLo1);
	108	qemu_put_betls(f, &env->CP0_Context);
	109	qemu_put_sbe32s(f, &env->CP0_PageMask);
	110	qemu_put_sbe32s(f, &env->CP0_PageGrain);
	111	qemu_put_sbe32s(f, &env->CP0_Wired);
	112	qemu_put_sbe32s(f, &env->CP0_SRSConf0);
	113	qemu_put_sbe32s(f, &env->CP0_SRSConf1);
	114	qemu_put_sbe32s(f, &env->CP0_SRSConf2);
	115	qemu_put_sbe32s(f, &env->CP0_SRSConf3);
	116	qemu_put_sbe32s(f, &env->CP0_SRSConf4);
	117	qemu_put_sbe32s(f, &env->CP0_HWREna);
	118	qemu_put_betls(f, &env->CP0_BadVAddr);
460c81f1 LA	119	qemu_put_be32s(f, &env->CP0_BadInstr);
460c81f1 LA	120	qemu_put_be32s(f, &env->CP0_BadInstrP);
33a84765 TS	121	qemu_put_sbe32s(f, &env->CP0_Count);
	122	qemu_put_betls(f, &env->CP0_EntryHi);
	123	qemu_put_sbe32s(f, &env->CP0_Compare);
	124	qemu_put_sbe32s(f, &env->CP0_Status);
	125	qemu_put_sbe32s(f, &env->CP0_IntCtl);
	126	qemu_put_sbe32s(f, &env->CP0_SRSCtl);
	127	qemu_put_sbe32s(f, &env->CP0_SRSMap);
	128	qemu_put_sbe32s(f, &env->CP0_Cause);
	129	qemu_put_betls(f, &env->CP0_EPC);
	130	qemu_put_sbe32s(f, &env->CP0_PRid);
	131	qemu_put_sbe32s(f, &env->CP0_EBase);
	132	qemu_put_sbe32s(f, &env->CP0_Config0);
	133	qemu_put_sbe32s(f, &env->CP0_Config1);
	134	qemu_put_sbe32s(f, &env->CP0_Config2);
	135	qemu_put_sbe32s(f, &env->CP0_Config3);
	136	qemu_put_sbe32s(f, &env->CP0_Config6);
	137	qemu_put_sbe32s(f, &env->CP0_Config7);
5499b6ff	138	qemu_put_betls(f, &env->lladdr);
33a84765 TS	139	for(i = 0; i < 8; i++)
	140	qemu_put_betls(f, &env->CP0_WatchLo[i]);
	141	for(i = 0; i < 8; i++)
	142	qemu_put_sbe32s(f, &env->CP0_WatchHi[i]);
	143	qemu_put_betls(f, &env->CP0_XContext);
	144	qemu_put_sbe32s(f, &env->CP0_Framemask);
	145	qemu_put_sbe32s(f, &env->CP0_Debug);
	146	qemu_put_betls(f, &env->CP0_DEPC);
	147	qemu_put_sbe32s(f, &env->CP0_Performance0);
	148	qemu_put_sbe32s(f, &env->CP0_TagLo);
	149	qemu_put_sbe32s(f, &env->CP0_DataLo);
	150	qemu_put_sbe32s(f, &env->CP0_TagHi);
	151	qemu_put_sbe32s(f, &env->CP0_DataHi);
	152	qemu_put_betls(f, &env->CP0_ErrorEPC);
	153	qemu_put_sbe32s(f, &env->CP0_DESAVE);
460c81f1 LA	154	for (i = 0; i < MIPS_KSCRATCH_NUM; i++) {
	155	qemu_put_betls(f, &env->CP0_KScratch[i]);
	156	}
33a84765 TS	157
	158	/* Save inactive TC state */
	159	for (i = 0; i < MIPS_SHADOW_SET_MAX; i++)
	160	save_tc(f, &env->tcs[i]);
	161	for (i = 0; i < MIPS_FPU_MAX; i++)
	162	save_fpu(f, &env->fpus[i]);
	163	}
	164
d279279e	165	static void load_tc(QEMUFile f, TCState tc, int version_id)
33a84765 TS	166	{
	167	int i;
	168
	169	/* Save active TC */
	170	for(i = 0; i < 32; i++)
	171	qemu_get_betls(f, &tc->gpr[i]);
	172	qemu_get_betls(f, &tc->PC);
	173	for(i = 0; i < MIPS_DSP_ACC; i++)
	174	qemu_get_betls(f, &tc->HI[i]);
	175	for(i = 0; i < MIPS_DSP_ACC; i++)
	176	qemu_get_betls(f, &tc->LO[i]);
	177	for(i = 0; i < MIPS_DSP_ACC; i++)
	178	qemu_get_betls(f, &tc->ACX[i]);
	179	qemu_get_betls(f, &tc->DSPControl);
	180	qemu_get_sbe32s(f, &tc->CP0_TCStatus);
	181	qemu_get_sbe32s(f, &tc->CP0_TCBind);
	182	qemu_get_betls(f, &tc->CP0_TCHalt);
	183	qemu_get_betls(f, &tc->CP0_TCContext);
	184	qemu_get_betls(f, &tc->CP0_TCSchedule);
	185	qemu_get_betls(f, &tc->CP0_TCScheFBack);
	186	qemu_get_sbe32s(f, &tc->CP0_Debug_tcstatus);
d279279e PJ	187	if (version_id >= 4) {
	188	qemu_get_betls(f, &tc->CP0_UserLocal);
	189	}
33a84765 TS	190	}
	191
	192	static void load_fpu(QEMUFile f, CPUMIPSFPUContext fpu)
	193	{
	194	int i;
	195
	196	for(i = 0; i < 32; i++)
	197	qemu_get_be64s(f, &fpu->fpr[i].d);
	198	qemu_get_s8s(f, &fpu->fp_status.float_detect_tininess);
	199	qemu_get_s8s(f, &fpu->fp_status.float_rounding_mode);
	200	qemu_get_s8s(f, &fpu->fp_status.float_exception_flags);
	201	qemu_get_be32s(f, &fpu->fcr0);
	202	qemu_get_be32s(f, &fpu->fcr31);
8dd3dca3 AJ	203	}
	204
	205	int cpu_load(QEMUFile f, void opaque, int version_id)
	206	{
7db13fae	207	CPUMIPSState *env = opaque;
00c8cb0a	208	MIPSCPU *cpu = mips_env_get_cpu(env);
33a84765 TS	209	int i;
33a84765 TS	210
d279279e	211	if (version_id < 3) {
33a84765	212	return -EINVAL;
d279279e	213	}
33a84765 TS	214
33a84765 TS	215	/* Load active TC */
d279279e	216	load_tc(f, &env->active_tc, version_id);
33a84765 TS	217
	218	/* Load active FPU */
	219	load_fpu(f, &env->active_fpu);
	220
	221	/* Load MVP */
	222	qemu_get_sbe32s(f, &env->mvp->CP0_MVPControl);
	223	qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf0);
	224	qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf1);
	225
	226	/* Load TLB */
	227	qemu_get_be32s(f, &env->tlb->nb_tlb);
	228	qemu_get_be32s(f, &env->tlb->tlb_in_use);
	229	for(i = 0; i < MIPS_TLB_MAX; i++) {
	230	uint16_t flags;
95bed643	231	uint8_t asid;
33a84765 TS	232
	233	qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN);
	234	qemu_get_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask);
95bed643 BS	235	qemu_get_8s(f, &asid);
95bed643 BS	236	env->tlb->mmu.r4k.tlb[i].ASID = asid;
33a84765 TS	237	qemu_get_be16s(f, &flags);
	238	env->tlb->mmu.r4k.tlb[i].G = (flags >> 10) & 1;
	239	env->tlb->mmu.r4k.tlb[i].C0 = (flags >> 7) & 3;
	240	env->tlb->mmu.r4k.tlb[i].C1 = (flags >> 4) & 3;
	241	env->tlb->mmu.r4k.tlb[i].V0 = (flags >> 3) & 1;
	242	env->tlb->mmu.r4k.tlb[i].V1 = (flags >> 2) & 1;
	243	env->tlb->mmu.r4k.tlb[i].D0 = (flags >> 1) & 1;
	244	env->tlb->mmu.r4k.tlb[i].D1 = (flags >> 0) & 1;
460c81f1 LA	245	if (version_id >= 5) {
	246	env->tlb->mmu.r4k.tlb[i].EHINV = (flags >> 15) & 1;
	247	env->tlb->mmu.r4k.tlb[i].RI1 = (flags >> 14) & 1;
	248	env->tlb->mmu.r4k.tlb[i].RI0 = (flags >> 13) & 1;
	249	env->tlb->mmu.r4k.tlb[i].XI1 = (flags >> 12) & 1;
	250	env->tlb->mmu.r4k.tlb[i].XI0 = (flags >> 11) & 1;
	251	}
33a84765 TS	252	qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]);
	253	qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]);
	254	}
	255
	256	/* Load CPU metastate */
	257	qemu_get_be32s(f, &env->current_tc);
	258	qemu_get_be32s(f, &env->current_fpu);
	259	qemu_get_sbe32s(f, &env->error_code);
	260	qemu_get_be32s(f, &env->hflags);
	261	qemu_get_betls(f, &env->btarget);
1ba74fb8 AJ	262	qemu_get_sbe32s(f, &i);
1ba74fb8 AJ	263	env->bcond = i;
33a84765 TS	264
	265	/* Load remaining CP1 registers */
	266	qemu_get_sbe32s(f, &env->CP0_Index);
	267	qemu_get_sbe32s(f, &env->CP0_Random);
	268	qemu_get_sbe32s(f, &env->CP0_VPEControl);
	269	qemu_get_sbe32s(f, &env->CP0_VPEConf0);
	270	qemu_get_sbe32s(f, &env->CP0_VPEConf1);
	271	qemu_get_betls(f, &env->CP0_YQMask);
	272	qemu_get_betls(f, &env->CP0_VPESchedule);
	273	qemu_get_betls(f, &env->CP0_VPEScheFBack);
	274	qemu_get_sbe32s(f, &env->CP0_VPEOpt);
	275	qemu_get_betls(f, &env->CP0_EntryLo0);
	276	qemu_get_betls(f, &env->CP0_EntryLo1);
	277	qemu_get_betls(f, &env->CP0_Context);
	278	qemu_get_sbe32s(f, &env->CP0_PageMask);
	279	qemu_get_sbe32s(f, &env->CP0_PageGrain);
	280	qemu_get_sbe32s(f, &env->CP0_Wired);
	281	qemu_get_sbe32s(f, &env->CP0_SRSConf0);
	282	qemu_get_sbe32s(f, &env->CP0_SRSConf1);
	283	qemu_get_sbe32s(f, &env->CP0_SRSConf2);
	284	qemu_get_sbe32s(f, &env->CP0_SRSConf3);
	285	qemu_get_sbe32s(f, &env->CP0_SRSConf4);
	286	qemu_get_sbe32s(f, &env->CP0_HWREna);
	287	qemu_get_betls(f, &env->CP0_BadVAddr);
	288	qemu_get_sbe32s(f, &env->CP0_Count);
	289	qemu_get_betls(f, &env->CP0_EntryHi);
	290	qemu_get_sbe32s(f, &env->CP0_Compare);
	291	qemu_get_sbe32s(f, &env->CP0_Status);
	292	qemu_get_sbe32s(f, &env->CP0_IntCtl);
	293	qemu_get_sbe32s(f, &env->CP0_SRSCtl);
	294	qemu_get_sbe32s(f, &env->CP0_SRSMap);
	295	qemu_get_sbe32s(f, &env->CP0_Cause);
	296	qemu_get_betls(f, &env->CP0_EPC);
	297	qemu_get_sbe32s(f, &env->CP0_PRid);
	298	qemu_get_sbe32s(f, &env->CP0_EBase);
	299	qemu_get_sbe32s(f, &env->CP0_Config0);
	300	qemu_get_sbe32s(f, &env->CP0_Config1);
	301	qemu_get_sbe32s(f, &env->CP0_Config2);
	302	qemu_get_sbe32s(f, &env->CP0_Config3);
	303	qemu_get_sbe32s(f, &env->CP0_Config6);
	304	qemu_get_sbe32s(f, &env->CP0_Config7);
5499b6ff	305	qemu_get_betls(f, &env->lladdr);
33a84765 TS	306	for(i = 0; i < 8; i++)
	307	qemu_get_betls(f, &env->CP0_WatchLo[i]);
	308	for(i = 0; i < 8; i++)
	309	qemu_get_sbe32s(f, &env->CP0_WatchHi[i]);
	310	qemu_get_betls(f, &env->CP0_XContext);
	311	qemu_get_sbe32s(f, &env->CP0_Framemask);
	312	qemu_get_sbe32s(f, &env->CP0_Debug);
	313	qemu_get_betls(f, &env->CP0_DEPC);
	314	qemu_get_sbe32s(f, &env->CP0_Performance0);
	315	qemu_get_sbe32s(f, &env->CP0_TagLo);
	316	qemu_get_sbe32s(f, &env->CP0_DataLo);
	317	qemu_get_sbe32s(f, &env->CP0_TagHi);
	318	qemu_get_sbe32s(f, &env->CP0_DataHi);
	319	qemu_get_betls(f, &env->CP0_ErrorEPC);
	320	qemu_get_sbe32s(f, &env->CP0_DESAVE);
460c81f1 LA	321	if (version_id >= 5) {
	322	qemu_get_be32s(f, &env->CP0_BadInstr);
	323	qemu_get_be32s(f, &env->CP0_BadInstrP);
	324	for (i = 0; i < MIPS_KSCRATCH_NUM; i++) {
	325	qemu_get_betls(f, &env->CP0_KScratch[i]);
	326	}
	327	}
33a84765 TS	328
33a84765 TS	329	/* Load inactive TC state */
d279279e PJ	330	for (i = 0; i < MIPS_SHADOW_SET_MAX; i++) {
	331	load_tc(f, &env->tcs[i], version_id);
	332	}
33a84765 TS	333	for (i = 0; i < MIPS_FPU_MAX; i++)
	334	load_fpu(f, &env->fpus[i]);
	335
4abf79a4	336	/* XXX: ensure compatibility for halted bit ? */
00c8cb0a	337	tlb_flush(CPU(cpu), 1);
8dd3dca3 AJ	338	return 0;
8dd3dca3 AJ	339	}