[qemu.git] / hw / lm32_boards.c

/*
 *  QEMU models for LatticeMico32 uclinux and evr32 boards.
 *
 *  Copyright (c) 2010 Michael Walle <[email protected]>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "sysbus.h"
#include "hw.h"
#include "net.h"
#include "flash.h"
#include "devices.h"
#include "boards.h"
#include "loader.h"
#include "blockdev.h"
#include "elf.h"
#include "lm32_hwsetup.h"
#include "lm32.h"
#include "exec-memory.h"

typedef struct {
    LM32CPU *cpu;
    target_phys_addr_t bootstrap_pc;
    target_phys_addr_t flash_base;
    target_phys_addr_t hwsetup_base;
    target_phys_addr_t initrd_base;
    size_t initrd_size;
    target_phys_addr_t cmdline_base;
} ResetInfo;

static void cpu_irq_handler(void *opaque, int irq, int level)
{
    CPULM32State *env = opaque;

    if (level) {
        cpu_interrupt(env, CPU_INTERRUPT_HARD);
    } else {
        cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
    }
}

static void main_cpu_reset(void *opaque)
{
    ResetInfo *reset_info = opaque;
    CPULM32State *env = &reset_info->cpu->env;

    cpu_reset(CPU(reset_info->cpu));

    /* init defaults */
    env->pc = (uint32_t)reset_info->bootstrap_pc;
    env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
    env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
    env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
    env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
        reset_info->initrd_size);
    env->eba = reset_info->flash_base;
    env->deba = reset_info->flash_base;
}

static void lm32_evr_init(ram_addr_t ram_size_not_used,
                          const char *boot_device,
                          const char *kernel_filename,
                          const char *kernel_cmdline,
                          const char *initrd_filename, const char *cpu_model)
{
    LM32CPU *cpu;
    CPULM32State *env;
    DriveInfo *dinfo;
    MemoryRegion *address_space_mem =  get_system_memory();
    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
    qemu_irq *cpu_irq, irq[32];
    ResetInfo *reset_info;
    int i;

    /* memory map */
    target_phys_addr_t flash_base  = 0x04000000;
    size_t flash_sector_size       = 256 * 1024;
    size_t flash_size              = 32 * 1024 * 1024;
    target_phys_addr_t ram_base    = 0x08000000;
    size_t ram_size                = 64 * 1024 * 1024;
    target_phys_addr_t timer0_base = 0x80002000;
    target_phys_addr_t uart0_base  = 0x80006000;
    target_phys_addr_t timer1_base = 0x8000a000;
    int uart0_irq                  = 0;
    int timer0_irq                 = 1;
    int timer1_irq                 = 3;

    reset_info = g_malloc0(sizeof(ResetInfo));

    if (cpu_model == NULL) {
        cpu_model = "lm32-full";
    }
    cpu = cpu_lm32_init(cpu_model);
    env = &cpu->env;
    reset_info->cpu = cpu;

    reset_info->flash_base = flash_base;

    memory_region_init_ram(phys_ram, "lm32_evr.sdram", ram_size);
    vmstate_register_ram_global(phys_ram);
    memory_region_add_subregion(address_space_mem, ram_base, phys_ram);

    dinfo = drive_get(IF_PFLASH, 0, 0);
    /* Spansion S29NS128P */
    pflash_cfi02_register(flash_base, NULL, "lm32_evr.flash", flash_size,
                          dinfo ? dinfo->bdrv : NULL, flash_sector_size,
                          flash_size / flash_sector_size, 1, 2,
                          0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);

    /* create irq lines */
    cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
    env->pic_state = lm32_pic_init(*cpu_irq);
    for (i = 0; i < 32; i++) {
        irq[i] = qdev_get_gpio_in(env->pic_state, i);
    }

    sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
    sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
    sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);

    /* make sure juart isn't the first chardev */
    env->juart_state = lm32_juart_init();

    reset_info->bootstrap_pc = flash_base;

    if (kernel_filename) {
        uint64_t entry;
        int kernel_size;

        kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
                               1, ELF_MACHINE, 0);
        reset_info->bootstrap_pc = entry;

        if (kernel_size < 0) {
            kernel_size = load_image_targphys(kernel_filename, ram_base,
                                              ram_size);
            reset_info->bootstrap_pc = ram_base;
        }

        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
                    kernel_filename);
            exit(1);
        }
    }

    qemu_register_reset(main_cpu_reset, reset_info);
}

static void lm32_uclinux_init(ram_addr_t ram_size_not_used,
                          const char *boot_device,
                          const char *kernel_filename,
                          const char *kernel_cmdline,
                          const char *initrd_filename, const char *cpu_model)
{
    LM32CPU *cpu;
    CPULM32State *env;
    DriveInfo *dinfo;
    MemoryRegion *address_space_mem =  get_system_memory();
    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
    qemu_irq *cpu_irq, irq[32];
    HWSetup *hw;
    ResetInfo *reset_info;
    int i;

    /* memory map */
    target_phys_addr_t flash_base   = 0x04000000;
    size_t flash_sector_size        = 256 * 1024;
    size_t flash_size               = 32 * 1024 * 1024;
    target_phys_addr_t ram_base     = 0x08000000;
    size_t ram_size                 = 64 * 1024 * 1024;
    target_phys_addr_t uart0_base   = 0x80000000;
    target_phys_addr_t timer0_base  = 0x80002000;
    target_phys_addr_t timer1_base  = 0x80010000;
    target_phys_addr_t timer2_base  = 0x80012000;
    int uart0_irq                   = 0;
    int timer0_irq                  = 1;
    int timer1_irq                  = 20;
    int timer2_irq                  = 21;
    target_phys_addr_t hwsetup_base = 0x0bffe000;
    target_phys_addr_t cmdline_base = 0x0bfff000;
    target_phys_addr_t initrd_base  = 0x08400000;
    size_t initrd_max               = 0x01000000;

    reset_info = g_malloc0(sizeof(ResetInfo));

    if (cpu_model == NULL) {
        cpu_model = "lm32-full";
    }
    cpu = cpu_lm32_init(cpu_model);
    env = &cpu->env;
    reset_info->cpu = cpu;

    reset_info->flash_base = flash_base;

    memory_region_init_ram(phys_ram, "lm32_uclinux.sdram", ram_size);
    vmstate_register_ram_global(phys_ram);
    memory_region_add_subregion(address_space_mem, ram_base, phys_ram);

    dinfo = drive_get(IF_PFLASH, 0, 0);
    /* Spansion S29NS128P */
    pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
                          dinfo ? dinfo->bdrv : NULL, flash_sector_size,
                          flash_size / flash_sector_size, 1, 2,
                          0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);

    /* create irq lines */
    cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
    env->pic_state = lm32_pic_init(*cpu_irq);
    for (i = 0; i < 32; i++) {
        irq[i] = qdev_get_gpio_in(env->pic_state, i);
    }

    sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
    sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
    sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
    sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);

    /* make sure juart isn't the first chardev */
    env->juart_state = lm32_juart_init();

    reset_info->bootstrap_pc = flash_base;

    if (kernel_filename) {
        uint64_t entry;
        int kernel_size;

        kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
                               1, ELF_MACHINE, 0);
        reset_info->bootstrap_pc = entry;

        if (kernel_size < 0) {
            kernel_size = load_image_targphys(kernel_filename, ram_base,
                                              ram_size);
            reset_info->bootstrap_pc = ram_base;
        }

        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
                    kernel_filename);
            exit(1);
        }
    }

    /* generate a rom with the hardware description */
    hw = hwsetup_init();
    hwsetup_add_cpu(hw, "LM32", 75000000);
    hwsetup_add_flash(hw, "flash", flash_base, flash_size);
    hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
    hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
    hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
    hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
    hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
    hwsetup_add_trailer(hw);
    hwsetup_create_rom(hw, hwsetup_base);
    hwsetup_free(hw);

    reset_info->hwsetup_base = hwsetup_base;

    if (kernel_cmdline && strlen(kernel_cmdline)) {
        pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
                kernel_cmdline);
        reset_info->cmdline_base = cmdline_base;
    }

    if (initrd_filename) {
        size_t initrd_size;
        initrd_size = load_image_targphys(initrd_filename, initrd_base,
                initrd_max);
        reset_info->initrd_base = initrd_base;
        reset_info->initrd_size = initrd_size;
    }

    qemu_register_reset(main_cpu_reset, reset_info);
}

static QEMUMachine lm32_evr_machine = {
    .name = "lm32-evr",
    .desc = "LatticeMico32 EVR32 eval system",
    .init = lm32_evr_init,
    .is_default = 1
};

static QEMUMachine lm32_uclinux_machine = {
    .name = "lm32-uclinux",
    .desc = "lm32 platform for uClinux and u-boot by Theobroma Systems",
    .init = lm32_uclinux_init,
    .is_default = 0
};

static void lm32_machine_init(void)
{
    qemu_register_machine(&lm32_uclinux_machine);
    qemu_register_machine(&lm32_evr_machine);
}

machine_init(lm32_machine_init);
Commit	Line	Data
d821732a MW	1	/*
	2	* QEMU models for LatticeMico32 uclinux and evr32 boards.
	3	*
	4	* Copyright (c) 2010 Michael Walle <[email protected]>
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include "sysbus.h"
	21	#include "hw.h"
	22	#include "net.h"
	23	#include "flash.h"
d821732a MW	24	#include "devices.h"
	25	#include "boards.h"
	26	#include "loader.h"
	27	#include "blockdev.h"
	28	#include "elf.h"
	29	#include "lm32_hwsetup.h"
	30	#include "lm32.h"
88fa8031	31	#include "exec-memory.h"
d821732a MW	32
d821732a MW	33	typedef struct {
b1435596	34	LM32CPU *cpu;
d821732a MW	35	target_phys_addr_t bootstrap_pc;
	36	target_phys_addr_t flash_base;
	37	target_phys_addr_t hwsetup_base;
	38	target_phys_addr_t initrd_base;
	39	size_t initrd_size;
	40	target_phys_addr_t cmdline_base;
	41	} ResetInfo;
	42
	43	static void cpu_irq_handler(void *opaque, int irq, int level)
	44	{
93a67402	45	CPULM32State *env = opaque;
d821732a MW	46
	47	if (level) {
	48	cpu_interrupt(env, CPU_INTERRUPT_HARD);
	49	} else {
	50	cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
	51	}
	52	}
	53
	54	static void main_cpu_reset(void *opaque)
	55	{
	56	ResetInfo *reset_info = opaque;
b1435596	57	CPULM32State *env = &reset_info->cpu->env;
d821732a	58
b1435596	59	cpu_reset(CPU(reset_info->cpu));
d821732a MW	60
	61	/* init defaults */
	62	env->pc = (uint32_t)reset_info->bootstrap_pc;
	63	env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
	64	env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
	65	env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
	66	env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
	67	reset_info->initrd_size);
	68	env->eba = reset_info->flash_base;
	69	env->deba = reset_info->flash_base;
	70	}
	71
	72	static void lm32_evr_init(ram_addr_t ram_size_not_used,
	73	const char *boot_device,
	74	const char *kernel_filename,
	75	const char *kernel_cmdline,
	76	const char initrd_filename, const char cpu_model)
	77	{
47dc4fa2	78	LM32CPU *cpu;
93a67402	79	CPULM32State *env;
d821732a	80	DriveInfo *dinfo;
88fa8031 AK	81	MemoryRegion *address_space_mem = get_system_memory();
88fa8031 AK	82	MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
d821732a MW	83	qemu_irq *cpu_irq, irq[32];
	84	ResetInfo *reset_info;
	85	int i;
	86
	87	/* memory map */
	88	target_phys_addr_t flash_base = 0x04000000;
	89	size_t flash_sector_size = 256 * 1024;
	90	size_t flash_size = 32 * 1024 * 1024;
	91	target_phys_addr_t ram_base = 0x08000000;
	92	size_t ram_size = 64 * 1024 * 1024;
	93	target_phys_addr_t timer0_base = 0x80002000;
	94	target_phys_addr_t uart0_base = 0x80006000;
	95	target_phys_addr_t timer1_base = 0x8000a000;
	96	int uart0_irq = 0;
	97	int timer0_irq = 1;
	98	int timer1_irq = 3;
	99
7267c094	100	reset_info = g_malloc0(sizeof(ResetInfo));
d821732a MW	101
	102	if (cpu_model == NULL) {
	103	cpu_model = "lm32-full";
	104	}
47dc4fa2 AF	105	cpu = cpu_lm32_init(cpu_model);
47dc4fa2 AF	106	env = &cpu->env;
b1435596	107	reset_info->cpu = cpu;
d821732a MW	108
	109	reset_info->flash_base = flash_base;
	110
c5705a77 AK	111	memory_region_init_ram(phys_ram, "lm32_evr.sdram", ram_size);
c5705a77 AK	112	vmstate_register_ram_global(phys_ram);
88fa8031	113	memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
d821732a	114
d821732a MW	115	dinfo = drive_get(IF_PFLASH, 0, 0);
d821732a MW	116	/* Spansion S29NS128P */
cfe5f011	117	pflash_cfi02_register(flash_base, NULL, "lm32_evr.flash", flash_size,
d821732a MW	118	dinfo ? dinfo->bdrv : NULL, flash_sector_size,
d821732a MW	119	flash_size / flash_sector_size, 1, 2,
01e0451a	120	0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
d821732a MW	121
	122	/* create irq lines */
	123	cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
	124	env->pic_state = lm32_pic_init(*cpu_irq);
	125	for (i = 0; i < 32; i++) {
	126	irq[i] = qdev_get_gpio_in(env->pic_state, i);
	127	}
	128
	129	sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
	130	sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
	131	sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
	132
	133	/* make sure juart isn't the first chardev */
	134	env->juart_state = lm32_juart_init();
	135
	136	reset_info->bootstrap_pc = flash_base;
	137
	138	if (kernel_filename) {
	139	uint64_t entry;
	140	int kernel_size;
	141
	142	kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
	143	1, ELF_MACHINE, 0);
	144	reset_info->bootstrap_pc = entry;
	145
	146	if (kernel_size < 0) {
	147	kernel_size = load_image_targphys(kernel_filename, ram_base,
	148	ram_size);
	149	reset_info->bootstrap_pc = ram_base;
	150	}
	151
	152	if (kernel_size < 0) {
	153	fprintf(stderr, "qemu: could not load kernel '%s'\n",
	154	kernel_filename);
	155	exit(1);
	156	}
	157	}
	158
	159	qemu_register_reset(main_cpu_reset, reset_info);
	160	}
	161
	162	static void lm32_uclinux_init(ram_addr_t ram_size_not_used,
	163	const char *boot_device,
	164	const char *kernel_filename,
	165	const char *kernel_cmdline,
	166	const char initrd_filename, const char cpu_model)
	167	{
47dc4fa2	168	LM32CPU *cpu;
93a67402	169	CPULM32State *env;
d821732a	170	DriveInfo *dinfo;
88fa8031 AK	171	MemoryRegion *address_space_mem = get_system_memory();
88fa8031 AK	172	MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
d821732a MW	173	qemu_irq *cpu_irq, irq[32];
	174	HWSetup *hw;
	175	ResetInfo *reset_info;
	176	int i;
	177
	178	/* memory map */
	179	target_phys_addr_t flash_base = 0x04000000;
	180	size_t flash_sector_size = 256 * 1024;
	181	size_t flash_size = 32 * 1024 * 1024;
	182	target_phys_addr_t ram_base = 0x08000000;
	183	size_t ram_size = 64 * 1024 * 1024;
	184	target_phys_addr_t uart0_base = 0x80000000;
	185	target_phys_addr_t timer0_base = 0x80002000;
	186	target_phys_addr_t timer1_base = 0x80010000;
	187	target_phys_addr_t timer2_base = 0x80012000;
	188	int uart0_irq = 0;
	189	int timer0_irq = 1;
	190	int timer1_irq = 20;
	191	int timer2_irq = 21;
	192	target_phys_addr_t hwsetup_base = 0x0bffe000;
	193	target_phys_addr_t cmdline_base = 0x0bfff000;
	194	target_phys_addr_t initrd_base = 0x08400000;
	195	size_t initrd_max = 0x01000000;
	196
7267c094	197	reset_info = g_malloc0(sizeof(ResetInfo));
d821732a MW	198
	199	if (cpu_model == NULL) {
	200	cpu_model = "lm32-full";
	201	}
47dc4fa2 AF	202	cpu = cpu_lm32_init(cpu_model);
47dc4fa2 AF	203	env = &cpu->env;
b1435596	204	reset_info->cpu = cpu;
d821732a MW	205
	206	reset_info->flash_base = flash_base;
	207
c5705a77 AK	208	memory_region_init_ram(phys_ram, "lm32_uclinux.sdram", ram_size);
c5705a77 AK	209	vmstate_register_ram_global(phys_ram);
88fa8031	210	memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
d821732a	211
d821732a MW	212	dinfo = drive_get(IF_PFLASH, 0, 0);
d821732a MW	213	/* Spansion S29NS128P */
cfe5f011	214	pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
d821732a MW	215	dinfo ? dinfo->bdrv : NULL, flash_sector_size,
d821732a MW	216	flash_size / flash_sector_size, 1, 2,
01e0451a	217	0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
d821732a MW	218
	219	/* create irq lines */
	220	cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
	221	env->pic_state = lm32_pic_init(*cpu_irq);
	222	for (i = 0; i < 32; i++) {
	223	irq[i] = qdev_get_gpio_in(env->pic_state, i);
	224	}
	225
	226	sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
	227	sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
	228	sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
	229	sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);
	230
	231	/* make sure juart isn't the first chardev */
	232	env->juart_state = lm32_juart_init();
	233
	234	reset_info->bootstrap_pc = flash_base;
	235
	236	if (kernel_filename) {
	237	uint64_t entry;
	238	int kernel_size;
	239
	240	kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
	241	1, ELF_MACHINE, 0);
	242	reset_info->bootstrap_pc = entry;
	243
	244	if (kernel_size < 0) {
	245	kernel_size = load_image_targphys(kernel_filename, ram_base,
	246	ram_size);
	247	reset_info->bootstrap_pc = ram_base;
	248	}
	249
	250	if (kernel_size < 0) {
	251	fprintf(stderr, "qemu: could not load kernel '%s'\n",
	252	kernel_filename);
	253	exit(1);
	254	}
	255	}
	256
	257	/* generate a rom with the hardware description */
	258	hw = hwsetup_init();
	259	hwsetup_add_cpu(hw, "LM32", 75000000);
	260	hwsetup_add_flash(hw, "flash", flash_base, flash_size);
	261	hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
	262	hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
	263	hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
	264	hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
	265	hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
	266	hwsetup_add_trailer(hw);
	267	hwsetup_create_rom(hw, hwsetup_base);
	268	hwsetup_free(hw);
	269
	270	reset_info->hwsetup_base = hwsetup_base;
	271
	272	if (kernel_cmdline && strlen(kernel_cmdline)) {
	273	pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
	274	kernel_cmdline);
	275	reset_info->cmdline_base = cmdline_base;
	276	}
	277
	278	if (initrd_filename) {
	279	size_t initrd_size;
	280	initrd_size = load_image_targphys(initrd_filename, initrd_base,
	281	initrd_max);
282	reset_info->initrd_base = initrd_base;
283	reset_info->initrd_size = initrd_size;
284	}
285
286	qemu_register_reset(main_cpu_reset, reset_info);
287	}
288
289	static QEMUMachine lm32_evr_machine = {
290	.name = "lm32-evr",
291	.desc = "LatticeMico32 EVR32 eval system",
292	.init = lm32_evr_init,
293	.is_default = 1
294	};
295
296	static QEMUMachine lm32_uclinux_machine = {
297	.name = "lm32-uclinux",
298	.desc = "lm32 platform for uClinux and u-boot by Theobroma Systems",
299	.init = lm32_uclinux_init,
300	.is_default = 0
301	};
302
303	static void lm32_machine_init(void)
304	{
305	qemu_register_machine(&lm32_uclinux_machine);
306	qemu_register_machine(&lm32_evr_machine);
307	}
308
309	machine_init(lm32_machine_init);