[qemu.git] / hw / ide / macio.c

/*
 * QEMU IDE Emulation: MacIO support.
 *
 * Copyright (c) 2003 Fabrice Bellard
 * Copyright (c) 2006 Openedhand Ltd.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw/hw.h"
#include "hw/ppc/mac.h"
#include "hw/ppc/mac_dbdma.h"
#include "block/block.h"
#include "sysemu/dma.h"

#include <hw/ide/internal.h>

/***********************************************************/
/* MacIO based PowerPC IDE */

#define MACIO_PAGE_SIZE 4096

static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
{
    DBDMA_io *io = opaque;
    MACIOIDEState *m = io->opaque;
    IDEState *s = idebus_active_if(&m->bus);

    if (ret < 0) {
        m->aiocb = NULL;
        qemu_sglist_destroy(&s->sg);
        ide_atapi_io_error(s, ret);
        goto done;
    }

    if (s->io_buffer_size > 0) {
        m->aiocb = NULL;
        qemu_sglist_destroy(&s->sg);

        s->packet_transfer_size -= s->io_buffer_size;

        s->io_buffer_index += s->io_buffer_size;
	s->lba += s->io_buffer_index >> 11;
        s->io_buffer_index &= 0x7ff;
    }

    if (s->packet_transfer_size <= 0)
        ide_atapi_cmd_ok(s);

    if (io->len == 0) {
        goto done;
    }

    /* launch next transfer */

    s->io_buffer_size = io->len;

    qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,
                     &address_space_memory);
    qemu_sglist_add(&s->sg, io->addr, io->len);
    io->addr += io->len;
    io->len = 0;

    m->aiocb = dma_bdrv_read(s->bs, &s->sg,
                             (int64_t)(s->lba << 2) + (s->io_buffer_index >> 9),
                             pmac_ide_atapi_transfer_cb, io);
    return;

done:
    bdrv_acct_done(s->bs, &s->acct);
    io->dma_end(opaque);
}

static void pmac_ide_transfer_cb(void *opaque, int ret)
{
    DBDMA_io *io = opaque;
    MACIOIDEState *m = io->opaque;
    IDEState *s = idebus_active_if(&m->bus);
    int n;
    int64_t sector_num;

    if (ret < 0) {
        m->aiocb = NULL;
        qemu_sglist_destroy(&s->sg);
	ide_dma_error(s);
        goto done;
    }

    sector_num = ide_get_sector(s);
    if (s->io_buffer_size > 0) {
        m->aiocb = NULL;
        qemu_sglist_destroy(&s->sg);
        n = (s->io_buffer_size + 0x1ff) >> 9;
        sector_num += n;
        ide_set_sector(s, sector_num);
        s->nsector -= n;
    }

    /* end of transfer ? */
    if (s->nsector == 0) {
        s->status = READY_STAT | SEEK_STAT;
        ide_set_irq(s->bus);
    }

    /* end of DMA ? */
    if (io->len == 0) {
        goto done;
    }

    /* launch next transfer */

    s->io_buffer_index = 0;
    s->io_buffer_size = io->len;

    qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,
                     &address_space_memory);
    qemu_sglist_add(&s->sg, io->addr, io->len);
    io->addr += io->len;
    io->len = 0;

    switch (s->dma_cmd) {
    case IDE_DMA_READ:
        m->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
		                 pmac_ide_transfer_cb, io);
        break;
    case IDE_DMA_WRITE:
        m->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
		                  pmac_ide_transfer_cb, io);
        break;
    case IDE_DMA_TRIM:
        m->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num,
                               ide_issue_trim, pmac_ide_transfer_cb, io,
                               DMA_DIRECTION_TO_DEVICE);
        break;
    }
    return;

done:
    if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
        bdrv_acct_done(s->bs, &s->acct);
    }
    io->dma_end(io);
}

static void pmac_ide_transfer(DBDMA_io *io)
{
    MACIOIDEState *m = io->opaque;
    IDEState *s = idebus_active_if(&m->bus);

    s->io_buffer_size = 0;
    if (s->drive_kind == IDE_CD) {
        bdrv_acct_start(s->bs, &s->acct, io->len, BDRV_ACCT_READ);
        pmac_ide_atapi_transfer_cb(io, 0);
        return;
    }

    switch (s->dma_cmd) {
    case IDE_DMA_READ:
        bdrv_acct_start(s->bs, &s->acct, io->len, BDRV_ACCT_READ);
        break;
    case IDE_DMA_WRITE:
        bdrv_acct_start(s->bs, &s->acct, io->len, BDRV_ACCT_WRITE);
        break;
    default:
        break;
    }

    pmac_ide_transfer_cb(io, 0);
}

static void pmac_ide_flush(DBDMA_io *io)
{
    MACIOIDEState *m = io->opaque;

    if (m->aiocb) {
        bdrv_drain_all();
    }
}

/* PowerMac IDE memory IO */
static void pmac_ide_writeb (void *opaque,
                             hwaddr addr, uint32_t val)
{
    MACIOIDEState *d = opaque;

    addr = (addr & 0xFFF) >> 4;
    switch (addr) {
    case 1 ... 7:
        ide_ioport_write(&d->bus, addr, val);
        break;
    case 8:
    case 22:
        ide_cmd_write(&d->bus, 0, val);
        break;
    default:
        break;
    }
}

static uint32_t pmac_ide_readb (void *opaque,hwaddr addr)
{
    uint8_t retval;
    MACIOIDEState *d = opaque;

    addr = (addr & 0xFFF) >> 4;
    switch (addr) {
    case 1 ... 7:
        retval = ide_ioport_read(&d->bus, addr);
        break;
    case 8:
    case 22:
        retval = ide_status_read(&d->bus, 0);
        break;
    default:
        retval = 0xFF;
        break;
    }
    return retval;
}

static void pmac_ide_writew (void *opaque,
                             hwaddr addr, uint32_t val)
{
    MACIOIDEState *d = opaque;

    addr = (addr & 0xFFF) >> 4;
    val = bswap16(val);
    if (addr == 0) {
        ide_data_writew(&d->bus, 0, val);
    }
}

static uint32_t pmac_ide_readw (void *opaque,hwaddr addr)
{
    uint16_t retval;
    MACIOIDEState *d = opaque;

    addr = (addr & 0xFFF) >> 4;
    if (addr == 0) {
        retval = ide_data_readw(&d->bus, 0);
    } else {
        retval = 0xFFFF;
    }
    retval = bswap16(retval);
    return retval;
}

static void pmac_ide_writel (void *opaque,
                             hwaddr addr, uint32_t val)
{
    MACIOIDEState *d = opaque;

    addr = (addr & 0xFFF) >> 4;
    val = bswap32(val);
    if (addr == 0) {
        ide_data_writel(&d->bus, 0, val);
    }
}

static uint32_t pmac_ide_readl (void *opaque,hwaddr addr)
{
    uint32_t retval;
    MACIOIDEState *d = opaque;

    addr = (addr & 0xFFF) >> 4;
    if (addr == 0) {
        retval = ide_data_readl(&d->bus, 0);
    } else {
        retval = 0xFFFFFFFF;
    }
    retval = bswap32(retval);
    return retval;
}

static const MemoryRegionOps pmac_ide_ops = {
    .old_mmio = {
        .write = {
            pmac_ide_writeb,
            pmac_ide_writew,
            pmac_ide_writel,
        },
        .read = {
            pmac_ide_readb,
            pmac_ide_readw,
            pmac_ide_readl,
        },
    },
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static const VMStateDescription vmstate_pmac = {
    .name = "ide",
    .version_id = 3,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .fields      = (VMStateField []) {
        VMSTATE_IDE_BUS(bus, MACIOIDEState),
        VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
        VMSTATE_END_OF_LIST()
    }
};

static void macio_ide_reset(DeviceState *dev)
{
    MACIOIDEState *d = MACIO_IDE(dev);

    ide_bus_reset(&d->bus);
}

static void macio_ide_realizefn(DeviceState *dev, Error **errp)
{
    MACIOIDEState *s = MACIO_IDE(dev);

    ide_init2(&s->bus, s->irq);
}

static void macio_ide_initfn(Object *obj)
{
    SysBusDevice *d = SYS_BUS_DEVICE(obj);
    MACIOIDEState *s = MACIO_IDE(obj);

    ide_bus_new(&s->bus, DEVICE(obj), 0, 2);
    memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000);
    sysbus_init_mmio(d, &s->mem);
    sysbus_init_irq(d, &s->irq);
    sysbus_init_irq(d, &s->dma_irq);
}

static void macio_ide_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->realize = macio_ide_realizefn;
    dc->reset = macio_ide_reset;
    dc->vmsd = &vmstate_pmac;
}

static const TypeInfo macio_ide_type_info = {
    .name = TYPE_MACIO_IDE,
    .parent = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(MACIOIDEState),
    .instance_init = macio_ide_initfn,
    .class_init = macio_ide_class_init,
};

static void macio_ide_register_types(void)
{
    type_register_static(&macio_ide_type_info);
}

/* hd_table must contain 2 block drivers */
void macio_ide_init_drives(MACIOIDEState *s, DriveInfo **hd_table)
{
    int i;

    for (i = 0; i < 2; i++) {
        if (hd_table[i]) {
            ide_create_drive(&s->bus, i, hd_table[i]);
        }
    }
}

void macio_ide_register_dma(MACIOIDEState *s, void *dbdma, int channel)
{
    DBDMA_register_channel(dbdma, channel, s->dma_irq,
                           pmac_ide_transfer, pmac_ide_flush, s);
}

type_init(macio_ide_register_types)
Commit	Line	Data
b8842209 GH	1	/*
	2	* QEMU IDE Emulation: MacIO support.
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	* Copyright (c) 2006 Openedhand Ltd.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
baec1910 AF	25	#include "hw/hw.h"
baec1910 AF	26	#include "hw/ppc/mac.h"
0d09e41a	27	#include "hw/ppc/mac_dbdma.h"
737e150e	28	#include "block/block.h"
9c17d615	29	#include "sysemu/dma.h"
59f2a787 GH	30
59f2a787 GH	31	#include <hw/ide/internal.h>
b8842209 GH	32
	33	/***********************************************************/
	34	/* MacIO based PowerPC IDE */
	35
02c7c992 BS	36	#define MACIO_PAGE_SIZE 4096
02c7c992 BS	37
b8842209 GH	38	static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
	39	{
	40	DBDMA_io *io = opaque;
	41	MACIOIDEState *m = io->opaque;
	42	IDEState *s = idebus_active_if(&m->bus);
	43
	44	if (ret < 0) {
	45	m->aiocb = NULL;
	46	qemu_sglist_destroy(&s->sg);
	47	ide_atapi_io_error(s, ret);
a597e79c	48	goto done;
b8842209 GH	49	}
	50
	51	if (s->io_buffer_size > 0) {
	52	m->aiocb = NULL;
	53	qemu_sglist_destroy(&s->sg);
	54
	55	s->packet_transfer_size -= s->io_buffer_size;
	56
	57	s->io_buffer_index += s->io_buffer_size;
	58	s->lba += s->io_buffer_index >> 11;
	59	s->io_buffer_index &= 0x7ff;
	60	}
	61
	62	if (s->packet_transfer_size <= 0)
	63	ide_atapi_cmd_ok(s);
	64
	65	if (io->len == 0) {
a597e79c	66	goto done;
b8842209 GH	67	}
	68
	69	/* launch next transfer */
	70
	71	s->io_buffer_size = io->len;
	72
f487b677	73	qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,
df32fd1c	74	&address_space_memory);
b8842209 GH	75	qemu_sglist_add(&s->sg, io->addr, io->len);
	76	io->addr += io->len;
	77	io->len = 0;
	78
	79	m->aiocb = dma_bdrv_read(s->bs, &s->sg,
	80	(int64_t)(s->lba << 2) + (s->io_buffer_index >> 9),
	81	pmac_ide_atapi_transfer_cb, io);
a597e79c CH	82	return;
	83
	84	done:
	85	bdrv_acct_done(s->bs, &s->acct);
	86	io->dma_end(opaque);
b8842209 GH	87	}
	88
	89	static void pmac_ide_transfer_cb(void *opaque, int ret)
	90	{
	91	DBDMA_io *io = opaque;
	92	MACIOIDEState *m = io->opaque;
	93	IDEState *s = idebus_active_if(&m->bus);
	94	int n;
	95	int64_t sector_num;
	96
	97	if (ret < 0) {
	98	m->aiocb = NULL;
	99	qemu_sglist_destroy(&s->sg);
	100	ide_dma_error(s);
a597e79c	101	goto done;
b8842209 GH	102	}
	103
	104	sector_num = ide_get_sector(s);
	105	if (s->io_buffer_size > 0) {
	106	m->aiocb = NULL;
	107	qemu_sglist_destroy(&s->sg);
	108	n = (s->io_buffer_size + 0x1ff) >> 9;
	109	sector_num += n;
	110	ide_set_sector(s, sector_num);
	111	s->nsector -= n;
	112	}
	113
	114	/* end of transfer ? */
	115	if (s->nsector == 0) {
	116	s->status = READY_STAT \| SEEK_STAT;
9cdd03a7	117	ide_set_irq(s->bus);
b8842209 GH	118	}
	119
	120	/* end of DMA ? */
b8842209	121	if (io->len == 0) {
a597e79c	122	goto done;
b8842209 GH	123	}
	124
	125	/* launch next transfer */
	126
	127	s->io_buffer_index = 0;
	128	s->io_buffer_size = io->len;
	129
f487b677	130	qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,
df32fd1c	131	&address_space_memory);
b8842209 GH	132	qemu_sglist_add(&s->sg, io->addr, io->len);
	133	io->addr += io->len;
	134	io->len = 0;
	135
4e1e0051 CH	136	switch (s->dma_cmd) {
4e1e0051 CH	137	case IDE_DMA_READ:
b8842209 GH	138	m->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
b8842209 GH	139	pmac_ide_transfer_cb, io);
4e1e0051 CH	140	break;
4e1e0051 CH	141	case IDE_DMA_WRITE:
b8842209 GH	142	m->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
b8842209 GH	143	pmac_ide_transfer_cb, io);
4e1e0051	144	break;
d353fb72 CH	145	case IDE_DMA_TRIM:
d353fb72 CH	146	m->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num,
b9b5df6f	147	ide_issue_trim, pmac_ide_transfer_cb, io,
43cf8ae6	148	DMA_DIRECTION_TO_DEVICE);
d353fb72	149	break;
4e1e0051	150	}
a597e79c	151	return;
b9b2008b	152
a597e79c CH	153	done:
	154	if (s->dma_cmd == IDE_DMA_READ \|\| s->dma_cmd == IDE_DMA_WRITE) {
	155	bdrv_acct_done(s->bs, &s->acct);
	156	}
	157	io->dma_end(io);
b8842209 GH	158	}
	159
	160	static void pmac_ide_transfer(DBDMA_io *io)
	161	{
	162	MACIOIDEState *m = io->opaque;
	163	IDEState *s = idebus_active_if(&m->bus);
	164
	165	s->io_buffer_size = 0;
cd8722bb	166	if (s->drive_kind == IDE_CD) {
a597e79c	167	bdrv_acct_start(s->bs, &s->acct, io->len, BDRV_ACCT_READ);
b8842209 GH	168	pmac_ide_atapi_transfer_cb(io, 0);
	169	return;
	170	}
	171
a597e79c CH	172	switch (s->dma_cmd) {
	173	case IDE_DMA_READ:
	174	bdrv_acct_start(s->bs, &s->acct, io->len, BDRV_ACCT_READ);
	175	break;
	176	case IDE_DMA_WRITE:
	177	bdrv_acct_start(s->bs, &s->acct, io->len, BDRV_ACCT_WRITE);
	178	break;
	179	default:
	180	break;
	181	}
	182
b8842209 GH	183	pmac_ide_transfer_cb(io, 0);
	184	}
	185
	186	static void pmac_ide_flush(DBDMA_io *io)
	187	{
	188	MACIOIDEState *m = io->opaque;
	189
922453bc SH	190	if (m->aiocb) {
	191	bdrv_drain_all();
	192	}
b8842209 GH	193	}
	194
	195	/* PowerMac IDE memory IO */
	196	static void pmac_ide_writeb (void *opaque,
a8170e5e	197	hwaddr addr, uint32_t val)
b8842209 GH	198	{
	199	MACIOIDEState *d = opaque;
	200
	201	addr = (addr & 0xFFF) >> 4;
	202	switch (addr) {
	203	case 1 ... 7:
	204	ide_ioport_write(&d->bus, addr, val);
	205	break;
	206	case 8:
	207	case 22:
	208	ide_cmd_write(&d->bus, 0, val);
	209	break;
	210	default:
	211	break;
	212	}
	213	}
	214
a8170e5e	215	static uint32_t pmac_ide_readb (void *opaque,hwaddr addr)
b8842209 GH	216	{
	217	uint8_t retval;
	218	MACIOIDEState *d = opaque;
	219
	220	addr = (addr & 0xFFF) >> 4;
	221	switch (addr) {
	222	case 1 ... 7:
	223	retval = ide_ioport_read(&d->bus, addr);
	224	break;
	225	case 8:
	226	case 22:
	227	retval = ide_status_read(&d->bus, 0);
	228	break;
	229	default:
	230	retval = 0xFF;
	231	break;
	232	}
	233	return retval;
	234	}
	235
	236	static void pmac_ide_writew (void *opaque,
a8170e5e	237	hwaddr addr, uint32_t val)
b8842209 GH	238	{
	239	MACIOIDEState *d = opaque;
	240
	241	addr = (addr & 0xFFF) >> 4;
b8842209	242	val = bswap16(val);
b8842209 GH	243	if (addr == 0) {
	244	ide_data_writew(&d->bus, 0, val);
	245	}
	246	}
	247
a8170e5e	248	static uint32_t pmac_ide_readw (void *opaque,hwaddr addr)
b8842209 GH	249	{
	250	uint16_t retval;
	251	MACIOIDEState *d = opaque;
	252
	253	addr = (addr & 0xFFF) >> 4;
	254	if (addr == 0) {
	255	retval = ide_data_readw(&d->bus, 0);
	256	} else {
	257	retval = 0xFFFF;
	258	}
b8842209	259	retval = bswap16(retval);
b8842209 GH	260	return retval;
	261	}
	262
	263	static void pmac_ide_writel (void *opaque,
a8170e5e	264	hwaddr addr, uint32_t val)
b8842209 GH	265	{
	266	MACIOIDEState *d = opaque;
	267
	268	addr = (addr & 0xFFF) >> 4;
b8842209	269	val = bswap32(val);
b8842209 GH	270	if (addr == 0) {
	271	ide_data_writel(&d->bus, 0, val);
	272	}
	273	}
	274
a8170e5e	275	static uint32_t pmac_ide_readl (void *opaque,hwaddr addr)
b8842209 GH	276	{
	277	uint32_t retval;
	278	MACIOIDEState *d = opaque;
	279
	280	addr = (addr & 0xFFF) >> 4;
	281	if (addr == 0) {
	282	retval = ide_data_readl(&d->bus, 0);
	283	} else {
	284	retval = 0xFFFFFFFF;
	285	}
b8842209	286	retval = bswap32(retval);
b8842209 GH	287	return retval;
	288	}
	289
a348f108	290	static const MemoryRegionOps pmac_ide_ops = {
23c5e4ca AK	291	.old_mmio = {
	292	.write = {
	293	pmac_ide_writeb,
	294	pmac_ide_writew,
	295	pmac_ide_writel,
	296	},
	297	.read = {
	298	pmac_ide_readb,
	299	pmac_ide_readw,
	300	pmac_ide_readl,
	301	},
	302	},
	303	.endianness = DEVICE_NATIVE_ENDIAN,
b8842209 GH	304	};
b8842209 GH	305
44bfa332 JQ	306	static const VMStateDescription vmstate_pmac = {
	307	.name = "ide",
	308	.version_id = 3,
	309	.minimum_version_id = 0,
	310	.minimum_version_id_old = 0,
	311	.fields = (VMStateField []) {
	312	VMSTATE_IDE_BUS(bus, MACIOIDEState),
	313	VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
	314	VMSTATE_END_OF_LIST()
b8842209	315	}
44bfa332	316	};
b8842209	317
07a7484e	318	static void macio_ide_reset(DeviceState *dev)
b8842209	319	{
07a7484e	320	MACIOIDEState *d = MACIO_IDE(dev);
b8842209	321
4a643563	322	ide_bus_reset(&d->bus);
b8842209 GH	323	}
b8842209 GH	324
07a7484e	325	static void macio_ide_realizefn(DeviceState dev, Error *errp)
b8842209	326	{
07a7484e AF	327	MACIOIDEState *s = MACIO_IDE(dev);
	328
	329	ide_init2(&s->bus, s->irq);
	330	}
	331
	332	static void macio_ide_initfn(Object *obj)
	333	{
	334	SysBusDevice *d = SYS_BUS_DEVICE(obj);
	335	MACIOIDEState *s = MACIO_IDE(obj);
	336
0ee20e66	337	ide_bus_new(&s->bus, DEVICE(obj), 0, 2);
1437c94b	338	memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000);
07a7484e AF	339	sysbus_init_mmio(d, &s->mem);
	340	sysbus_init_irq(d, &s->irq);
	341	sysbus_init_irq(d, &s->dma_irq);
	342	}
	343
	344	static void macio_ide_class_init(ObjectClass oc, void data)
	345	{
	346	DeviceClass *dc = DEVICE_CLASS(oc);
	347
	348	dc->realize = macio_ide_realizefn;
	349	dc->reset = macio_ide_reset;
	350	dc->vmsd = &vmstate_pmac;
	351	}
b8842209	352
07a7484e AF	353	static const TypeInfo macio_ide_type_info = {
	354	.name = TYPE_MACIO_IDE,
	355	.parent = TYPE_SYS_BUS_DEVICE,
	356	.instance_size = sizeof(MACIOIDEState),
	357	.instance_init = macio_ide_initfn,
	358	.class_init = macio_ide_class_init,
	359	};
b8842209	360
07a7484e AF	361	static void macio_ide_register_types(void)
	362	{
	363	type_register_static(&macio_ide_type_info);
	364	}
b8842209	365
14eefd0e	366	/* hd_table must contain 2 block drivers */
07a7484e AF	367	void macio_ide_init_drives(MACIOIDEState s, DriveInfo *hd_table)
	368	{
	369	int i;
b8842209	370
07a7484e AF	371	for (i = 0; i < 2; i++) {
	372	if (hd_table[i]) {
	373	ide_create_drive(&s->bus, i, hd_table[i]);
	374	}
	375	}
b8842209	376	}
07a7484e AF	377
	378	void macio_ide_register_dma(MACIOIDEState s, void dbdma, int channel)
	379	{
	380	DBDMA_register_channel(dbdma, channel, s->dma_irq,
	381	pmac_ide_transfer, pmac_ide_flush, s);
	382	}
	383
	384	type_init(macio_ide_register_types)