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9ee6e8bb PB |
1 | /* |
2 | * Arm PrimeCell PL022 Synchronous Serial Port | |
3 | * | |
4 | * Copyright (c) 2007 CodeSourcery. | |
5 | * Written by Paul Brook | |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the GPL. |
9ee6e8bb PB |
8 | */ |
9 | ||
5493e33f PB |
10 | #include "sysbus.h" |
11 | #include "ssi.h" | |
87ecb68b | 12 | #include "primecell.h" |
9ee6e8bb PB |
13 | |
14 | //#define DEBUG_PL022 1 | |
15 | ||
16 | #ifdef DEBUG_PL022 | |
001faf32 BS |
17 | #define DPRINTF(fmt, ...) \ |
18 | do { printf("pl022: " fmt , ## __VA_ARGS__); } while (0) | |
19 | #define BADF(fmt, ...) \ | |
20 | do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__); exit(1);} while (0) | |
9ee6e8bb | 21 | #else |
001faf32 BS |
22 | #define DPRINTF(fmt, ...) do {} while(0) |
23 | #define BADF(fmt, ...) \ | |
24 | do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__);} while (0) | |
9ee6e8bb PB |
25 | #endif |
26 | ||
27 | #define PL022_CR1_LBM 0x01 | |
28 | #define PL022_CR1_SSE 0x02 | |
29 | #define PL022_CR1_MS 0x04 | |
30 | #define PL022_CR1_SDO 0x08 | |
31 | ||
32 | #define PL022_SR_TFE 0x01 | |
33 | #define PL022_SR_TNF 0x02 | |
34 | #define PL022_SR_RNE 0x04 | |
35 | #define PL022_SR_RFF 0x08 | |
36 | #define PL022_SR_BSY 0x10 | |
37 | ||
38 | #define PL022_INT_ROR 0x01 | |
39 | #define PL022_INT_RT 0x04 | |
40 | #define PL022_INT_RX 0x04 | |
41 | #define PL022_INT_TX 0x08 | |
42 | ||
43 | typedef struct { | |
5493e33f | 44 | SysBusDevice busdev; |
02a59c37 | 45 | MemoryRegion iomem; |
9ee6e8bb PB |
46 | uint32_t cr0; |
47 | uint32_t cr1; | |
48 | uint32_t bitmask; | |
49 | uint32_t sr; | |
50 | uint32_t cpsr; | |
51 | uint32_t is; | |
52 | uint32_t im; | |
53 | /* The FIFO head points to the next empty entry. */ | |
54 | int tx_fifo_head; | |
55 | int rx_fifo_head; | |
56 | int tx_fifo_len; | |
57 | int rx_fifo_len; | |
58 | uint16_t tx_fifo[8]; | |
59 | uint16_t rx_fifo[8]; | |
60 | qemu_irq irq; | |
5493e33f | 61 | SSIBus *ssi; |
9ee6e8bb PB |
62 | } pl022_state; |
63 | ||
64 | static const unsigned char pl022_id[8] = | |
65 | { 0x22, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; | |
66 | ||
67 | static void pl022_update(pl022_state *s) | |
68 | { | |
69 | s->sr = 0; | |
70 | if (s->tx_fifo_len == 0) | |
71 | s->sr |= PL022_SR_TFE; | |
72 | if (s->tx_fifo_len != 8) | |
73 | s->sr |= PL022_SR_TNF; | |
74 | if (s->rx_fifo_len != 0) | |
75 | s->sr |= PL022_SR_RNE; | |
76 | if (s->rx_fifo_len == 8) | |
77 | s->sr |= PL022_SR_RFF; | |
78 | if (s->tx_fifo_len) | |
79 | s->sr |= PL022_SR_BSY; | |
80 | s->is = 0; | |
81 | if (s->rx_fifo_len >= 4) | |
82 | s->is |= PL022_INT_RX; | |
83 | if (s->tx_fifo_len <= 4) | |
84 | s->is |= PL022_INT_TX; | |
85 | ||
86 | qemu_set_irq(s->irq, (s->is & s->im) != 0); | |
87 | } | |
88 | ||
89 | static void pl022_xfer(pl022_state *s) | |
90 | { | |
91 | int i; | |
92 | int o; | |
93 | int val; | |
94 | ||
95 | if ((s->cr1 & PL022_CR1_SSE) == 0) { | |
96 | pl022_update(s); | |
97 | DPRINTF("Disabled\n"); | |
98 | return; | |
99 | } | |
100 | ||
101 | DPRINTF("Maybe xfer %d/%d\n", s->tx_fifo_len, s->rx_fifo_len); | |
102 | i = (s->tx_fifo_head - s->tx_fifo_len) & 7; | |
103 | o = s->rx_fifo_head; | |
104 | /* ??? We do not emulate the line speed. | |
105 | This may break some applications. The are two problematic cases: | |
106 | (a) A driver feeds data into the TX FIFO until it is full, | |
107 | and only then drains the RX FIFO. On real hardware the CPU can | |
108 | feed data fast enough that the RX fifo never gets chance to overflow. | |
109 | (b) A driver transmits data, deliberately allowing the RX FIFO to | |
110 | overflow because it ignores the RX data anyway. | |
111 | ||
112 | We choose to support (a) by stalling the transmit engine if it would | |
113 | cause the RX FIFO to overflow. In practice much transmit-only code | |
114 | falls into (a) because it flushes the RX FIFO to determine when | |
115 | the transfer has completed. */ | |
116 | while (s->tx_fifo_len && s->rx_fifo_len < 8) { | |
117 | DPRINTF("xfer\n"); | |
118 | val = s->tx_fifo[i]; | |
119 | if (s->cr1 & PL022_CR1_LBM) { | |
120 | /* Loopback mode. */ | |
9ee6e8bb | 121 | } else { |
5493e33f | 122 | val = ssi_transfer(s->ssi, val); |
9ee6e8bb PB |
123 | } |
124 | s->rx_fifo[o] = val & s->bitmask; | |
125 | i = (i + 1) & 7; | |
126 | o = (o + 1) & 7; | |
127 | s->tx_fifo_len--; | |
128 | s->rx_fifo_len++; | |
129 | } | |
130 | s->rx_fifo_head = o; | |
131 | pl022_update(s); | |
132 | } | |
133 | ||
02a59c37 AK |
134 | static uint64_t pl022_read(void *opaque, target_phys_addr_t offset, |
135 | unsigned size) | |
9ee6e8bb PB |
136 | { |
137 | pl022_state *s = (pl022_state *)opaque; | |
138 | int val; | |
139 | ||
9ee6e8bb PB |
140 | if (offset >= 0xfe0 && offset < 0x1000) { |
141 | return pl022_id[(offset - 0xfe0) >> 2]; | |
142 | } | |
143 | switch (offset) { | |
144 | case 0x00: /* CR0 */ | |
145 | return s->cr0; | |
146 | case 0x04: /* CR1 */ | |
147 | return s->cr1; | |
148 | case 0x08: /* DR */ | |
149 | if (s->rx_fifo_len) { | |
150 | val = s->rx_fifo[(s->rx_fifo_head - s->rx_fifo_len) & 7]; | |
151 | DPRINTF("RX %02x\n", val); | |
152 | s->rx_fifo_len--; | |
153 | pl022_xfer(s); | |
154 | } else { | |
155 | val = 0; | |
156 | } | |
157 | return val; | |
158 | case 0x0c: /* SR */ | |
159 | return s->sr; | |
160 | case 0x10: /* CPSR */ | |
161 | return s->cpsr; | |
162 | case 0x14: /* IMSC */ | |
163 | return s->im; | |
164 | case 0x18: /* RIS */ | |
165 | return s->is; | |
166 | case 0x1c: /* MIS */ | |
167 | return s->im & s->is; | |
168 | case 0x20: /* DMACR */ | |
169 | /* Not implemented. */ | |
170 | return 0; | |
171 | default: | |
2ac71179 | 172 | hw_error("pl022_read: Bad offset %x\n", (int)offset); |
9ee6e8bb PB |
173 | return 0; |
174 | } | |
175 | } | |
176 | ||
c227f099 | 177 | static void pl022_write(void *opaque, target_phys_addr_t offset, |
02a59c37 | 178 | uint64_t value, unsigned size) |
9ee6e8bb PB |
179 | { |
180 | pl022_state *s = (pl022_state *)opaque; | |
181 | ||
9ee6e8bb PB |
182 | switch (offset) { |
183 | case 0x00: /* CR0 */ | |
184 | s->cr0 = value; | |
185 | /* Clock rate and format are ignored. */ | |
186 | s->bitmask = (1 << ((value & 15) + 1)) - 1; | |
187 | break; | |
188 | case 0x04: /* CR1 */ | |
189 | s->cr1 = value; | |
190 | if ((s->cr1 & (PL022_CR1_MS | PL022_CR1_SSE)) | |
191 | == (PL022_CR1_MS | PL022_CR1_SSE)) { | |
192 | BADF("SPI slave mode not implemented\n"); | |
193 | } | |
194 | pl022_xfer(s); | |
195 | break; | |
196 | case 0x08: /* DR */ | |
197 | if (s->tx_fifo_len < 8) { | |
02a59c37 | 198 | DPRINTF("TX %02x\n", (unsigned)value); |
9ee6e8bb PB |
199 | s->tx_fifo[s->tx_fifo_head] = value & s->bitmask; |
200 | s->tx_fifo_head = (s->tx_fifo_head + 1) & 7; | |
201 | s->tx_fifo_len++; | |
202 | pl022_xfer(s); | |
203 | } | |
204 | break; | |
205 | case 0x10: /* CPSR */ | |
206 | /* Prescaler. Ignored. */ | |
207 | s->cpsr = value & 0xff; | |
208 | break; | |
209 | case 0x14: /* IMSC */ | |
210 | s->im = value; | |
211 | pl022_update(s); | |
212 | break; | |
213 | case 0x20: /* DMACR */ | |
2ac71179 PB |
214 | if (value) { |
215 | hw_error("pl022: DMA not implemented\n"); | |
216 | } | |
9ee6e8bb PB |
217 | break; |
218 | default: | |
2ac71179 | 219 | hw_error("pl022_write: Bad offset %x\n", (int)offset); |
9ee6e8bb PB |
220 | } |
221 | } | |
222 | ||
223 | static void pl022_reset(pl022_state *s) | |
224 | { | |
225 | s->rx_fifo_len = 0; | |
226 | s->tx_fifo_len = 0; | |
227 | s->im = 0; | |
228 | s->is = PL022_INT_TX; | |
229 | s->sr = PL022_SR_TFE | PL022_SR_TNF; | |
230 | } | |
231 | ||
02a59c37 AK |
232 | static const MemoryRegionOps pl022_ops = { |
233 | .read = pl022_read, | |
234 | .write = pl022_write, | |
235 | .endianness = DEVICE_NATIVE_ENDIAN, | |
9ee6e8bb PB |
236 | }; |
237 | ||
075790c2 JQ |
238 | static const VMStateDescription vmstate_pl022 = { |
239 | .name = "pl022_ssp", | |
240 | .version_id = 1, | |
241 | .minimum_version_id = 1, | |
242 | .minimum_version_id_old = 1, | |
243 | .fields = (VMStateField[]) { | |
244 | VMSTATE_UINT32(cr0, pl022_state), | |
245 | VMSTATE_UINT32(cr1, pl022_state), | |
246 | VMSTATE_UINT32(bitmask, pl022_state), | |
247 | VMSTATE_UINT32(sr, pl022_state), | |
248 | VMSTATE_UINT32(cpsr, pl022_state), | |
249 | VMSTATE_UINT32(is, pl022_state), | |
250 | VMSTATE_UINT32(im, pl022_state), | |
251 | VMSTATE_INT32(tx_fifo_head, pl022_state), | |
252 | VMSTATE_INT32(rx_fifo_head, pl022_state), | |
253 | VMSTATE_INT32(tx_fifo_len, pl022_state), | |
254 | VMSTATE_INT32(rx_fifo_len, pl022_state), | |
255 | VMSTATE_UINT16(tx_fifo[0], pl022_state), | |
256 | VMSTATE_UINT16(rx_fifo[0], pl022_state), | |
257 | VMSTATE_UINT16(tx_fifo[1], pl022_state), | |
258 | VMSTATE_UINT16(rx_fifo[1], pl022_state), | |
259 | VMSTATE_UINT16(tx_fifo[2], pl022_state), | |
260 | VMSTATE_UINT16(rx_fifo[2], pl022_state), | |
261 | VMSTATE_UINT16(tx_fifo[3], pl022_state), | |
262 | VMSTATE_UINT16(rx_fifo[3], pl022_state), | |
263 | VMSTATE_UINT16(tx_fifo[4], pl022_state), | |
264 | VMSTATE_UINT16(rx_fifo[4], pl022_state), | |
265 | VMSTATE_UINT16(tx_fifo[5], pl022_state), | |
266 | VMSTATE_UINT16(rx_fifo[5], pl022_state), | |
267 | VMSTATE_UINT16(tx_fifo[6], pl022_state), | |
268 | VMSTATE_UINT16(rx_fifo[6], pl022_state), | |
269 | VMSTATE_UINT16(tx_fifo[7], pl022_state), | |
270 | VMSTATE_UINT16(rx_fifo[7], pl022_state), | |
271 | VMSTATE_END_OF_LIST() | |
23e39294 | 272 | } |
075790c2 | 273 | }; |
23e39294 | 274 | |
81a322d4 | 275 | static int pl022_init(SysBusDevice *dev) |
9ee6e8bb | 276 | { |
5493e33f | 277 | pl022_state *s = FROM_SYSBUS(pl022_state, dev); |
9ee6e8bb | 278 | |
02a59c37 | 279 | memory_region_init_io(&s->iomem, &pl022_ops, s, "pl022", 0x1000); |
750ecd44 | 280 | sysbus_init_mmio(dev, &s->iomem); |
5493e33f | 281 | sysbus_init_irq(dev, &s->irq); |
02e2da45 | 282 | s->ssi = ssi_create_bus(&dev->qdev, "ssi"); |
9ee6e8bb | 283 | pl022_reset(s); |
075790c2 | 284 | vmstate_register(&dev->qdev, -1, &vmstate_pl022, s); |
81a322d4 | 285 | return 0; |
9ee6e8bb | 286 | } |
5493e33f PB |
287 | |
288 | static void pl022_register_devices(void) | |
289 | { | |
290 | sysbus_register_dev("pl022", sizeof(pl022_state), pl022_init); | |
291 | } | |
292 | ||
293 | device_init(pl022_register_devices) |