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f8da88d7 SG |
1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* | |
3 | * LoongArch translation routines. | |
4 | * | |
5 | * Copyright (c) 2021 Loongson Technology Corporation Limited | |
6 | */ | |
7 | ||
8 | #ifndef TARGET_LOONGARCH_TRANSLATE_H | |
9 | #define TARGET_LOONGARCH_TRANSLATE_H | |
10 | ||
11 | #include "exec/translator.h" | |
12 | ||
143d6785 SG |
13 | #define TRANS(NAME, FUNC, ...) \ |
14 | static bool trans_##NAME(DisasContext *ctx, arg_##NAME * a) \ | |
15 | { return FUNC(ctx, a, __VA_ARGS__); } | |
16 | ||
17 | /* | |
18 | * If an operation is being performed on less than TARGET_LONG_BITS, | |
19 | * it may require the inputs to be sign- or zero-extended; which will | |
20 | * depend on the exact operation being performed. | |
21 | */ | |
22 | typedef enum { | |
23 | EXT_NONE, | |
24 | EXT_SIGN, | |
25 | EXT_ZERO, | |
26 | } DisasExtend; | |
27 | ||
f8da88d7 SG |
28 | typedef struct DisasContext { |
29 | DisasContextBase base; | |
30 | target_ulong page_start; | |
31 | uint32_t opcode; | |
32 | int mem_idx; | |
143d6785 SG |
33 | TCGv zero; |
34 | /* Space for 3 operands plus 1 extra for address computation. */ | |
35 | TCGv temp[4]; | |
36 | uint8_t ntemp; | |
f8da88d7 SG |
37 | } DisasContext; |
38 | ||
39 | void generate_exception(DisasContext *ctx, int excp); | |
40 | ||
41 | extern TCGv cpu_gpr[32], cpu_pc; | |
42 | extern TCGv_i32 cpu_fscr0; | |
43 | extern TCGv_i64 cpu_fpr[32]; | |
44 | ||
45 | #endif |