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7e7c5e4c
AZ		 1/*
2 * TI TWL92230C energy-management companion device for the OMAP24xx.
3 * Aka. Menelaus (N4200 MENELAUS1_V2.2)
4 *
5 * Copyright (C) 2008 Nokia Corporation
6 * Written by Andrzej Zaborowski <[email protected]>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 or
11 * (at your option) version 3 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
fad6cb1a
AJ		 18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
7e7c5e4c
AZ		 21 */
22
23#include "hw.h"
24#include "qemu-timer.h"
25#include "i2c.h"
26#include "sysemu.h"
27#include "console.h"
28
29#define VERBOSE 1
30
bc24a225 31typedef struct {
7e7c5e4c 32 i2c_slave i2c;
7e7c5e4c
AZ		 33
34 int firstbyte;
35 uint8_t reg;
36
37 uint8_t vcore[5];
38 uint8_t dcdc[3];
39 uint8_t ldo[8];
40 uint8_t sleep[2];
41 uint8_t osc;
42 uint8_t detect;
43 uint16_t mask;
44 uint16_t status;
45 uint8_t dir;
46 uint8_t inputs;
47 uint8_t outputs;
48 uint8_t bbsms;
49 uint8_t pull[4];
50 uint8_t mmc_ctrl[3];
51 uint8_t mmc_debounce;
52 struct {
53 uint8_t ctrl;
54 uint16_t comp;
b0f74c87 55 QEMUTimer *hz_tm;
7e7c5e4c
AZ		 56 int64_t next;
57 struct tm tm;
58 struct tm new;
59 struct tm alm;
aec454d2
AZ		 60 int sec_offset;
61 int alm_sec;
62 int next_comp;
7e7c5e4c 63 } rtc;
d3356811 64 qemu_irq out[4];
7e7c5e4c
AZ		 65 qemu_irq *in;
66 int pwrbtn_state;
67 qemu_irq pwrbtn;
bc24a225 68} MenelausState;
7e7c5e4c 69
bc24a225 70static inline void menelaus_update(MenelausState *s)
7e7c5e4c 71{
d3356811 72 qemu_set_irq(s->out[3], s->status & ~s->mask);
7e7c5e4c
AZ		 73}
74
bc24a225 75static inline void menelaus_rtc_start(MenelausState *s)
7e7c5e4c
AZ		 76{
77 s->rtc.next =+ qemu_get_clock(rt_clock);
b0f74c87 78 qemu_mod_timer(s->rtc.hz_tm, s->rtc.next);
7e7c5e4c
AZ		 79}
80
bc24a225 81static inline void menelaus_rtc_stop(MenelausState *s)
7e7c5e4c 82{
b0f74c87 83 qemu_del_timer(s->rtc.hz_tm);
7e7c5e4c
AZ		 84 s->rtc.next =- qemu_get_clock(rt_clock);
85 if (s->rtc.next < 1)
86 s->rtc.next = 1;
87}
88
bc24a225 89static void menelaus_rtc_update(MenelausState *s)
7e7c5e4c 90{
aec454d2 91 qemu_get_timedate(&s->rtc.tm, s->rtc.sec_offset);
7e7c5e4c
AZ		 92}
93
bc24a225 94static void menelaus_alm_update(MenelausState *s)
7e7c5e4c
AZ		 95{
96 if ((s->rtc.ctrl & 3) == 3)
aec454d2 97 s->rtc.alm_sec = qemu_timedate_diff(&s->rtc.alm) - s->rtc.sec_offset;
7e7c5e4c
AZ		 98}
99
100static void menelaus_rtc_hz(void *opaque)
101{
bc24a225 102 MenelausState *s = (MenelausState *) opaque;
7e7c5e4c 103
aec454d2
AZ		 104 s->rtc.next_comp --;
105 s->rtc.alm_sec --;
7e7c5e4c 106 s->rtc.next += 1000;
b0f74c87 107 qemu_mod_timer(s->rtc.hz_tm, s->rtc.next);
7e7c5e4c
AZ		 108 if ((s->rtc.ctrl >> 3) & 3) { /* EVERY */
109 menelaus_rtc_update(s);
110 if (((s->rtc.ctrl >> 3) & 3) == 1 && !s->rtc.tm.tm_sec)
111 s->status |= 1 << 8; /* RTCTMR */
112 else if (((s->rtc.ctrl >> 3) & 3) == 2 && !s->rtc.tm.tm_min)
113 s->status |= 1 << 8; /* RTCTMR */
114 else if (!s->rtc.tm.tm_hour)
115 s->status |= 1 << 8; /* RTCTMR */
116 } else
117 s->status |= 1 << 8; /* RTCTMR */
118 if ((s->rtc.ctrl >> 1) & 1) { /* RTC_AL_EN */
aec454d2 119 if (s->rtc.alm_sec == 0)
7e7c5e4c
AZ		 120 s->status |= 1 << 9; /* RTCALM */
121 /* TODO: wake-up */
122 }
aec454d2 123 if (s->rtc.next_comp <= 0) {
7e7c5e4c 124 s->rtc.next -= muldiv64((int16_t) s->rtc.comp, 1000, 0x8000);
aec454d2 125 s->rtc.next_comp = 3600;
7e7c5e4c
AZ		 126 }
127 menelaus_update(s);
128}
129
8fcd3692 130static void menelaus_reset(i2c_slave *i2c)
7e7c5e4c 131{
bc24a225 132 MenelausState *s = (MenelausState *) i2c;
7e7c5e4c
AZ		 133 s->reg = 0x00;
134
135 s->vcore[0] = 0x0c; /* XXX: X-loader needs 0x8c? check! */
136 s->vcore[1] = 0x05;
137 s->vcore[2] = 0x02;
138 s->vcore[3] = 0x0c;
139 s->vcore[4] = 0x03;
140 s->dcdc[0] = 0x33; /* Depends on wiring */
141 s->dcdc[1] = 0x03;
142 s->dcdc[2] = 0x00;
143 s->ldo[0] = 0x95;
144 s->ldo[1] = 0x7e;
145 s->ldo[2] = 0x00;
146 s->ldo[3] = 0x00; /* Depends on wiring */
147 s->ldo[4] = 0x03; /* Depends on wiring */
148 s->ldo[5] = 0x00;
149 s->ldo[6] = 0x00;
150 s->ldo[7] = 0x00;
151 s->sleep[0] = 0x00;
152 s->sleep[1] = 0x00;
153 s->osc = 0x01;
154 s->detect = 0x09;
155 s->mask = 0x0fff;
156 s->status = 0;
157 s->dir = 0x07;
158 s->outputs = 0x00;
159 s->bbsms = 0x00;
160 s->pull[0] = 0x00;
161 s->pull[1] = 0x00;
162 s->pull[2] = 0x00;
163 s->pull[3] = 0x00;
164 s->mmc_ctrl[0] = 0x03;
165 s->mmc_ctrl[1] = 0xc0;
166 s->mmc_ctrl[2] = 0x00;
167 s->mmc_debounce = 0x05;
168
7e7c5e4c
AZ		 169 if (s->rtc.ctrl & 1)
170 menelaus_rtc_stop(s);
171 s->rtc.ctrl = 0x00;
172 s->rtc.comp = 0x0000;
173 s->rtc.next = 1000;
aec454d2
AZ		 174 s->rtc.sec_offset = 0;
175 s->rtc.next_comp = 1800;
176 s->rtc.alm_sec = 1800;
7e7c5e4c
AZ		 177 s->rtc.alm.tm_sec = 0x00;
178 s->rtc.alm.tm_min = 0x00;
179 s->rtc.alm.tm_hour = 0x00;
180 s->rtc.alm.tm_mday = 0x01;
181 s->rtc.alm.tm_mon = 0x00;
182 s->rtc.alm.tm_year = 2004;
183 menelaus_update(s);
184}
185
186static inline uint8_t to_bcd(int val)
187{
188 return ((val / 10) << 4) | (val % 10);
189}
190
191static inline int from_bcd(uint8_t val)
192{
193 return ((val >> 4) * 10) + (val & 0x0f);
194}
195
196static void menelaus_gpio_set(void *opaque, int line, int level)
197{
bc24a225 198 MenelausState *s = (MenelausState *) opaque;
7e7c5e4c
AZ		 199
200 /* No interrupt generated */
201 s->inputs &= ~(1 << line);
202 s->inputs |= level << line;
203}
204
205static void menelaus_pwrbtn_set(void *opaque, int line, int level)
206{
bc24a225 207 MenelausState *s = (MenelausState *) opaque;
7e7c5e4c
AZ		 208
209 if (!s->pwrbtn_state && level) {
210 s->status |= 1 << 11; /* PSHBTN */
211 menelaus_update(s);
212 }
213 s->pwrbtn_state = level;
214}
215
216#define MENELAUS_REV 0x01
217#define MENELAUS_VCORE_CTRL1 0x02
218#define MENELAUS_VCORE_CTRL2 0x03
219#define MENELAUS_VCORE_CTRL3 0x04
220#define MENELAUS_VCORE_CTRL4 0x05
221#define MENELAUS_VCORE_CTRL5 0x06
222#define MENELAUS_DCDC_CTRL1 0x07
223#define MENELAUS_DCDC_CTRL2 0x08
224#define MENELAUS_DCDC_CTRL3 0x09
225#define MENELAUS_LDO_CTRL1 0x0a
226#define MENELAUS_LDO_CTRL2 0x0b
227#define MENELAUS_LDO_CTRL3 0x0c
228#define MENELAUS_LDO_CTRL4 0x0d
229#define MENELAUS_LDO_CTRL5 0x0e
230#define MENELAUS_LDO_CTRL6 0x0f
231#define MENELAUS_LDO_CTRL7 0x10
232#define MENELAUS_LDO_CTRL8 0x11
233#define MENELAUS_SLEEP_CTRL1 0x12
234#define MENELAUS_SLEEP_CTRL2 0x13
235#define MENELAUS_DEVICE_OFF 0x14
236#define MENELAUS_OSC_CTRL 0x15
237#define MENELAUS_DETECT_CTRL 0x16
238#define MENELAUS_INT_MASK1 0x17
239#define MENELAUS_INT_MASK2 0x18
240#define MENELAUS_INT_STATUS1 0x19
241#define MENELAUS_INT_STATUS2 0x1a
242#define MENELAUS_INT_ACK1 0x1b
243#define MENELAUS_INT_ACK2 0x1c
244#define MENELAUS_GPIO_CTRL 0x1d
245#define MENELAUS_GPIO_IN 0x1e
246#define MENELAUS_GPIO_OUT 0x1f
247#define MENELAUS_BBSMS 0x20
248#define MENELAUS_RTC_CTRL 0x21
249#define MENELAUS_RTC_UPDATE 0x22
250#define MENELAUS_RTC_SEC 0x23
251#define MENELAUS_RTC_MIN 0x24
252#define MENELAUS_RTC_HR 0x25
253#define MENELAUS_RTC_DAY 0x26
254#define MENELAUS_RTC_MON 0x27
255#define MENELAUS_RTC_YR 0x28
256#define MENELAUS_RTC_WKDAY 0x29
257#define MENELAUS_RTC_AL_SEC 0x2a
258#define MENELAUS_RTC_AL_MIN 0x2b
259#define MENELAUS_RTC_AL_HR 0x2c
260#define MENELAUS_RTC_AL_DAY 0x2d
261#define MENELAUS_RTC_AL_MON 0x2e
262#define MENELAUS_RTC_AL_YR 0x2f
263#define MENELAUS_RTC_COMP_MSB 0x30
264#define MENELAUS_RTC_COMP_LSB 0x31
265#define MENELAUS_S1_PULL_EN 0x32
266#define MENELAUS_S1_PULL_DIR 0x33
267#define MENELAUS_S2_PULL_EN 0x34
268#define MENELAUS_S2_PULL_DIR 0x35
269#define MENELAUS_MCT_CTRL1 0x36
270#define MENELAUS_MCT_CTRL2 0x37
271#define MENELAUS_MCT_CTRL3 0x38
272#define MENELAUS_MCT_PIN_ST 0x39
273#define MENELAUS_DEBOUNCE1 0x3a
274
275static uint8_t menelaus_read(void *opaque, uint8_t addr)
276{
bc24a225 277 MenelausState *s = (MenelausState *) opaque;
7e7c5e4c
AZ		 278 int reg = 0;
279
280 switch (addr) {
281 case MENELAUS_REV:
282 return 0x22;
283
284 case MENELAUS_VCORE_CTRL5: reg ++;
285 case MENELAUS_VCORE_CTRL4: reg ++;
286 case MENELAUS_VCORE_CTRL3: reg ++;
287 case MENELAUS_VCORE_CTRL2: reg ++;
288 case MENELAUS_VCORE_CTRL1:
289 return s->vcore[reg];
290
291 case MENELAUS_DCDC_CTRL3: reg ++;
292 case MENELAUS_DCDC_CTRL2: reg ++;
293 case MENELAUS_DCDC_CTRL1:
294 return s->dcdc[reg];
295
296 case MENELAUS_LDO_CTRL8: reg ++;
297 case MENELAUS_LDO_CTRL7: reg ++;
298 case MENELAUS_LDO_CTRL6: reg ++;
299 case MENELAUS_LDO_CTRL5: reg ++;
300 case MENELAUS_LDO_CTRL4: reg ++;
301 case MENELAUS_LDO_CTRL3: reg ++;
302 case MENELAUS_LDO_CTRL2: reg ++;
303 case MENELAUS_LDO_CTRL1:
304 return s->ldo[reg];
305
306 case MENELAUS_SLEEP_CTRL2: reg ++;
307 case MENELAUS_SLEEP_CTRL1:
308 return s->sleep[reg];
309
310 case MENELAUS_DEVICE_OFF:
311 return 0;
312
313 case MENELAUS_OSC_CTRL:
314 return s->osc | (1 << 7); /* CLK32K_GOOD */
315
316 case MENELAUS_DETECT_CTRL:
317 return s->detect;
318
319 case MENELAUS_INT_MASK1:
320 return (s->mask >> 0) & 0xff;
321 case MENELAUS_INT_MASK2:
322 return (s->mask >> 8) & 0xff;
323
324 case MENELAUS_INT_STATUS1:
325 return (s->status >> 0) & 0xff;
326 case MENELAUS_INT_STATUS2:
327 return (s->status >> 8) & 0xff;
328
329 case MENELAUS_INT_ACK1:
330 case MENELAUS_INT_ACK2:
331 return 0;
332
333 case MENELAUS_GPIO_CTRL:
334 return s->dir;
335 case MENELAUS_GPIO_IN:
336 return s->inputs | (~s->dir & s->outputs);
337 case MENELAUS_GPIO_OUT:
338 return s->outputs;
339
340 case MENELAUS_BBSMS:
341 return s->bbsms;
342
343 case MENELAUS_RTC_CTRL:
344 return s->rtc.ctrl;
345 case MENELAUS_RTC_UPDATE:
346 return 0x00;
347 case MENELAUS_RTC_SEC:
348 menelaus_rtc_update(s);
349 return to_bcd(s->rtc.tm.tm_sec);
350 case MENELAUS_RTC_MIN:
351 menelaus_rtc_update(s);
352 return to_bcd(s->rtc.tm.tm_min);
353 case MENELAUS_RTC_HR:
354 menelaus_rtc_update(s);
355 if ((s->rtc.ctrl >> 2) & 1) /* MODE12_n24 */
356 return to_bcd((s->rtc.tm.tm_hour % 12) + 1) |
357 (!!(s->rtc.tm.tm_hour >= 12) << 7); /* PM_nAM */
358 else
359 return to_bcd(s->rtc.tm.tm_hour);
360 case MENELAUS_RTC_DAY:
361 menelaus_rtc_update(s);
362 return to_bcd(s->rtc.tm.tm_mday);
363 case MENELAUS_RTC_MON:
364 menelaus_rtc_update(s);
365 return to_bcd(s->rtc.tm.tm_mon + 1);
366 case MENELAUS_RTC_YR:
367 menelaus_rtc_update(s);
368 return to_bcd(s->rtc.tm.tm_year - 2000);
369 case MENELAUS_RTC_WKDAY:
370 menelaus_rtc_update(s);
371 return to_bcd(s->rtc.tm.tm_wday);
372 case MENELAUS_RTC_AL_SEC:
373 return to_bcd(s->rtc.alm.tm_sec);
374 case MENELAUS_RTC_AL_MIN:
375 return to_bcd(s->rtc.alm.tm_min);
376 case MENELAUS_RTC_AL_HR:
377 if ((s->rtc.ctrl >> 2) & 1) /* MODE12_n24 */
378 return to_bcd((s->rtc.alm.tm_hour % 12) + 1) |
379 (!!(s->rtc.alm.tm_hour >= 12) << 7);/* AL_PM_nAM */
380 else
381 return to_bcd(s->rtc.alm.tm_hour);
382 case MENELAUS_RTC_AL_DAY:
383 return to_bcd(s->rtc.alm.tm_mday);
384 case MENELAUS_RTC_AL_MON:
385 return to_bcd(s->rtc.alm.tm_mon + 1);
386 case MENELAUS_RTC_AL_YR:
387 return to_bcd(s->rtc.alm.tm_year - 2000);
388 case MENELAUS_RTC_COMP_MSB:
389 return (s->rtc.comp >> 8) & 0xff;
390 case MENELAUS_RTC_COMP_LSB:
391 return (s->rtc.comp >> 0) & 0xff;
392
393 case MENELAUS_S1_PULL_EN:
394 return s->pull[0];
395 case MENELAUS_S1_PULL_DIR:
396 return s->pull[1];
397 case MENELAUS_S2_PULL_EN:
398 return s->pull[2];
399 case MENELAUS_S2_PULL_DIR:
400 return s->pull[3];
401
402 case MENELAUS_MCT_CTRL3: reg ++;
403 case MENELAUS_MCT_CTRL2: reg ++;
404 case MENELAUS_MCT_CTRL1:
405 return s->mmc_ctrl[reg];
406 case MENELAUS_MCT_PIN_ST:
407 /* TODO: return the real Card Detect */
408 return 0;
409 case MENELAUS_DEBOUNCE1:
410 return s->mmc_debounce;
411
412 default:
413#ifdef VERBOSE
414 printf("%s: unknown register %02x\n", __FUNCTION__, addr);
415#endif
416 break;
417 }
418 return 0;
419}
420
421static void menelaus_write(void *opaque, uint8_t addr, uint8_t value)
422{
bc24a225 423 MenelausState *s = (MenelausState *) opaque;
7e7c5e4c
AZ		 424 int line;
425 int reg = 0;
426 struct tm tm;
427
428 switch (addr) {
429 case MENELAUS_VCORE_CTRL1:
430 s->vcore[0] = (value & 0xe) | MIN(value & 0x1f, 0x12);
431 break;
432 case MENELAUS_VCORE_CTRL2:
433 s->vcore[1] = value;
434 break;
435 case MENELAUS_VCORE_CTRL3:
436 s->vcore[2] = MIN(value & 0x1f, 0x12);
437 break;
438 case MENELAUS_VCORE_CTRL4:
439 s->vcore[3] = MIN(value & 0x1f, 0x12);
440 break;
441 case MENELAUS_VCORE_CTRL5:
442 s->vcore[4] = value & 3;
443 /* XXX
444 * auto set to 3 on M_Active, nRESWARM
445 * auto set to 0 on M_WaitOn, M_Backup
446 */
447 break;
448
449 case MENELAUS_DCDC_CTRL1:
450 s->dcdc[0] = value & 0x3f;
451 break;
452 case MENELAUS_DCDC_CTRL2:
453 s->dcdc[1] = value & 0x07;
454 /* XXX
455 * auto set to 3 on M_Active, nRESWARM
456 * auto set to 0 on M_WaitOn, M_Backup
457 */
458 break;
459 case MENELAUS_DCDC_CTRL3:
460 s->dcdc[2] = value & 0x07;
461 break;
462
463 case MENELAUS_LDO_CTRL1:
464 s->ldo[0] = value;
465 break;
466 case MENELAUS_LDO_CTRL2:
467 s->ldo[1] = value & 0x7f;
468 /* XXX
469 * auto set to 0x7e on M_WaitOn, M_Backup
470 */
471 break;
472 case MENELAUS_LDO_CTRL3:
473 s->ldo[2] = value & 3;
474 /* XXX
475 * auto set to 3 on M_Active, nRESWARM
476 * auto set to 0 on M_WaitOn, M_Backup
477 */
478 break;
479 case MENELAUS_LDO_CTRL4:
480 s->ldo[3] = value & 3;
481 /* XXX
482 * auto set to 3 on M_Active, nRESWARM
483 * auto set to 0 on M_WaitOn, M_Backup
484 */
485 break;
486 case MENELAUS_LDO_CTRL5:
487 s->ldo[4] = value & 3;
488 /* XXX
489 * auto set to 3 on M_Active, nRESWARM
490 * auto set to 0 on M_WaitOn, M_Backup
491 */
492 break;
493 case MENELAUS_LDO_CTRL6:
494 s->ldo[5] = value & 3;
495 break;
496 case MENELAUS_LDO_CTRL7:
497 s->ldo[6] = value & 3;
498 break;
499 case MENELAUS_LDO_CTRL8:
500 s->ldo[7] = value & 3;
501 break;
502
503 case MENELAUS_SLEEP_CTRL2: reg ++;
504 case MENELAUS_SLEEP_CTRL1:
505 s->sleep[reg] = value;
506 break;
507
508 case MENELAUS_DEVICE_OFF:
509 if (value & 1)
510 menelaus_reset(&s->i2c);
511 break;
512
513 case MENELAUS_OSC_CTRL:
514 s->osc = value & 7;
515 break;
516
517 case MENELAUS_DETECT_CTRL:
518 s->detect = value & 0x7f;
519 break;
520
521 case MENELAUS_INT_MASK1:
522 s->mask &= 0xf00;
523 s->mask |= value << 0;
524 menelaus_update(s);
525 break;
526 case MENELAUS_INT_MASK2:
527 s->mask &= 0x0ff;
528 s->mask |= value << 8;
529 menelaus_update(s);
530 break;
531
532 case MENELAUS_INT_ACK1:
533 s->status &= ~(((uint16_t) value) << 0);
534 menelaus_update(s);
535 break;
536 case MENELAUS_INT_ACK2:
537 s->status &= ~(((uint16_t) value) << 8);
538 menelaus_update(s);
539 break;
540
541 case MENELAUS_GPIO_CTRL:
d3356811
PB		 542 for (line = 0; line < 3; line ++) {
543 if (((s->dir ^ value) >> line) & 1) {
544 qemu_set_irq(s->out[line],
545 ((s->outputs & ~s->dir) >> line) & 1);
546 }
547 }
7e7c5e4c
AZ		 548 s->dir = value & 0x67;
549 break;
550 case MENELAUS_GPIO_OUT:
d3356811
PB		 551 for (line = 0; line < 3; line ++) {
552 if ((((s->outputs ^ value) & ~s->dir) >> line) & 1) {
553 qemu_set_irq(s->out[line], (s->outputs >> line) & 1);
554 }
555 }
7e7c5e4c
AZ		 556 s->outputs = value & 0x07;
557 break;
558
559 case MENELAUS_BBSMS:
560 s->bbsms = 0x0d;
561 break;
562
563 case MENELAUS_RTC_CTRL:
564 if ((s->rtc.ctrl ^ value) & 1) { /* RTC_EN */
565 if (value & 1)
566 menelaus_rtc_start(s);
567 else
568 menelaus_rtc_stop(s);
569 }
570 s->rtc.ctrl = value & 0x1f;
571 menelaus_alm_update(s);
572 break;
573 case MENELAUS_RTC_UPDATE:
574 menelaus_rtc_update(s);
575 memcpy(&tm, &s->rtc.tm, sizeof(tm));
576 switch (value & 0xf) {
577 case 0:
578 break;
579 case 1:
580 tm.tm_sec = s->rtc.new.tm_sec;
581 break;
582 case 2:
583 tm.tm_min = s->rtc.new.tm_min;
584 break;
585 case 3:
586 if (s->rtc.new.tm_hour > 23)
587 goto rtc_badness;
588 tm.tm_hour = s->rtc.new.tm_hour;
589 break;
590 case 4:
591 if (s->rtc.new.tm_mday < 1)
592 goto rtc_badness;
593 /* TODO check range */
594 tm.tm_mday = s->rtc.new.tm_mday;
595 break;
596 case 5:
597 if (s->rtc.new.tm_mon < 0 || s->rtc.new.tm_mon > 11)
598 goto rtc_badness;
599 tm.tm_mon = s->rtc.new.tm_mon;
600 break;
601 case 6:
602 tm.tm_year = s->rtc.new.tm_year;
603 break;
604 case 7:
605 /* TODO set .tm_mday instead */
606 tm.tm_wday = s->rtc.new.tm_wday;
607 break;
608 case 8:
609 if (s->rtc.new.tm_hour > 23)
610 goto rtc_badness;
611 if (s->rtc.new.tm_mday < 1)
612 goto rtc_badness;
613 if (s->rtc.new.tm_mon < 0 || s->rtc.new.tm_mon > 11)
614 goto rtc_badness;
615 tm.tm_sec = s->rtc.new.tm_sec;
616 tm.tm_min = s->rtc.new.tm_min;
617 tm.tm_hour = s->rtc.new.tm_hour;
618 tm.tm_mday = s->rtc.new.tm_mday;
619 tm.tm_mon = s->rtc.new.tm_mon;
620 tm.tm_year = s->rtc.new.tm_year;
621 break;
622 rtc_badness:
623 default:
624 fprintf(stderr, "%s: bad RTC_UPDATE value %02x\n",
625 __FUNCTION__, value);
626 s->status |= 1 << 10; /* RTCERR */
627 menelaus_update(s);
628 }
aec454d2 629 s->rtc.sec_offset = qemu_timedate_diff(&tm);
7e7c5e4c
AZ		 630 break;
631 case MENELAUS_RTC_SEC:
632 s->rtc.tm.tm_sec = from_bcd(value & 0x7f);
633 break;
634 case MENELAUS_RTC_MIN:
635 s->rtc.tm.tm_min = from_bcd(value & 0x7f);
636 break;
637 case MENELAUS_RTC_HR:
638 s->rtc.tm.tm_hour = (s->rtc.ctrl & (1 << 2)) ? /* MODE12_n24 */
639 MIN(from_bcd(value & 0x3f), 12) + ((value >> 7) ? 11 : -1) :
640 from_bcd(value & 0x3f);
641 break;
642 case MENELAUS_RTC_DAY:
643 s->rtc.tm.tm_mday = from_bcd(value);
644 break;
645 case MENELAUS_RTC_MON:
646 s->rtc.tm.tm_mon = MAX(1, from_bcd(value)) - 1;
647 break;
648 case MENELAUS_RTC_YR:
649 s->rtc.tm.tm_year = 2000 + from_bcd(value);
650 break;
651 case MENELAUS_RTC_WKDAY:
652 s->rtc.tm.tm_mday = from_bcd(value);
653 break;
654 case MENELAUS_RTC_AL_SEC:
655 s->rtc.alm.tm_sec = from_bcd(value & 0x7f);
656 menelaus_alm_update(s);
657 break;
658 case MENELAUS_RTC_AL_MIN:
659 s->rtc.alm.tm_min = from_bcd(value & 0x7f);
660 menelaus_alm_update(s);
661 break;
662 case MENELAUS_RTC_AL_HR:
663 s->rtc.alm.tm_hour = (s->rtc.ctrl & (1 << 2)) ? /* MODE12_n24 */
664 MIN(from_bcd(value & 0x3f), 12) + ((value >> 7) ? 11 : -1) :
665 from_bcd(value & 0x3f);
666 menelaus_alm_update(s);
667 break;
668 case MENELAUS_RTC_AL_DAY:
669 s->rtc.alm.tm_mday = from_bcd(value);
670 menelaus_alm_update(s);
671 break;
672 case MENELAUS_RTC_AL_MON:
673 s->rtc.alm.tm_mon = MAX(1, from_bcd(value)) - 1;
674 menelaus_alm_update(s);
675 break;
676 case MENELAUS_RTC_AL_YR:
677 s->rtc.alm.tm_year = 2000 + from_bcd(value);
678 menelaus_alm_update(s);
679 break;
680 case MENELAUS_RTC_COMP_MSB:
681 s->rtc.comp &= 0xff;
682 s->rtc.comp |= value << 8;
683 break;
684 case MENELAUS_RTC_COMP_LSB:
685 s->rtc.comp &= 0xff << 8;
686 s->rtc.comp |= value;
687 break;
688
689 case MENELAUS_S1_PULL_EN:
690 s->pull[0] = value;
691 break;
692 case MENELAUS_S1_PULL_DIR:
693 s->pull[1] = value & 0x1f;
694 break;
695 case MENELAUS_S2_PULL_EN:
696 s->pull[2] = value;
697 break;
698 case MENELAUS_S2_PULL_DIR:
699 s->pull[3] = value & 0x1f;
700 break;
701
702 case MENELAUS_MCT_CTRL1:
703 s->mmc_ctrl[0] = value & 0x7f;
704 break;
705 case MENELAUS_MCT_CTRL2:
706 s->mmc_ctrl[1] = value;
707 /* TODO update Card Detect interrupts */
708 break;
709 case MENELAUS_MCT_CTRL3:
710 s->mmc_ctrl[2] = value & 0xf;
711 break;
712 case MENELAUS_DEBOUNCE1:
713 s->mmc_debounce = value & 0x3f;
714 break;
715
716 default:
717#ifdef VERBOSE
718 printf("%s: unknown register %02x\n", __FUNCTION__, addr);
719#endif
720 }
721}
722
723static void menelaus_event(i2c_slave *i2c, enum i2c_event event)
724{
bc24a225 725 MenelausState *s = (MenelausState *) i2c;
7e7c5e4c
AZ		 726
727 if (event == I2C_START_SEND)
728 s->firstbyte = 1;
729}
730
731static int menelaus_tx(i2c_slave *i2c, uint8_t data)
732{
bc24a225 733 MenelausState *s = (MenelausState *) i2c;
7e7c5e4c
AZ		 734 /* Interpret register address byte */
735 if (s->firstbyte) {
736 s->reg = data;
737 s->firstbyte = 0;
738 } else
739 menelaus_write(s, s->reg ++, data);
740
741 return 0;
742}
743
744static int menelaus_rx(i2c_slave *i2c)
745{
bc24a225 746 MenelausState *s = (MenelausState *) i2c;
7e7c5e4c
AZ		 747
748 return menelaus_read(s, s->reg ++);
749}
750
751static void tm_put(QEMUFile *f, struct tm *tm) {
752 qemu_put_be16(f, tm->tm_sec);
753 qemu_put_be16(f, tm->tm_min);
754 qemu_put_be16(f, tm->tm_hour);
755 qemu_put_be16(f, tm->tm_mday);
756 qemu_put_be16(f, tm->tm_min);
757 qemu_put_be16(f, tm->tm_year);
758}
759
760static void tm_get(QEMUFile *f, struct tm *tm) {
761 tm->tm_sec = qemu_get_be16(f);
762 tm->tm_min = qemu_get_be16(f);
763 tm->tm_hour = qemu_get_be16(f);
764 tm->tm_mday = qemu_get_be16(f);
765 tm->tm_min = qemu_get_be16(f);
766 tm->tm_year = qemu_get_be16(f);
767}
768
769static void menelaus_save(QEMUFile *f, void *opaque)
770{
bc24a225 771 MenelausState *s = (MenelausState *) opaque;
7e7c5e4c
AZ		 772
773 qemu_put_be32(f, s->firstbyte);
774 qemu_put_8s(f, &s->reg);
775
776 qemu_put_8s(f, &s->vcore[0]);
777 qemu_put_8s(f, &s->vcore[1]);
778 qemu_put_8s(f, &s->vcore[2]);
779 qemu_put_8s(f, &s->vcore[3]);
780 qemu_put_8s(f, &s->vcore[4]);
2ba2d706
AZ		 781 qemu_put_8s(f, &s->dcdc[0]);
782 qemu_put_8s(f, &s->dcdc[1]);
783 qemu_put_8s(f, &s->dcdc[2]);
7e7c5e4c
AZ		 784 qemu_put_8s(f, &s->ldo[0]);
785 qemu_put_8s(f, &s->ldo[1]);
786 qemu_put_8s(f, &s->ldo[2]);
787 qemu_put_8s(f, &s->ldo[3]);
788 qemu_put_8s(f, &s->ldo[4]);
789 qemu_put_8s(f, &s->ldo[5]);
790 qemu_put_8s(f, &s->ldo[6]);
791 qemu_put_8s(f, &s->ldo[7]);
792 qemu_put_8s(f, &s->sleep[0]);
793 qemu_put_8s(f, &s->sleep[1]);
794 qemu_put_8s(f, &s->osc);
795 qemu_put_8s(f, &s->detect);
796 qemu_put_be16s(f, &s->mask);
797 qemu_put_be16s(f, &s->status);
798 qemu_put_8s(f, &s->dir);
799 qemu_put_8s(f, &s->inputs);
800 qemu_put_8s(f, &s->outputs);
801 qemu_put_8s(f, &s->bbsms);
802 qemu_put_8s(f, &s->pull[0]);
803 qemu_put_8s(f, &s->pull[1]);
804 qemu_put_8s(f, &s->pull[2]);
805 qemu_put_8s(f, &s->pull[3]);
806 qemu_put_8s(f, &s->mmc_ctrl[0]);
807 qemu_put_8s(f, &s->mmc_ctrl[1]);
808 qemu_put_8s(f, &s->mmc_ctrl[2]);
809 qemu_put_8s(f, &s->mmc_debounce);
810 qemu_put_8s(f, &s->rtc.ctrl);
811 qemu_put_be16s(f, &s->rtc.comp);
812 /* Should be <= 1000 */
813 qemu_put_be16(f, s->rtc.next - qemu_get_clock(rt_clock));
814 tm_put(f, &s->rtc.new);
815 tm_put(f, &s->rtc.alm);
816 qemu_put_byte(f, s->pwrbtn_state);
817
818 i2c_slave_save(f, &s->i2c);
819}
820
821static int menelaus_load(QEMUFile *f, void *opaque, int version_id)
822{
bc24a225 823 MenelausState *s = (MenelausState *) opaque;
7e7c5e4c
AZ		 824
825 s->firstbyte = qemu_get_be32(f);
826 qemu_get_8s(f, &s->reg);
827
828 if (s->rtc.ctrl & 1) /* RTC_EN */
829 menelaus_rtc_stop(s);
830 qemu_get_8s(f, &s->vcore[0]);
831 qemu_get_8s(f, &s->vcore[1]);
832 qemu_get_8s(f, &s->vcore[2]);
833 qemu_get_8s(f, &s->vcore[3]);
834 qemu_get_8s(f, &s->vcore[4]);
2ba2d706
AZ		 835 qemu_get_8s(f, &s->dcdc[0]);
836 qemu_get_8s(f, &s->dcdc[1]);
837 qemu_get_8s(f, &s->dcdc[2]);
7e7c5e4c
AZ		 838 qemu_get_8s(f, &s->ldo[0]);
839 qemu_get_8s(f, &s->ldo[1]);
840 qemu_get_8s(f, &s->ldo[2]);
841 qemu_get_8s(f, &s->ldo[3]);
842 qemu_get_8s(f, &s->ldo[4]);
843 qemu_get_8s(f, &s->ldo[5]);
844 qemu_get_8s(f, &s->ldo[6]);
845 qemu_get_8s(f, &s->ldo[7]);
846 qemu_get_8s(f, &s->sleep[0]);
847 qemu_get_8s(f, &s->sleep[1]);
848 qemu_get_8s(f, &s->osc);
849 qemu_get_8s(f, &s->detect);
850 qemu_get_be16s(f, &s->mask);
851 qemu_get_be16s(f, &s->status);
852 qemu_get_8s(f, &s->dir);
853 qemu_get_8s(f, &s->inputs);
854 qemu_get_8s(f, &s->outputs);
855 qemu_get_8s(f, &s->bbsms);
856 qemu_get_8s(f, &s->pull[0]);
857 qemu_get_8s(f, &s->pull[1]);
858 qemu_get_8s(f, &s->pull[2]);
859 qemu_get_8s(f, &s->pull[3]);
860 qemu_get_8s(f, &s->mmc_ctrl[0]);
861 qemu_get_8s(f, &s->mmc_ctrl[1]);
862 qemu_get_8s(f, &s->mmc_ctrl[2]);
863 qemu_get_8s(f, &s->mmc_debounce);
864 qemu_get_8s(f, &s->rtc.ctrl);
865 qemu_get_be16s(f, &s->rtc.comp);
866 s->rtc.next = qemu_get_be16(f);
867 tm_get(f, &s->rtc.new);
868 tm_get(f, &s->rtc.alm);
869 s->pwrbtn_state = qemu_get_byte(f);
870 menelaus_alm_update(s);
871 menelaus_update(s);
872 if (s->rtc.ctrl & 1) /* RTC_EN */
873 menelaus_rtc_start(s);
874
875 i2c_slave_load(f, &s->i2c);
876 return 0;
877}
878
d3356811 879static void twl92230_init(i2c_slave *i2c)
7e7c5e4c 880{
d3356811 881 MenelausState *s = FROM_I2C_SLAVE(MenelausState, i2c);
7e7c5e4c 882
b0f74c87 883 s->rtc.hz_tm = qemu_new_timer(rt_clock, menelaus_rtc_hz, s);
d3356811
PB		 884 /* Three output pins plus one interrupt pin. */
885 qdev_init_gpio_out(&i2c->qdev, s->out, 4);
886 qdev_init_gpio_in(&i2c->qdev, menelaus_gpio_set, 3);
7e7c5e4c
AZ		 887 s->pwrbtn = qemu_allocate_irqs(menelaus_pwrbtn_set, s, 1)[0];
888
889 menelaus_reset(&s->i2c);
890
18be5187 891 register_savevm("menelaus", -1, 0, menelaus_save, menelaus_load, s);
7e7c5e4c
AZ		 892}
893
d3356811
PB		 894static I2CSlaveInfo twl92230_info = {
895 .init = twl92230_init,
896 .event = menelaus_event,
897 .recv = menelaus_rx,
898 .send = menelaus_tx
899};
7e7c5e4c 900
d3356811 901static void twl92230_register_devices(void)
7e7c5e4c 902{
d3356811 903 i2c_register_slave("twl92230", sizeof(MenelausState), &twl92230_info);
7e7c5e4c 904}
d3356811
PB		 905
906device_init(twl92230_register_devices)
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