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b8616055 AB |
1 | /* |
2 | * LED, Switch and Debug control registers for ARM Integrator Boards | |
3 | * | |
4 | * This is currently a stub for this functionality but at least | |
5 | * ensures something other than unassigned_mem_read() handles access | |
6 | * to this area. | |
7 | * | |
8 | * The real h/w is described at: | |
9 | * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0159b/Babbfijf.html | |
10 | * | |
11 | * Copyright (c) 2013 Alex Bennée <[email protected]> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
14 | * See the COPYING file in the top-level directory. | |
15 | */ | |
16 | ||
0d1c9782 | 17 | #include "qemu/osdep.h" |
b8616055 AB |
18 | #include "hw/hw.h" |
19 | #include "hw/sysbus.h" | |
20 | #include "exec/address-spaces.h" | |
21 | #include "hw/misc/arm_integrator_debug.h" | |
22 | ||
23 | #define INTEGRATOR_DEBUG(obj) \ | |
24 | OBJECT_CHECK(IntegratorDebugState, (obj), TYPE_INTEGRATOR_DEBUG) | |
25 | ||
26 | typedef struct { | |
27 | SysBusDevice parent_obj; | |
28 | ||
29 | MemoryRegion iomem; | |
30 | } IntegratorDebugState; | |
31 | ||
32 | static uint64_t intdbg_control_read(void *opaque, hwaddr offset, | |
33 | unsigned size) | |
34 | { | |
35 | switch (offset >> 2) { | |
36 | case 0: /* ALPHA */ | |
37 | case 1: /* LEDS */ | |
38 | case 2: /* SWITCHES */ | |
39 | qemu_log_mask(LOG_UNIMP, | |
40 | "%s: returning zero from %" HWADDR_PRIx ":%u\n", | |
41 | __func__, offset, size); | |
42 | return 0; | |
43 | default: | |
44 | qemu_log_mask(LOG_GUEST_ERROR, | |
45 | "%s: Bad offset %" HWADDR_PRIx, | |
46 | __func__, offset); | |
47 | return 0; | |
48 | } | |
49 | } | |
50 | ||
51 | static void intdbg_control_write(void *opaque, hwaddr offset, | |
52 | uint64_t value, unsigned size) | |
53 | { | |
54 | switch (offset >> 2) { | |
55 | case 1: /* ALPHA */ | |
56 | case 2: /* LEDS */ | |
57 | case 3: /* SWITCHES */ | |
58 | /* Nothing interesting implemented yet. */ | |
59 | qemu_log_mask(LOG_UNIMP, | |
60 | "%s: ignoring write of %" PRIu64 | |
61 | " to %" HWADDR_PRIx ":%u\n", | |
62 | __func__, value, offset, size); | |
63 | break; | |
64 | default: | |
65 | qemu_log_mask(LOG_GUEST_ERROR, | |
66 | "%s: write of %" PRIu64 | |
67 | " to bad offset %" HWADDR_PRIx "\n", | |
68 | __func__, value, offset); | |
69 | } | |
70 | } | |
71 | ||
72 | static const MemoryRegionOps intdbg_control_ops = { | |
73 | .read = intdbg_control_read, | |
74 | .write = intdbg_control_write, | |
75 | .endianness = DEVICE_NATIVE_ENDIAN, | |
76 | }; | |
77 | ||
78 | static void intdbg_control_init(Object *obj) | |
79 | { | |
80 | SysBusDevice *sd = SYS_BUS_DEVICE(obj); | |
81 | IntegratorDebugState *s = INTEGRATOR_DEBUG(obj); | |
82 | ||
81e0ab48 | 83 | memory_region_init_io(&s->iomem, obj, &intdbg_control_ops, |
b8616055 AB |
84 | NULL, "dbg-leds", 0x1000000); |
85 | sysbus_init_mmio(sd, &s->iomem); | |
86 | } | |
87 | ||
88 | static const TypeInfo intdbg_info = { | |
89 | .name = TYPE_INTEGRATOR_DEBUG, | |
90 | .parent = TYPE_SYS_BUS_DEVICE, | |
91 | .instance_size = sizeof(IntegratorDebugState), | |
92 | .instance_init = intdbg_control_init, | |
93 | }; | |
94 | ||
95 | static void intdbg_register_types(void) | |
96 | { | |
97 | type_register_static(&intdbg_info); | |
98 | } | |
99 | ||
100 | type_init(intdbg_register_types) |