[qemu.git] / ioport.c

/*
 * QEMU System Emulator
 *
 * Copyright (c) 2003-2008 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
/*
 * splitted out ioport related stuffs from vl.c.
 */

#include "exec/ioport.h"
#include "trace.h"
#include "exec/memory.h"

/***********************************************************/
/* IO Port */

//#define DEBUG_UNUSED_IOPORT
//#define DEBUG_IOPORT

#ifdef DEBUG_UNUSED_IOPORT
#  define LOG_UNUSED_IOPORT(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
#else
#  define LOG_UNUSED_IOPORT(fmt, ...) do{ } while (0)
#endif

#ifdef DEBUG_IOPORT
#  define LOG_IOPORT(...) qemu_log_mask(CPU_LOG_IOPORT, ## __VA_ARGS__)
#else
#  define LOG_IOPORT(...) do { } while (0)
#endif

/* XXX: use a two level table to limit memory usage */

static void *ioport_opaque[MAX_IOPORTS];
static IOPortReadFunc *ioport_read_table[3][MAX_IOPORTS];
static IOPortWriteFunc *ioport_write_table[3][MAX_IOPORTS];
static IOPortDestructor *ioport_destructor_table[MAX_IOPORTS];

static IOPortReadFunc default_ioport_readb, default_ioport_readw, default_ioport_readl;
static IOPortWriteFunc default_ioport_writeb, default_ioport_writew, default_ioport_writel;

static uint32_t ioport_read(int index, uint32_t address)
{
    static IOPortReadFunc * const default_func[3] = {
        default_ioport_readb,
        default_ioport_readw,
        default_ioport_readl
    };
    IOPortReadFunc *func = ioport_read_table[index][address];
    if (!func)
        func = default_func[index];
    return func(ioport_opaque[address], address);
}

static void ioport_write(int index, uint32_t address, uint32_t data)
{
    static IOPortWriteFunc * const default_func[3] = {
        default_ioport_writeb,
        default_ioport_writew,
        default_ioport_writel
    };
    IOPortWriteFunc *func = ioport_write_table[index][address];
    if (!func)
        func = default_func[index];
    func(ioport_opaque[address], address, data);
}

static uint32_t default_ioport_readb(void *opaque, uint32_t address)
{
    LOG_UNUSED_IOPORT("unused inb: port=0x%04"PRIx32"\n", address);
    return 0xff;
}

static void default_ioport_writeb(void *opaque, uint32_t address, uint32_t data)
{
    LOG_UNUSED_IOPORT("unused outb: port=0x%04"PRIx32" data=0x%02"PRIx32"\n",
                      address, data);
}

/* default is to make two byte accesses */
static uint32_t default_ioport_readw(void *opaque, uint32_t address)
{
    uint32_t data;
    data = ioport_read(0, address);
    address = (address + 1) & IOPORTS_MASK;
    data |= ioport_read(0, address) << 8;
    return data;
}

static void default_ioport_writew(void *opaque, uint32_t address, uint32_t data)
{
    ioport_write(0, address, data & 0xff);
    address = (address + 1) & IOPORTS_MASK;
    ioport_write(0, address, (data >> 8) & 0xff);
}

static uint32_t default_ioport_readl(void *opaque, uint32_t address)
{
    LOG_UNUSED_IOPORT("unused inl: port=0x%04"PRIx32"\n", address);
    return 0xffffffff;
}

static void default_ioport_writel(void *opaque, uint32_t address, uint32_t data)
{
    LOG_UNUSED_IOPORT("unused outl: port=0x%04"PRIx32" data=0x%02"PRIx32"\n",
                      address, data);
}

static int ioport_bsize(int size, int *bsize)
{
    if (size == 1) {
        *bsize = 0;
    } else if (size == 2) {
        *bsize = 1;
    } else if (size == 4) {
        *bsize = 2;
    } else {
        return -1;
    }
    return 0;
}

/* size is the word size in byte */
int register_ioport_read(pio_addr_t start, int length, int size,
                         IOPortReadFunc *func, void *opaque)
{
    int i, bsize;

    if (ioport_bsize(size, &bsize)) {
        hw_error("register_ioport_read: invalid size");
        return -1;
    }
    for(i = start; i < start + length; ++i) {
        ioport_read_table[bsize][i] = func;
        if (ioport_opaque[i] != NULL && ioport_opaque[i] != opaque)
            hw_error("register_ioport_read: invalid opaque for address 0x%x",
                     i);
        ioport_opaque[i] = opaque;
    }
    return 0;
}

/* size is the word size in byte */
int register_ioport_write(pio_addr_t start, int length, int size,
                          IOPortWriteFunc *func, void *opaque)
{
    int i, bsize;

    if (ioport_bsize(size, &bsize)) {
        hw_error("register_ioport_write: invalid size");
        return -1;
    }
    for(i = start; i < start + length; ++i) {
        ioport_write_table[bsize][i] = func;
        if (ioport_opaque[i] != NULL && ioport_opaque[i] != opaque)
            hw_error("register_ioport_write: invalid opaque for address 0x%x",
                     i);
        ioport_opaque[i] = opaque;
    }
    return 0;
}

static uint32_t ioport_readb_thunk(void *opaque, uint32_t addr)
{
    IORange *ioport = opaque;
    uint64_t data;

    ioport->ops->read(ioport, addr - ioport->base, 1, &data);
    return data;
}

static uint32_t ioport_readw_thunk(void *opaque, uint32_t addr)
{
    IORange *ioport = opaque;
    uint64_t data;

    ioport->ops->read(ioport, addr - ioport->base, 2, &data);
    return data;
}

static uint32_t ioport_readl_thunk(void *opaque, uint32_t addr)
{
    IORange *ioport = opaque;
    uint64_t data;

    ioport->ops->read(ioport, addr - ioport->base, 4, &data);
    return data;
}

static void ioport_writeb_thunk(void *opaque, uint32_t addr, uint32_t data)
{
    IORange *ioport = opaque;

    ioport->ops->write(ioport, addr - ioport->base, 1, data);
}

static void ioport_writew_thunk(void *opaque, uint32_t addr, uint32_t data)
{
    IORange *ioport = opaque;

    ioport->ops->write(ioport, addr - ioport->base, 2, data);
}

static void ioport_writel_thunk(void *opaque, uint32_t addr, uint32_t data)
{
    IORange *ioport = opaque;

    ioport->ops->write(ioport, addr - ioport->base, 4, data);
}

static void iorange_destructor_thunk(void *opaque)
{
    IORange *iorange = opaque;

    if (iorange->ops->destructor) {
        iorange->ops->destructor(iorange);
    }
}

void ioport_register(IORange *ioport)
{
    register_ioport_read(ioport->base, ioport->len, 1,
                         ioport_readb_thunk, ioport);
    register_ioport_read(ioport->base, ioport->len, 2,
                         ioport_readw_thunk, ioport);
    register_ioport_read(ioport->base, ioport->len, 4,
                         ioport_readl_thunk, ioport);
    register_ioport_write(ioport->base, ioport->len, 1,
                          ioport_writeb_thunk, ioport);
    register_ioport_write(ioport->base, ioport->len, 2,
                          ioport_writew_thunk, ioport);
    register_ioport_write(ioport->base, ioport->len, 4,
                          ioport_writel_thunk, ioport);
    ioport_destructor_table[ioport->base] = iorange_destructor_thunk;
}

void isa_unassign_ioport(pio_addr_t start, int length)
{
    int i;

    if (ioport_destructor_table[start]) {
        ioport_destructor_table[start](ioport_opaque[start]);
        ioport_destructor_table[start] = NULL;
    }
    for(i = start; i < start + length; i++) {
        ioport_read_table[0][i] = NULL;
        ioport_read_table[1][i] = NULL;
        ioport_read_table[2][i] = NULL;

        ioport_write_table[0][i] = NULL;
        ioport_write_table[1][i] = NULL;
        ioport_write_table[2][i] = NULL;

        ioport_opaque[i] = NULL;
    }
}

bool isa_is_ioport_assigned(pio_addr_t start)
{
    return (ioport_read_table[0][start] || ioport_write_table[0][start] ||
	    ioport_read_table[1][start] || ioport_write_table[1][start] ||
	    ioport_read_table[2][start] || ioport_write_table[2][start]);
}

/***********************************************************/

void cpu_outb(pio_addr_t addr, uint8_t val)
{
    LOG_IOPORT("outb: %04"FMT_pioaddr" %02"PRIx8"\n", addr, val);
    trace_cpu_out(addr, val);
    ioport_write(0, addr, val);
}

void cpu_outw(pio_addr_t addr, uint16_t val)
{
    LOG_IOPORT("outw: %04"FMT_pioaddr" %04"PRIx16"\n", addr, val);
    trace_cpu_out(addr, val);
    ioport_write(1, addr, val);
}

void cpu_outl(pio_addr_t addr, uint32_t val)
{
    LOG_IOPORT("outl: %04"FMT_pioaddr" %08"PRIx32"\n", addr, val);
    trace_cpu_out(addr, val);
    ioport_write(2, addr, val);
}

uint8_t cpu_inb(pio_addr_t addr)
{
    uint8_t val;
    val = ioport_read(0, addr);
    trace_cpu_in(addr, val);
    LOG_IOPORT("inb : %04"FMT_pioaddr" %02"PRIx8"\n", addr, val);
    return val;
}

uint16_t cpu_inw(pio_addr_t addr)
{
    uint16_t val;
    val = ioport_read(1, addr);
    trace_cpu_in(addr, val);
    LOG_IOPORT("inw : %04"FMT_pioaddr" %04"PRIx16"\n", addr, val);
    return val;
}

uint32_t cpu_inl(pio_addr_t addr)
{
    uint32_t val;
    val = ioport_read(2, addr);
    trace_cpu_in(addr, val);
    LOG_IOPORT("inl : %04"FMT_pioaddr" %08"PRIx32"\n", addr, val);
    return val;
}

void portio_list_init(PortioList *piolist,
                      const MemoryRegionPortio *callbacks,
                      void *opaque, const char *name)
{
    unsigned n = 0;

    while (callbacks[n].size) {
        ++n;
    }

    piolist->ports = callbacks;
    piolist->nr = 0;
    piolist->regions = g_new0(MemoryRegion *, n);
    piolist->aliases = g_new0(MemoryRegion *, n);
    piolist->address_space = NULL;
    piolist->opaque = opaque;
    piolist->name = name;
}

void portio_list_destroy(PortioList *piolist)
{
    g_free(piolist->regions);
    g_free(piolist->aliases);
}

static void portio_list_add_1(PortioList *piolist,
                              const MemoryRegionPortio *pio_init,
                              unsigned count, unsigned start,
                              unsigned off_low, unsigned off_high)
{
    MemoryRegionPortio *pio;
    MemoryRegionOps *ops;
    MemoryRegion *region, *alias;
    unsigned i;

    /* Copy the sub-list and null-terminate it.  */
    pio = g_new(MemoryRegionPortio, count + 1);
    memcpy(pio, pio_init, sizeof(MemoryRegionPortio) * count);
    memset(pio + count, 0, sizeof(MemoryRegionPortio));

    /* Adjust the offsets to all be zero-based for the region.  */
    for (i = 0; i < count; ++i) {
        pio[i].offset -= off_low;
    }

    ops = g_new0(MemoryRegionOps, 1);
    ops->old_portio = pio;

    region = g_new(MemoryRegion, 1);
    alias = g_new(MemoryRegion, 1);
    /*
     * Use an alias so that the callback is called with an absolute address,
     * rather than an offset relative to to start + off_low.
     */
    memory_region_init_io(region, ops, piolist->opaque, piolist->name,
                          INT64_MAX);
    memory_region_init_alias(alias, piolist->name,
                             region, start + off_low, off_high - off_low);
    memory_region_add_subregion(piolist->address_space,
                                start + off_low, alias);
    piolist->regions[piolist->nr] = region;
    piolist->aliases[piolist->nr] = alias;
    ++piolist->nr;
}

void portio_list_add(PortioList *piolist,
                     MemoryRegion *address_space,
                     uint32_t start)
{
    const MemoryRegionPortio *pio, *pio_start = piolist->ports;
    unsigned int off_low, off_high, off_last, count;

    piolist->address_space = address_space;

    /* Handle the first entry specially.  */
    off_last = off_low = pio_start->offset;
    off_high = off_low + pio_start->len;
    count = 1;

    for (pio = pio_start + 1; pio->size != 0; pio++, count++) {
        /* All entries must be sorted by offset.  */
        assert(pio->offset >= off_last);
        off_last = pio->offset;

        /* If we see a hole, break the region.  */
        if (off_last > off_high) {
            portio_list_add_1(piolist, pio_start, count, start, off_low,
                              off_high);
            /* ... and start collecting anew.  */
            pio_start = pio;
            off_low = off_last;
            off_high = off_low + pio->len;
            count = 0;
        } else if (off_last + pio->len > off_high) {
            off_high = off_last + pio->len;
        }
    }

    /* There will always be an open sub-list.  */
    portio_list_add_1(piolist, pio_start, count, start, off_low, off_high);
}

void portio_list_del(PortioList *piolist)
{
    MemoryRegion *mr, *alias;
    unsigned i;

    for (i = 0; i < piolist->nr; ++i) {
        mr = piolist->regions[i];
        alias = piolist->aliases[i];
        memory_region_del_subregion(piolist->address_space, alias);
        memory_region_destroy(alias);
        memory_region_destroy(mr);
        g_free((MemoryRegionOps *)mr->ops);
        g_free(mr);
        g_free(alias);
        piolist->regions[i] = NULL;
        piolist->aliases[i] = NULL;
    }
}
Commit	Line	Data
32993977 IY	1	/*
	2	* QEMU System Emulator
	3	*
	4	* Copyright (c) 2003-2008 Fabrice Bellard
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	/*
	25	* splitted out ioport related stuffs from vl.c.
	26	*/
	27
022c62cb	28	#include "exec/ioport.h"
bd3c9aa5	29	#include "trace.h"
022c62cb	30	#include "exec/memory.h"
32993977 IY	31
	32	/***********************************************************/
	33	/* IO Port */
	34
	35	//#define DEBUG_UNUSED_IOPORT
	36	//#define DEBUG_IOPORT
	37
fc7083b5 IY	38	#ifdef DEBUG_UNUSED_IOPORT
	39	# define LOG_UNUSED_IOPORT(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
	40	#else
	41	# define LOG_UNUSED_IOPORT(fmt, ...) do{ } while (0)
	42	#endif
	43
32993977 IY	44	#ifdef DEBUG_IOPORT
	45	# define LOG_IOPORT(...) qemu_log_mask(CPU_LOG_IOPORT, ## __VA_ARGS__)
	46	#else
	47	# define LOG_IOPORT(...) do { } while (0)
	48	#endif
	49
	50	/* XXX: use a two level table to limit memory usage */
	51
	52	static void *ioport_opaque[MAX_IOPORTS];
	53	static IOPortReadFunc *ioport_read_table[3][MAX_IOPORTS];
	54	static IOPortWriteFunc *ioport_write_table[3][MAX_IOPORTS];
c5b703ac	55	static IOPortDestructor *ioport_destructor_table[MAX_IOPORTS];
32993977 IY	56
	57	static IOPortReadFunc default_ioport_readb, default_ioport_readw, default_ioport_readl;
	58	static IOPortWriteFunc default_ioport_writeb, default_ioport_writew, default_ioport_writel;
	59
	60	static uint32_t ioport_read(int index, uint32_t address)
	61	{
1dde6fcc	62	static IOPortReadFunc * const default_func[3] = {
32993977 IY	63	default_ioport_readb,
	64	default_ioport_readw,
	65	default_ioport_readl
	66	};
	67	IOPortReadFunc *func = ioport_read_table[index][address];
	68	if (!func)
	69	func = default_func[index];
	70	return func(ioport_opaque[address], address);
	71	}
	72
	73	static void ioport_write(int index, uint32_t address, uint32_t data)
	74	{
1dde6fcc	75	static IOPortWriteFunc * const default_func[3] = {
32993977 IY	76	default_ioport_writeb,
	77	default_ioport_writew,
	78	default_ioport_writel
	79	};
	80	IOPortWriteFunc *func = ioport_write_table[index][address];
	81	if (!func)
	82	func = default_func[index];
	83	func(ioport_opaque[address], address, data);
	84	}
	85
	86	static uint32_t default_ioport_readb(void *opaque, uint32_t address)
	87	{
fc7083b5	88	LOG_UNUSED_IOPORT("unused inb: port=0x%04"PRIx32"\n", address);
32993977 IY	89	return 0xff;
	90	}
	91
	92	static void default_ioport_writeb(void *opaque, uint32_t address, uint32_t data)
	93	{
fc7083b5 IY	94	LOG_UNUSED_IOPORT("unused outb: port=0x%04"PRIx32" data=0x%02"PRIx32"\n",
fc7083b5 IY	95	address, data);
32993977 IY	96	}
	97
	98	/* default is to make two byte accesses */
	99	static uint32_t default_ioport_readw(void *opaque, uint32_t address)
	100	{
	101	uint32_t data;
	102	data = ioport_read(0, address);
d56dd6cf	103	address = (address + 1) & IOPORTS_MASK;
32993977 IY	104	data \|= ioport_read(0, address) << 8;
	105	return data;
	106	}
	107
	108	static void default_ioport_writew(void *opaque, uint32_t address, uint32_t data)
	109	{
	110	ioport_write(0, address, data & 0xff);
d56dd6cf	111	address = (address + 1) & IOPORTS_MASK;
32993977 IY	112	ioport_write(0, address, (data >> 8) & 0xff);
	113	}
	114
	115	static uint32_t default_ioport_readl(void *opaque, uint32_t address)
	116	{
fc7083b5	117	LOG_UNUSED_IOPORT("unused inl: port=0x%04"PRIx32"\n", address);
32993977 IY	118	return 0xffffffff;
	119	}
	120
	121	static void default_ioport_writel(void *opaque, uint32_t address, uint32_t data)
	122	{
fc7083b5 IY	123	LOG_UNUSED_IOPORT("unused outl: port=0x%04"PRIx32" data=0x%02"PRIx32"\n",
fc7083b5 IY	124	address, data);
32993977 IY	125	}
32993977 IY	126
23e0affd IY	127	static int ioport_bsize(int size, int *bsize)
	128	{
	129	if (size == 1) {
	130	*bsize = 0;
	131	} else if (size == 2) {
	132	*bsize = 1;
	133	} else if (size == 4) {
	134	*bsize = 2;
	135	} else {
	136	return -1;
	137	}
	138	return 0;
	139	}
	140
32993977	141	/* size is the word size in byte */
c227f099	142	int register_ioport_read(pio_addr_t start, int length, int size,
32993977 IY	143	IOPortReadFunc func, void opaque)
	144	{
	145	int i, bsize;
	146
23e0affd	147	if (ioport_bsize(size, &bsize)) {
32993977 IY	148	hw_error("register_ioport_read: invalid size");
	149	return -1;
	150	}
bf3fb0e1	151	for(i = start; i < start + length; ++i) {
32993977 IY	152	ioport_read_table[bsize][i] = func;
32993977 IY	153	if (ioport_opaque[i] != NULL && ioport_opaque[i] != opaque)
f66a99d7 AF	154	hw_error("register_ioport_read: invalid opaque for address 0x%x",
f66a99d7 AF	155	i);
32993977 IY	156	ioport_opaque[i] = opaque;
	157	}
	158	return 0;
	159	}
	160
	161	/* size is the word size in byte */
c227f099	162	int register_ioport_write(pio_addr_t start, int length, int size,
32993977 IY	163	IOPortWriteFunc func, void opaque)
	164	{
	165	int i, bsize;
	166
23e0affd	167	if (ioport_bsize(size, &bsize)) {
32993977 IY	168	hw_error("register_ioport_write: invalid size");
	169	return -1;
	170	}
bf3fb0e1	171	for(i = start; i < start + length; ++i) {
32993977 IY	172	ioport_write_table[bsize][i] = func;
32993977 IY	173	if (ioport_opaque[i] != NULL && ioport_opaque[i] != opaque)
f66a99d7 AF	174	hw_error("register_ioport_write: invalid opaque for address 0x%x",
f66a99d7 AF	175	i);
32993977 IY	176	ioport_opaque[i] = opaque;
	177	}
	178	return 0;
	179	}
	180
acd1c812 AK	181	static uint32_t ioport_readb_thunk(void *opaque, uint32_t addr)
	182	{
	183	IORange *ioport = opaque;
	184	uint64_t data;
	185
	186	ioport->ops->read(ioport, addr - ioport->base, 1, &data);
	187	return data;
	188	}
	189
	190	static uint32_t ioport_readw_thunk(void *opaque, uint32_t addr)
	191	{
	192	IORange *ioport = opaque;
	193	uint64_t data;
	194
	195	ioport->ops->read(ioport, addr - ioport->base, 2, &data);
	196	return data;
	197	}
	198
	199	static uint32_t ioport_readl_thunk(void *opaque, uint32_t addr)
	200	{
	201	IORange *ioport = opaque;
	202	uint64_t data;
	203
	204	ioport->ops->read(ioport, addr - ioport->base, 4, &data);
	205	return data;
	206	}
	207
	208	static void ioport_writeb_thunk(void *opaque, uint32_t addr, uint32_t data)
	209	{
	210	IORange *ioport = opaque;
	211
	212	ioport->ops->write(ioport, addr - ioport->base, 1, data);
	213	}
	214
	215	static void ioport_writew_thunk(void *opaque, uint32_t addr, uint32_t data)
	216	{
	217	IORange *ioport = opaque;
	218
	219	ioport->ops->write(ioport, addr - ioport->base, 2, data);
	220	}
	221
	222	static void ioport_writel_thunk(void *opaque, uint32_t addr, uint32_t data)
	223	{
	224	IORange *ioport = opaque;
	225
	226	ioport->ops->write(ioport, addr - ioport->base, 4, data);
	227	}
	228
c5b703ac AK	229	static void iorange_destructor_thunk(void *opaque)
	230	{
	231	IORange *iorange = opaque;
	232
	233	if (iorange->ops->destructor) {
	234	iorange->ops->destructor(iorange);
	235	}
	236	}
	237
acd1c812 AK	238	void ioport_register(IORange *ioport)
	239	{
	240	register_ioport_read(ioport->base, ioport->len, 1,
	241	ioport_readb_thunk, ioport);
	242	register_ioport_read(ioport->base, ioport->len, 2,
	243	ioport_readw_thunk, ioport);
	244	register_ioport_read(ioport->base, ioport->len, 4,
	245	ioport_readl_thunk, ioport);
	246	register_ioport_write(ioport->base, ioport->len, 1,
	247	ioport_writeb_thunk, ioport);
	248	register_ioport_write(ioport->base, ioport->len, 2,
	249	ioport_writew_thunk, ioport);
	250	register_ioport_write(ioport->base, ioport->len, 4,
	251	ioport_writel_thunk, ioport);
c5b703ac	252	ioport_destructor_table[ioport->base] = iorange_destructor_thunk;
acd1c812 AK	253	}
acd1c812 AK	254
c227f099	255	void isa_unassign_ioport(pio_addr_t start, int length)
32993977 IY	256	{
	257	int i;
	258
c5b703ac AK	259	if (ioport_destructor_table[start]) {
	260	ioport_destructor_table[start](ioport_opaque[start]);
	261	ioport_destructor_table[start] = NULL;
	262	}
32993977	263	for(i = start; i < start + length; i++) {
6141dbfe PB	264	ioport_read_table[0][i] = NULL;
	265	ioport_read_table[1][i] = NULL;
	266	ioport_read_table[2][i] = NULL;
32993977	267
6141dbfe PB	268	ioport_write_table[0][i] = NULL;
	269	ioport_write_table[1][i] = NULL;
	270	ioport_write_table[2][i] = NULL;
32993977 IY	271
	272	ioport_opaque[i] = NULL;
	273	}
	274	}
	275
6141dbfe PB	276	bool isa_is_ioport_assigned(pio_addr_t start)
	277	{
	278	return (ioport_read_table[0][start] \|\| ioport_write_table[0][start] \|\|
	279	ioport_read_table[1][start] \|\| ioport_write_table[1][start] \|\|
	280	ioport_read_table[2][start] \|\| ioport_write_table[2][start]);
	281	}
	282
32993977 IY	283	/***********************************************************/
32993977 IY	284
c227f099	285	void cpu_outb(pio_addr_t addr, uint8_t val)
32993977	286	{
07323531	287	LOG_IOPORT("outb: %04"FMT_pioaddr" %02"PRIx8"\n", addr, val);
bd3c9aa5	288	trace_cpu_out(addr, val);
32993977	289	ioport_write(0, addr, val);
32993977 IY	290	}
32993977 IY	291
c227f099	292	void cpu_outw(pio_addr_t addr, uint16_t val)
32993977	293	{
07323531	294	LOG_IOPORT("outw: %04"FMT_pioaddr" %04"PRIx16"\n", addr, val);
bd3c9aa5	295	trace_cpu_out(addr, val);
32993977	296	ioport_write(1, addr, val);
32993977 IY	297	}
32993977 IY	298
c227f099	299	void cpu_outl(pio_addr_t addr, uint32_t val)
32993977	300	{
07323531	301	LOG_IOPORT("outl: %04"FMT_pioaddr" %08"PRIx32"\n", addr, val);
bd3c9aa5	302	trace_cpu_out(addr, val);
32993977	303	ioport_write(2, addr, val);
32993977 IY	304	}
32993977 IY	305
c227f099	306	uint8_t cpu_inb(pio_addr_t addr)
32993977	307	{
07323531	308	uint8_t val;
32993977	309	val = ioport_read(0, addr);
bd3c9aa5	310	trace_cpu_in(addr, val);
07323531	311	LOG_IOPORT("inb : %04"FMT_pioaddr" %02"PRIx8"\n", addr, val);
32993977 IY	312	return val;
	313	}
	314
c227f099	315	uint16_t cpu_inw(pio_addr_t addr)
32993977	316	{
07323531	317	uint16_t val;
32993977	318	val = ioport_read(1, addr);
bd3c9aa5	319	trace_cpu_in(addr, val);
07323531	320	LOG_IOPORT("inw : %04"FMT_pioaddr" %04"PRIx16"\n", addr, val);
32993977 IY	321	return val;
	322	}
	323
c227f099	324	uint32_t cpu_inl(pio_addr_t addr)
32993977	325	{
07323531	326	uint32_t val;
32993977	327	val = ioport_read(2, addr);
bd3c9aa5	328	trace_cpu_in(addr, val);
07323531	329	LOG_IOPORT("inl : %04"FMT_pioaddr" %08"PRIx32"\n", addr, val);
32993977 IY	330	return val;
32993977 IY	331	}
6bf9fd43 AK	332
	333	void portio_list_init(PortioList *piolist,
	334	const MemoryRegionPortio *callbacks,
	335	void opaque, const char name)
	336	{
	337	unsigned n = 0;
	338
	339	while (callbacks[n].size) {
	340	++n;
	341	}
	342
	343	piolist->ports = callbacks;
	344	piolist->nr = 0;
	345	piolist->regions = g_new0(MemoryRegion *, n);
de58ac72	346	piolist->aliases = g_new0(MemoryRegion *, n);
6bf9fd43 AK	347	piolist->address_space = NULL;
	348	piolist->opaque = opaque;
	349	piolist->name = name;
	350	}
	351
	352	void portio_list_destroy(PortioList *piolist)
	353	{
	354	g_free(piolist->regions);
de58ac72	355	g_free(piolist->aliases);
6bf9fd43 AK	356	}
	357
	358	static void portio_list_add_1(PortioList *piolist,
	359	const MemoryRegionPortio *pio_init,
	360	unsigned count, unsigned start,
	361	unsigned off_low, unsigned off_high)
	362	{
	363	MemoryRegionPortio *pio;
	364	MemoryRegionOps *ops;
de58ac72	365	MemoryRegion region, alias;
6bf9fd43 AK	366	unsigned i;
	367
	368	/* Copy the sub-list and null-terminate it. */
	369	pio = g_new(MemoryRegionPortio, count + 1);
	370	memcpy(pio, pio_init, sizeof(MemoryRegionPortio) * count);
	371	memset(pio + count, 0, sizeof(MemoryRegionPortio));
	372
	373	/* Adjust the offsets to all be zero-based for the region. */
	374	for (i = 0; i < count; ++i) {
	375	pio[i].offset -= off_low;
	376	}
	377
	378	ops = g_new0(MemoryRegionOps, 1);
	379	ops->old_portio = pio;
	380
	381	region = g_new(MemoryRegion, 1);
de58ac72 AK	382	alias = g_new(MemoryRegion, 1);
	383	/*
	384	* Use an alias so that the callback is called with an absolute address,
	385	* rather than an offset relative to to start + off_low.
	386	*/
6bf9fd43	387	memory_region_init_io(region, ops, piolist->opaque, piolist->name,
4200872b	388	INT64_MAX);
de58ac72 AK	389	memory_region_init_alias(alias, piolist->name,
de58ac72 AK	390	region, start + off_low, off_high - off_low);
6bf9fd43	391	memory_region_add_subregion(piolist->address_space,
de58ac72 AK	392	start + off_low, alias);
	393	piolist->regions[piolist->nr] = region;
	394	piolist->aliases[piolist->nr] = alias;
	395	++piolist->nr;
6bf9fd43 AK	396	}
	397
	398	void portio_list_add(PortioList *piolist,
	399	MemoryRegion *address_space,
	400	uint32_t start)
	401	{
	402	const MemoryRegionPortio pio, pio_start = piolist->ports;
	403	unsigned int off_low, off_high, off_last, count;
	404
	405	piolist->address_space = address_space;
	406
	407	/* Handle the first entry specially. */
	408	off_last = off_low = pio_start->offset;
	409	off_high = off_low + pio_start->len;
	410	count = 1;
	411
	412	for (pio = pio_start + 1; pio->size != 0; pio++, count++) {
	413	/* All entries must be sorted by offset. */
	414	assert(pio->offset >= off_last);
	415	off_last = pio->offset;
	416
	417	/* If we see a hole, break the region. */
	418	if (off_last > off_high) {
	419	portio_list_add_1(piolist, pio_start, count, start, off_low,
	420	off_high);
	421	/* ... and start collecting anew. */
	422	pio_start = pio;
	423	off_low = off_last;
	424	off_high = off_low + pio->len;
	425	count = 0;
	426	} else if (off_last + pio->len > off_high) {
	427	off_high = off_last + pio->len;
	428	}
	429	}
	430
	431	/* There will always be an open sub-list. */
	432	portio_list_add_1(piolist, pio_start, count, start, off_low, off_high);
	433	}
	434
	435	void portio_list_del(PortioList *piolist)
	436	{
de58ac72	437	MemoryRegion mr, alias;
6bf9fd43 AK	438	unsigned i;
	439
	440	for (i = 0; i < piolist->nr; ++i) {
	441	mr = piolist->regions[i];
de58ac72 AK	442	alias = piolist->aliases[i];
	443	memory_region_del_subregion(piolist->address_space, alias);
	444	memory_region_destroy(alias);
6bf9fd43 AK	445	memory_region_destroy(mr);
	446	g_free((MemoryRegionOps *)mr->ops);
	447	g_free(mr);
de58ac72	448	g_free(alias);
6bf9fd43	449	piolist->regions[i] = NULL;
de58ac72	450	piolist->aliases[i] = NULL;
6bf9fd43 AK	451	}
6bf9fd43 AK	452	}