projects / qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 711b20b4 SB |
1 | /* |
| 2 | * tpm.h - TPM ACPI definitions | |
| 3 | * | |
| 4 | * Copyright (C) 2014 IBM Corporation | |
| 5 | * | |
| 6 | * Authors: | |
| 7 | * Stefan Berger <[email protected]> | |
| 8 | * | |
| 9 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
| 10 | * See the COPYING file in the top-level directory. | |
| 11 | * | |
| 12 | * Implementation of the TIS interface according to specs found at | |
| 13 | * http://www.trustedcomputinggroup.org | |
| 14 | * | |
| 15 | */ | |
| 16 | #ifndef HW_ACPI_TPM_H | |
| 17 | #define HW_ACPI_TPM_H | |
| 18 | ||
| 3d779b93 | 19 | #include "qemu/units.h" |
| 4ab6cb4c | 20 | #include "hw/registerfields.h" |
| ac6dd31e SB |
21 | #include "hw/acpi/aml-build.h" |
| 22 | #include "sysemu/tpm.h" | |
| 4ab6cb4c | 23 | |
| 711b20b4 SB |
24 | #define TPM_TIS_ADDR_BASE 0xFED40000 |
| 25 | #define TPM_TIS_ADDR_SIZE 0x5000 | |
| 26 | ||
| 27 | #define TPM_TIS_IRQ 5 | |
| 28 | ||
| adb0e917 SB |
29 | #define TPM_TIS_NUM_LOCALITIES 5 /* per spec */ |
| 30 | #define TPM_TIS_LOCALITY_SHIFT 12 | |
| 31 | ||
| 32 | /* tis registers */ | |
| 33 | #define TPM_TIS_REG_ACCESS 0x00 | |
| 34 | #define TPM_TIS_REG_INT_ENABLE 0x08 | |
| 35 | #define TPM_TIS_REG_INT_VECTOR 0x0c | |
| 36 | #define TPM_TIS_REG_INT_STATUS 0x10 | |
| 37 | #define TPM_TIS_REG_INTF_CAPABILITY 0x14 | |
| 38 | #define TPM_TIS_REG_STS 0x18 | |
| 39 | #define TPM_TIS_REG_DATA_FIFO 0x24 | |
| 40 | #define TPM_TIS_REG_INTERFACE_ID 0x30 | |
| 41 | #define TPM_TIS_REG_DATA_XFIFO 0x80 | |
| 42 | #define TPM_TIS_REG_DATA_XFIFO_END 0xbc | |
| 43 | #define TPM_TIS_REG_DID_VID 0xf00 | |
| 44 | #define TPM_TIS_REG_RID 0xf04 | |
| 45 | ||
| 46 | /* vendor-specific registers */ | |
| 47 | #define TPM_TIS_REG_DEBUG 0xf90 | |
| 48 | ||
| 49 | #define TPM_TIS_STS_TPM_FAMILY_MASK (0x3 << 26)/* TPM 2.0 */ | |
| 50 | #define TPM_TIS_STS_TPM_FAMILY1_2 (0 << 26) /* TPM 2.0 */ | |
| 51 | #define TPM_TIS_STS_TPM_FAMILY2_0 (1 << 26) /* TPM 2.0 */ | |
| 52 | #define TPM_TIS_STS_RESET_ESTABLISHMENT_BIT (1 << 25) /* TPM 2.0 */ | |
| 53 | #define TPM_TIS_STS_COMMAND_CANCEL (1 << 24) /* TPM 2.0 */ | |
| 54 | ||
| 55 | #define TPM_TIS_STS_VALID (1 << 7) | |
| 56 | #define TPM_TIS_STS_COMMAND_READY (1 << 6) | |
| 57 | #define TPM_TIS_STS_TPM_GO (1 << 5) | |
| 58 | #define TPM_TIS_STS_DATA_AVAILABLE (1 << 4) | |
| 59 | #define TPM_TIS_STS_EXPECT (1 << 3) | |
| 60 | #define TPM_TIS_STS_SELFTEST_DONE (1 << 2) | |
| 61 | #define TPM_TIS_STS_RESPONSE_RETRY (1 << 1) | |
| 62 | ||
| 63 | #define TPM_TIS_BURST_COUNT_SHIFT 8 | |
| 64 | #define TPM_TIS_BURST_COUNT(X) \ | |
| 65 | ((X) << TPM_TIS_BURST_COUNT_SHIFT) | |
| 66 | ||
| 67 | #define TPM_TIS_ACCESS_TPM_REG_VALID_STS (1 << 7) | |
| 68 | #define TPM_TIS_ACCESS_ACTIVE_LOCALITY (1 << 5) | |
| 69 | #define TPM_TIS_ACCESS_BEEN_SEIZED (1 << 4) | |
| 70 | #define TPM_TIS_ACCESS_SEIZE (1 << 3) | |
| 71 | #define TPM_TIS_ACCESS_PENDING_REQUEST (1 << 2) | |
| 72 | #define TPM_TIS_ACCESS_REQUEST_USE (1 << 1) | |
| 73 | #define TPM_TIS_ACCESS_TPM_ESTABLISHMENT (1 << 0) | |
| 74 | ||
| 75 | #define TPM_TIS_INT_ENABLED (1 << 31) | |
| 76 | #define TPM_TIS_INT_DATA_AVAILABLE (1 << 0) | |
| 77 | #define TPM_TIS_INT_STS_VALID (1 << 1) | |
| 78 | #define TPM_TIS_INT_LOCALITY_CHANGED (1 << 2) | |
| 79 | #define TPM_TIS_INT_COMMAND_READY (1 << 7) | |
| 80 | ||
| 81 | #define TPM_TIS_INT_POLARITY_MASK (3 << 3) | |
| 82 | #define TPM_TIS_INT_POLARITY_LOW_LEVEL (1 << 3) | |
| 83 | ||
| 84 | #define TPM_TIS_INTERRUPTS_SUPPORTED (TPM_TIS_INT_LOCALITY_CHANGED | \ | |
| 85 | TPM_TIS_INT_DATA_AVAILABLE | \ | |
| 86 | TPM_TIS_INT_STS_VALID | \ | |
| 87 | TPM_TIS_INT_COMMAND_READY) | |
| 88 | ||
| 89 | #define TPM_TIS_CAP_INTERFACE_VERSION1_3 (2 << 28) | |
| 90 | #define TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 (3 << 28) | |
| 91 | #define TPM_TIS_CAP_DATA_TRANSFER_64B (3 << 9) | |
| 92 | #define TPM_TIS_CAP_DATA_TRANSFER_LEGACY (0 << 9) | |
| 93 | #define TPM_TIS_CAP_BURST_COUNT_DYNAMIC (0 << 8) | |
| 94 | #define TPM_TIS_CAP_INTERRUPT_LOW_LEVEL (1 << 4) /* support is mandatory */ | |
| 95 | #define TPM_TIS_CAPABILITIES_SUPPORTED1_3 \ | |
| 96 | (TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \ | |
| 97 | TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \ | |
| 98 | TPM_TIS_CAP_DATA_TRANSFER_64B | \ | |
| 99 | TPM_TIS_CAP_INTERFACE_VERSION1_3 | \ | |
| 100 | TPM_TIS_INTERRUPTS_SUPPORTED) | |
| 101 | ||
| 102 | #define TPM_TIS_CAPABILITIES_SUPPORTED2_0 \ | |
| 103 | (TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \ | |
| 104 | TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \ | |
| 105 | TPM_TIS_CAP_DATA_TRANSFER_64B | \ | |
| 106 | TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 | \ | |
| 107 | TPM_TIS_INTERRUPTS_SUPPORTED) | |
| 108 | ||
| 109 | #define TPM_TIS_IFACE_ID_INTERFACE_TIS1_3 (0xf) /* TPM 2.0 */ | |
| 110 | #define TPM_TIS_IFACE_ID_INTERFACE_FIFO (0x0) /* TPM 2.0 */ | |
| 111 | #define TPM_TIS_IFACE_ID_INTERFACE_VER_FIFO (0 << 4) /* TPM 2.0 */ | |
| 112 | #define TPM_TIS_IFACE_ID_CAP_5_LOCALITIES (1 << 8) /* TPM 2.0 */ | |
| 113 | #define TPM_TIS_IFACE_ID_CAP_TIS_SUPPORTED (1 << 13) /* TPM 2.0 */ | |
| 114 | #define TPM_TIS_IFACE_ID_INT_SEL_LOCK (1 << 19) /* TPM 2.0 */ | |
| 115 | ||
| 116 | #define TPM_TIS_IFACE_ID_SUPPORTED_FLAGS1_3 \ | |
| 117 | (TPM_TIS_IFACE_ID_INTERFACE_TIS1_3 | \ | |
| 118 | (~0u << 4)/* all of it is don't care */) | |
| 119 | ||
| 120 | /* if backend was a TPM 2.0: */ | |
| 121 | #define TPM_TIS_IFACE_ID_SUPPORTED_FLAGS2_0 \ | |
| 122 | (TPM_TIS_IFACE_ID_INTERFACE_FIFO | \ | |
| 123 | TPM_TIS_IFACE_ID_INTERFACE_VER_FIFO | \ | |
| 124 | TPM_TIS_IFACE_ID_CAP_5_LOCALITIES | \ | |
| 125 | TPM_TIS_IFACE_ID_CAP_TIS_SUPPORTED) | |
| 126 | ||
| 127 | #define TPM_TIS_TPM_DID 0x0001 | |
| 128 | #define TPM_TIS_TPM_VID PCI_VENDOR_ID_IBM | |
| 129 | #define TPM_TIS_TPM_RID 0x0001 | |
| 130 | ||
| 131 | #define TPM_TIS_NO_DATA_BYTE 0xff | |
| 132 | ||
| 133 | ||
| 4ab6cb4c MAL |
134 | REG32(CRB_LOC_STATE, 0x00) |
| 135 | FIELD(CRB_LOC_STATE, tpmEstablished, 0, 1) | |
| 136 | FIELD(CRB_LOC_STATE, locAssigned, 1, 1) | |
| 137 | FIELD(CRB_LOC_STATE, activeLocality, 2, 3) | |
| 138 | FIELD(CRB_LOC_STATE, reserved, 5, 2) | |
| 139 | FIELD(CRB_LOC_STATE, tpmRegValidSts, 7, 1) | |
| 140 | REG32(CRB_LOC_CTRL, 0x08) | |
| 141 | REG32(CRB_LOC_STS, 0x0C) | |
| 142 | FIELD(CRB_LOC_STS, Granted, 0, 1) | |
| 143 | FIELD(CRB_LOC_STS, beenSeized, 1, 1) | |
| 144 | REG32(CRB_INTF_ID, 0x30) | |
| 145 | FIELD(CRB_INTF_ID, InterfaceType, 0, 4) | |
| 146 | FIELD(CRB_INTF_ID, InterfaceVersion, 4, 4) | |
| 147 | FIELD(CRB_INTF_ID, CapLocality, 8, 1) | |
| 148 | FIELD(CRB_INTF_ID, CapCRBIdleBypass, 9, 1) | |
| 149 | FIELD(CRB_INTF_ID, Reserved1, 10, 1) | |
| 150 | FIELD(CRB_INTF_ID, CapDataXferSizeSupport, 11, 2) | |
| 151 | FIELD(CRB_INTF_ID, CapFIFO, 13, 1) | |
| 152 | FIELD(CRB_INTF_ID, CapCRB, 14, 1) | |
| 153 | FIELD(CRB_INTF_ID, CapIFRes, 15, 2) | |
| 154 | FIELD(CRB_INTF_ID, InterfaceSelector, 17, 2) | |
| 155 | FIELD(CRB_INTF_ID, IntfSelLock, 19, 1) | |
| 156 | FIELD(CRB_INTF_ID, Reserved2, 20, 4) | |
| 157 | FIELD(CRB_INTF_ID, RID, 24, 8) | |
| 158 | REG32(CRB_INTF_ID2, 0x34) | |
| 159 | FIELD(CRB_INTF_ID2, VID, 0, 16) | |
| 160 | FIELD(CRB_INTF_ID2, DID, 16, 16) | |
| 161 | REG32(CRB_CTRL_EXT, 0x38) | |
| 162 | REG32(CRB_CTRL_REQ, 0x40) | |
| 163 | REG32(CRB_CTRL_STS, 0x44) | |
| 164 | FIELD(CRB_CTRL_STS, tpmSts, 0, 1) | |
| 165 | FIELD(CRB_CTRL_STS, tpmIdle, 1, 1) | |
| 166 | REG32(CRB_CTRL_CANCEL, 0x48) | |
| 167 | REG32(CRB_CTRL_START, 0x4C) | |
| 168 | REG32(CRB_INT_ENABLED, 0x50) | |
| 169 | REG32(CRB_INT_STS, 0x54) | |
| 170 | REG32(CRB_CTRL_CMD_SIZE, 0x58) | |
| 171 | REG32(CRB_CTRL_CMD_LADDR, 0x5C) | |
| 172 | REG32(CRB_CTRL_CMD_HADDR, 0x60) | |
| 173 | REG32(CRB_CTRL_RSP_SIZE, 0x64) | |
| 174 | REG32(CRB_CTRL_RSP_ADDR, 0x68) | |
| 175 | REG32(CRB_DATA_BUFFER, 0x80) | |
| 176 | ||
| 177 | #define TPM_CRB_ADDR_BASE 0xFED40000 | |
| 178 | #define TPM_CRB_ADDR_SIZE 0x1000 | |
| 179 | #define TPM_CRB_ADDR_CTRL (TPM_CRB_ADDR_BASE + A_CRB_CTRL_REQ) | |
| 180 | #define TPM_CRB_R_MAX R_CRB_DATA_BUFFER | |
| 181 | ||
| 3d779b93 | 182 | #define TPM_LOG_AREA_MINIMUM_SIZE (64 * KiB) |
| 711b20b4 SB |
183 | |
| 184 | #define TPM_TCPA_ACPI_CLASS_CLIENT 0 | |
| 185 | #define TPM_TCPA_ACPI_CLASS_SERVER 1 | |
| 186 | ||
| 5cb18b3d SB |
187 | #define TPM2_ACPI_CLASS_CLIENT 0 |
| 188 | #define TPM2_ACPI_CLASS_SERVER 1 | |
| 189 | ||
| 190 | #define TPM2_START_METHOD_MMIO 6 | |
| 4ab6cb4c | 191 | #define TPM2_START_METHOD_CRB 7 |
| 5cb18b3d | 192 | |
| 3b97c01e SB |
193 | /* |
| 194 | * Physical Presence Interface | |
| 195 | */ | |
| 196 | #define TPM_PPI_ADDR_SIZE 0x400 | |
| 197 | #define TPM_PPI_ADDR_BASE 0xFED45000 | |
| 198 | ||
| 0fe24669 SB |
199 | #define TPM_PPI_VERSION_NONE 0 |
| 200 | #define TPM_PPI_VERSION_1_30 1 | |
| 201 | ||
| ac6dd31e SB |
202 | /* whether function is blocked by BIOS settings; bits 0, 1, 2 */ |
| 203 | #define TPM_PPI_FUNC_NOT_IMPLEMENTED (0 << 0) | |
| 204 | #define TPM_PPI_FUNC_BIOS_ONLY (1 << 0) | |
| 205 | #define TPM_PPI_FUNC_BLOCKED (2 << 0) | |
| 206 | #define TPM_PPI_FUNC_ALLOWED_USR_REQ (3 << 0) | |
| 207 | #define TPM_PPI_FUNC_ALLOWED_USR_NOT_REQ (4 << 0) | |
| 208 | #define TPM_PPI_FUNC_MASK (7 << 0) | |
| 209 | ||
| 210 | void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev); | |
| 211 | ||
| 711b20b4 | 212 | #endif /* HW_ACPI_TPM_H */ |