[qemu.git] / hw / arm / xlnx-zynqmp.c

/*
 * Xilinx Zynq MPSoC emulation
 *
 * Copyright (C) 2015 Xilinx Inc
 * Written by Peter Crosthwaite <[email protected]>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 * for more details.
 */

#include "qemu/osdep.h"
#include "hw/arm/xlnx-zynqmp.h"
#include "hw/intc/arm_gic_common.h"
#include "exec/address-spaces.h"

#define GIC_NUM_SPI_INTR 160

#define ARM_PHYS_TIMER_PPI  30
#define ARM_VIRT_TIMER_PPI  27

#define GIC_BASE_ADDR       0xf9000000
#define GIC_DIST_ADDR       0xf9010000
#define GIC_CPU_ADDR        0xf9020000

#define SATA_INTR           133
#define SATA_ADDR           0xFD0C0000
#define SATA_NUM_PORTS      2

static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
    0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
};

static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
    57, 59, 61, 63,
};

static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
    0xFF000000, 0xFF010000,
};

static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
    21, 22,
};

static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
    0xFF160000, 0xFF170000,
};

static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
    48, 49,
};

typedef struct XlnxZynqMPGICRegion {
    int region_index;
    uint32_t address;
} XlnxZynqMPGICRegion;

static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
    { .region_index = 0, .address = GIC_DIST_ADDR, },
    { .region_index = 1, .address = GIC_CPU_ADDR,  },
};

static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
{
    return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
}

static void xlnx_zynqmp_init(Object *obj)
{
    XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
    int i;

    for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
        object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
                          "cortex-a53-" TYPE_ARM_CPU);
        object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]),
                                  &error_abort);
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
        object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
                          "cortex-r5-" TYPE_ARM_CPU);
        object_property_add_child(obj, "rpu-cpu[*]", OBJECT(&s->rpu_cpu[i]),
                                  &error_abort);
    }

    object_property_add_link(obj, "ddr-ram", TYPE_MEMORY_REGION,
                             (Object **)&s->ddr_ram,
                             qdev_prop_allow_set_link_before_realize,
                             OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);

    object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
    qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());

    for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
        object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
        qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
        object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
        qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
    }

    object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
    qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());

    for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
        object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]),
                          TYPE_SYSBUS_SDHCI);
        qdev_set_parent_bus(DEVICE(&s->sdhci[i]),
                            sysbus_get_default());
    }
}

static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
{
    XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
    MemoryRegion *system_memory = get_system_memory();
    uint8_t i;
    uint64_t ram_size;
    const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
    ram_addr_t ddr_low_size, ddr_high_size;
    qemu_irq gic_spi[GIC_NUM_SPI_INTR];
    Error *err = NULL;

    ram_size = memory_region_size(s->ddr_ram);

    /* Create the DDR Memory Regions. User friendly checks should happen at
     * the board level
     */
    if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
        /* The RAM size is above the maximum available for the low DDR.
         * Create the high DDR memory region as well.
         */
        assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
        ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
        ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;

        memory_region_init_alias(&s->ddr_ram_high, NULL,
                                 "ddr-ram-high", s->ddr_ram,
                                  ddr_low_size, ddr_high_size);
        memory_region_add_subregion(get_system_memory(),
                                    XLNX_ZYNQMP_HIGH_RAM_START,
                                    &s->ddr_ram_high);
    } else {
        /* RAM must be non-zero */
        assert(ram_size);
        ddr_low_size = ram_size;
    }

    memory_region_init_alias(&s->ddr_ram_low, NULL,
                             "ddr-ram-low", s->ddr_ram,
                              0, ddr_low_size);
    memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);

    /* Create the four OCM banks */
    for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
        char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);

        memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
                               XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
        vmstate_register_ram_global(&s->ocm_ram[i]);
        memory_region_add_subregion(get_system_memory(),
                                    XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
                                        i * XLNX_ZYNQMP_OCM_RAM_SIZE,
                                    &s->ocm_ram[i]);

        g_free(ocm_name);
    }

    qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
    qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
    qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS);
    object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
    for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
        SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
        const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
        MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
        uint32_t addr = r->address;
        int j;

        sysbus_mmio_map(gic, r->region_index, addr);

        for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
            MemoryRegion *alias = &s->gic_mr[i][j];

            addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
            memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
                                     0, XLNX_ZYNQMP_GIC_REGION_SIZE);
            memory_region_add_subregion(system_memory, addr, alias);
        }
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
        qemu_irq irq;
        char *name;

        object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
                                "psci-conduit", &error_abort);

        name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
        if (strcmp(name, boot_cpu)) {
            /* Secondary CPUs start in PSCI powered-down state */
            object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
                                     "start-powered-off", &error_abort);
        } else {
            s->boot_cpu_ptr = &s->apu_cpu[i];
        }
        g_free(name);

        object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
                                "reset-cbar", &error_abort);
        object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
                                 &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }

        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
                           qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
                                            ARM_CPU_IRQ));
        irq = qdev_get_gpio_in(DEVICE(&s->gic),
                               arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
        qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq);
        irq = qdev_get_gpio_in(DEVICE(&s->gic),
                               arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
        qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq);
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
        char *name;

        name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
        if (strcmp(name, boot_cpu)) {
            /* Secondary CPUs start in PSCI powered-down state */
            object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
                                     "start-powered-off", &error_abort);
        } else {
            s->boot_cpu_ptr = &s->rpu_cpu[i];
        }
        g_free(name);

        object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
                                 &error_abort);
        object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
                                 &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
    }

    if (!s->boot_cpu_ptr) {
        error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
        return;
    }

    for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
        gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
        NICInfo *nd = &nd_table[i];

        if (nd->used) {
            qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
            qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
        }
        object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
                           gic_spi[gem_intr[i]]);
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
        object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
                           gic_spi[uart_intr[i]]);
    }

    object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
                            &error_abort);
    object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);

    for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
        object_property_set_bool(OBJECT(&s->sdhci[i]), true,
                                 "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
                        sdhci_addr[i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
                           gic_spi[sdhci_intr[i]]);
    }
}

static Property xlnx_zynqmp_props[] = {
    DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
    DEFINE_PROP_END_OF_LIST()
};

static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->props = xlnx_zynqmp_props;
    dc->realize = xlnx_zynqmp_realize;

    /*
     * Reason: creates an ARM CPU, thus use after free(), see
     * arm_cpu_class_init()
     */
    dc->cannot_destroy_with_object_finalize_yet = true;
}

static const TypeInfo xlnx_zynqmp_type_info = {
    .name = TYPE_XLNX_ZYNQMP,
    .parent = TYPE_DEVICE,
    .instance_size = sizeof(XlnxZynqMPState),
    .instance_init = xlnx_zynqmp_init,
    .class_init = xlnx_zynqmp_class_init,
};

static void xlnx_zynqmp_register_types(void)
{
    type_register_static(&xlnx_zynqmp_type_info);
}

type_init(xlnx_zynqmp_register_types)
Commit	Line	Data
f0a902f7 PC	1	/*
	2	* Xilinx Zynq MPSoC emulation
	3	*
	4	* Copyright (C) 2015 Xilinx Inc
	5	* Written by Peter Crosthwaite <[email protected]>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	15	* for more details.
	16	*/
	17
12b16722	18	#include "qemu/osdep.h"
f0a902f7	19	#include "hw/arm/xlnx-zynqmp.h"
bf4cb109	20	#include "hw/intc/arm_gic_common.h"
7729e1f4 PC	21	#include "exec/address-spaces.h"
	22
	23	#define GIC_NUM_SPI_INTR 160
	24
bf4cb109 PC	25	#define ARM_PHYS_TIMER_PPI 30
	26	#define ARM_VIRT_TIMER_PPI 27
	27
7729e1f4 PC	28	#define GIC_BASE_ADDR 0xf9000000
	29	#define GIC_DIST_ADDR 0xf9010000
	30	#define GIC_CPU_ADDR 0xf9020000
	31
6fdf3282 AF	32	#define SATA_INTR 133
	33	#define SATA_ADDR 0xFD0C0000
	34	#define SATA_NUM_PORTS 2
	35
14ca2e46 PC	36	static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
	37	0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
	38	};
	39
	40	static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
	41	57, 59, 61, 63,
	42	};
	43
3bade2a9 PC	44	static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
	45	0xFF000000, 0xFF010000,
	46	};
	47
	48	static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
	49	21, 22,
	50	};
	51
33108e9f SPB	52	static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
	53	0xFF160000, 0xFF170000,
	54	};
	55
	56	static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
	57	48, 49,
	58	};
	59
7729e1f4 PC	60	typedef struct XlnxZynqMPGICRegion {
	61	int region_index;
	62	uint32_t address;
	63	} XlnxZynqMPGICRegion;
	64
	65	static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
	66	{ .region_index = 0, .address = GIC_DIST_ADDR, },
	67	{ .region_index = 1, .address = GIC_CPU_ADDR, },
	68	};
f0a902f7	69
bf4cb109 PC	70	static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
	71	{
	72	return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
	73	}
	74
f0a902f7 PC	75	static void xlnx_zynqmp_init(Object *obj)
	76	{
	77	XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
	78	int i;
	79
2e5577bc PC	80	for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
2e5577bc PC	81	object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
f0a902f7	82	"cortex-a53-" TYPE_ARM_CPU);
2e5577bc	83	object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]),
f0a902f7 PC	84	&error_abort);
f0a902f7 PC	85	}
7729e1f4	86
b58850e7 PC	87	for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
	88	object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
	89	"cortex-r5-" TYPE_ARM_CPU);
	90	object_property_add_child(obj, "rpu-cpu[*]", OBJECT(&s->rpu_cpu[i]),
	91	&error_abort);
	92	}
	93
dc3b89ef AF	94	object_property_add_link(obj, "ddr-ram", TYPE_MEMORY_REGION,
	95	(Object **)&s->ddr_ram,
	96	qdev_prop_allow_set_link_before_realize,
	97	OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
	98
7729e1f4 PC	99	object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
7729e1f4 PC	100	qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
14ca2e46 PC	101
	102	for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
	103	object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
	104	qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
	105	}
3bade2a9 PC	106
	107	for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
	108	object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
	109	qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
	110	}
6fdf3282 AF	111
	112	object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
	113	qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
33108e9f SPB	114
	115	for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
	116	object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]),
	117	TYPE_SYSBUS_SDHCI);
	118	qdev_set_parent_bus(DEVICE(&s->sdhci[i]),
	119	sysbus_get_default());
	120	}
f0a902f7 PC	121	}
	122
	123	static void xlnx_zynqmp_realize(DeviceState dev, Error *errp)
	124	{
	125	XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
7729e1f4	126	MemoryRegion *system_memory = get_system_memory();
f0a902f7	127	uint8_t i;
dc3b89ef	128	uint64_t ram_size;
6396a193	129	const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
dc3b89ef	130	ram_addr_t ddr_low_size, ddr_high_size;
14ca2e46	131	qemu_irq gic_spi[GIC_NUM_SPI_INTR];
f0a902f7 PC	132	Error *err = NULL;
f0a902f7 PC	133
dc3b89ef AF	134	ram_size = memory_region_size(s->ddr_ram);
	135
	136	/* Create the DDR Memory Regions. User friendly checks should happen at
	137	* the board level
	138	*/
	139	if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
	140	/* The RAM size is above the maximum available for the low DDR.
	141	* Create the high DDR memory region as well.
	142	*/
	143	assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
	144	ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
	145	ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
	146
	147	memory_region_init_alias(&s->ddr_ram_high, NULL,
	148	"ddr-ram-high", s->ddr_ram,
	149	ddr_low_size, ddr_high_size);
	150	memory_region_add_subregion(get_system_memory(),
	151	XLNX_ZYNQMP_HIGH_RAM_START,
	152	&s->ddr_ram_high);
	153	} else {
	154	/* RAM must be non-zero */
	155	assert(ram_size);
	156	ddr_low_size = ram_size;
	157	}
	158
	159	memory_region_init_alias(&s->ddr_ram_low, NULL,
	160	"ddr-ram-low", s->ddr_ram,
	161	0, ddr_low_size);
	162	memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);
	163
6675d719 AF	164	/* Create the four OCM banks */
	165	for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
	166	char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);
	167
	168	memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
f8ed85ac	169	XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
6675d719 AF	170	vmstate_register_ram_global(&s->ocm_ram[i]);
	171	memory_region_add_subregion(get_system_memory(),
	172	XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
	173	i * XLNX_ZYNQMP_OCM_RAM_SIZE,
	174	&s->ocm_ram[i]);
	175
	176	g_free(ocm_name);
	177	}
	178
7729e1f4 PC	179	qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
7729e1f4 PC	180	qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
2e5577bc	181	qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS);
7729e1f4 PC	182	object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
7729e1f4 PC	183	if (err) {
24cfc8dc	184	error_propagate(errp, err);
7729e1f4 PC	185	return;
	186	}
	187	assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
	188	for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
	189	SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
	190	const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
	191	MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
	192	uint32_t addr = r->address;
	193	int j;
	194
	195	sysbus_mmio_map(gic, r->region_index, addr);
	196
	197	for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
	198	MemoryRegion *alias = &s->gic_mr[i][j];
	199
	200	addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
	201	memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
	202	0, XLNX_ZYNQMP_GIC_REGION_SIZE);
	203	memory_region_add_subregion(system_memory, addr, alias);
	204	}
	205	}
	206
2e5577bc	207	for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
bf4cb109	208	qemu_irq irq;
6396a193	209	char *name;
bf4cb109	210
2e5577bc	211	object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
f0a902f7	212	"psci-conduit", &error_abort);
6396a193 PC	213
	214	name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
	215	if (strcmp(name, boot_cpu)) {
f0a902f7	216	/* Secondary CPUs start in PSCI powered-down state */
2e5577bc	217	object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
f0a902f7	218	"start-powered-off", &error_abort);
6396a193 PC	219	} else {
6396a193 PC	220	s->boot_cpu_ptr = &s->apu_cpu[i];
f0a902f7	221	}
5348c62c	222	g_free(name);
f0a902f7	223
2e5577bc	224	object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
e1292517	225	"reset-cbar", &error_abort);
2e5577bc PC	226	object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
2e5577bc PC	227	&err);
f0a902f7	228	if (err) {
24cfc8dc	229	error_propagate(errp, err);
f0a902f7 PC	230	return;
f0a902f7 PC	231	}
7729e1f4 PC	232
7729e1f4 PC	233	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
2e5577bc PC	234	qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
2e5577bc PC	235	ARM_CPU_IRQ));
bf4cb109 PC	236	irq = qdev_get_gpio_in(DEVICE(&s->gic),
bf4cb109 PC	237	arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
2e5577bc	238	qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq);
bf4cb109 PC	239	irq = qdev_get_gpio_in(DEVICE(&s->gic),
bf4cb109 PC	240	arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
2e5577bc	241	qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq);
f0a902f7	242	}
14ca2e46	243
b58850e7 PC	244	for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
	245	char *name;
	246
	247	name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
	248	if (strcmp(name, boot_cpu)) {
	249	/* Secondary CPUs start in PSCI powered-down state */
	250	object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
	251	"start-powered-off", &error_abort);
	252	} else {
	253	s->boot_cpu_ptr = &s->rpu_cpu[i];
	254	}
5348c62c	255	g_free(name);
b58850e7 PC	256
b58850e7 PC	257	object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
e1292517	258	&error_abort);
b58850e7 PC	259	object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
	260	&err);
	261	if (err) {
24cfc8dc	262	error_propagate(errp, err);
b58850e7 PC	263	return;
	264	}
	265	}
	266
6396a193	267	if (!s->boot_cpu_ptr) {
9af9e0fe	268	error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
6396a193 PC	269	return;
	270	}
	271
14ca2e46 PC	272	for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
	273	gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
	274	}
	275
	276	for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
	277	NICInfo *nd = &nd_table[i];
	278
	279	if (nd->used) {
	280	qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
	281	qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
	282	}
	283	object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
	284	if (err) {
24cfc8dc	285	error_propagate(errp, err);
14ca2e46 PC	286	return;
	287	}
	288	sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
	289	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
	290	gic_spi[gem_intr[i]]);
	291	}
3bade2a9 PC	292
	293	for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
	294	object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
	295	if (err) {
24cfc8dc	296	error_propagate(errp, err);
3bade2a9 PC	297	return;
	298	}
	299	sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
	300	sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
	301	gic_spi[uart_intr[i]]);
	302	}
6fdf3282 AF	303
	304	object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
	305	&error_abort);
	306	object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
	307	if (err) {
	308	error_propagate(errp, err);
	309	return;
	310	}
	311
	312	sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
	313	sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
33108e9f SPB	314
	315	for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
	316	object_property_set_bool(OBJECT(&s->sdhci[i]), true,
	317	"realized", &err);
	318	if (err) {
	319	error_propagate(errp, err);
	320	return;
	321	}
	322	sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
	323	sdhci_addr[i]);
	324	sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
	325	gic_spi[sdhci_intr[i]]);
	326	}
f0a902f7 PC	327	}
f0a902f7 PC	328
6396a193 PC	329	static Property xlnx_zynqmp_props[] = {
	330	DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
	331	DEFINE_PROP_END_OF_LIST()
	332	};
	333
f0a902f7 PC	334	static void xlnx_zynqmp_class_init(ObjectClass oc, void data)
	335	{
	336	DeviceClass *dc = DEVICE_CLASS(oc);
	337
6396a193	338	dc->props = xlnx_zynqmp_props;
f0a902f7	339	dc->realize = xlnx_zynqmp_realize;
4c315c27 MA	340
	341	/*
	342	* Reason: creates an ARM CPU, thus use after free(), see
	343	* arm_cpu_class_init()
	344	*/
	345	dc->cannot_destroy_with_object_finalize_yet = true;
f0a902f7 PC	346	}
	347
	348	static const TypeInfo xlnx_zynqmp_type_info = {
	349	.name = TYPE_XLNX_ZYNQMP,
	350	.parent = TYPE_DEVICE,
	351	.instance_size = sizeof(XlnxZynqMPState),
	352	.instance_init = xlnx_zynqmp_init,
	353	.class_init = xlnx_zynqmp_class_init,
	354	};
	355
	356	static void xlnx_zynqmp_register_types(void)
	357	{
	358	type_register_static(&xlnx_zynqmp_type_info);
	359	}
	360
	361	type_init(xlnx_zynqmp_register_types)