[qemu.git] / hw / arm / xilinx_zynq.c

/*
 * Xilinx Zynq Baseboard System emulation.
 *
 * Copyright (c) 2010 Xilinx.
 * Copyright (c) 2012 Peter A.G. Crosthwaite ([email protected])
 * Copyright (c) 2012 Petalogix Pty Ltd.
 * Written by Haibing Ma
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "hw/arm/arm.h"
#include "net/net.h"
#include "exec/address-spaces.h"
#include "sysemu/sysemu.h"
#include "hw/boards.h"
#include "hw/block/flash.h"
#include "sysemu/block-backend.h"
#include "hw/loader.h"
#include "hw/misc/zynq-xadc.h"
#include "hw/ssi.h"
#include "qemu/error-report.h"

#define NUM_SPI_FLASHES 4
#define NUM_QSPI_FLASHES 2
#define NUM_QSPI_BUSSES 2

#define FLASH_SIZE (64 * 1024 * 1024)
#define FLASH_SECTOR_SIZE (128 * 1024)

#define IRQ_OFFSET 32 /* pic interrupts start from index 32 */

#define MPCORE_PERIPHBASE 0xF8F00000
#define ZYNQ_BOARD_MIDR 0x413FC090

static const int dma_irqs[8] = {
    46, 47, 48, 49, 72, 73, 74, 75
};

#define BOARD_SETUP_ADDR        0x100

#define SLCR_LOCK_OFFSET        0x004
#define SLCR_UNLOCK_OFFSET      0x008
#define SLCR_ARM_PLL_OFFSET     0x100

#define SLCR_XILINX_UNLOCK_KEY  0xdf0d
#define SLCR_XILINX_LOCK_KEY    0x767b

#define ARMV7_IMM16(x) (extract32((x),  0, 12) | \
                        extract32((x), 12,  4) << 16)

/* Write immediate val to address r0 + addr. r0 should contain base offset
 * of the SLCR block. Clobbers r1.
 */

#define SLCR_WRITE(addr, val) \
    0xe3001000 + ARMV7_IMM16(extract32((val),  0, 16)), /* movw r1 ... */ \
    0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \
    0xe5801000 + (addr)

static void zynq_write_board_setup(ARMCPU *cpu,
                                   const struct arm_boot_info *info)
{
    int n;
    uint32_t board_setup_blob[] = {
        0xe3a004f8, /* mov r0, #0xf8000000 */
        SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY),
        SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008),
        SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY),
        0xe12fff1e, /* bx lr */
    };
    for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {
        board_setup_blob[n] = tswap32(board_setup_blob[n]);
    }
    rom_add_blob_fixed("board-setup", board_setup_blob,
                       sizeof(board_setup_blob), BOARD_SETUP_ADDR);
}

static struct arm_boot_info zynq_binfo = {};

static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
{
    DeviceState *dev;
    SysBusDevice *s;

    dev = qdev_create(NULL, "cadence_gem");
    if (nd->used) {
        qemu_check_nic_model(nd, "cadence_gem");
        qdev_set_nic_properties(dev, nd);
    }
    qdev_init_nofail(dev);
    s = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(s, 0, base);
    sysbus_connect_irq(s, 0, irq);
}

static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
                                         bool is_qspi)
{
    DeviceState *dev;
    SysBusDevice *busdev;
    SSIBus *spi;
    DeviceState *flash_dev;
    int i, j;
    int num_busses =  is_qspi ? NUM_QSPI_BUSSES : 1;
    int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;

    dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
    qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
    qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
    qdev_prop_set_uint8(dev, "num-busses", num_busses);
    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(busdev, 0, base_addr);
    if (is_qspi) {
        sysbus_mmio_map(busdev, 1, 0xFC000000);
    }
    sysbus_connect_irq(busdev, 0, irq);

    for (i = 0; i < num_busses; ++i) {
        char bus_name[16];
        qemu_irq cs_line;

        snprintf(bus_name, 16, "spi%d", i);
        spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);

        for (j = 0; j < num_ss; ++j) {
            flash_dev = ssi_create_slave(spi, "n25q128");

            cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
            sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);
        }
    }

}

static void zynq_init(MachineState *machine)
{
    ram_addr_t ram_size = machine->ram_size;
    const char *cpu_model = machine->cpu_model;
    const char *kernel_filename = machine->kernel_filename;
    const char *kernel_cmdline = machine->kernel_cmdline;
    const char *initrd_filename = machine->initrd_filename;
    ObjectClass *cpu_oc;
    ARMCPU *cpu;
    MemoryRegion *address_space_mem = get_system_memory();
    MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
    MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
    DeviceState *dev;
    SysBusDevice *busdev;
    qemu_irq pic[64];
    int n;

    if (!cpu_model) {
        cpu_model = "cortex-a9";
    }
    cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);

    cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc)));

    /* By default A9 CPUs have EL3 enabled.  This board does not
     * currently support EL3 so the CPU EL3 property is disabled before
     * realization.
     */
    if (object_property_find(OBJECT(cpu), "has_el3", NULL)) {
        object_property_set_bool(OBJECT(cpu), false, "has_el3", &error_fatal);
    }

    object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr",
                            &error_fatal);
    object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar",
                            &error_fatal);
    object_property_set_bool(OBJECT(cpu), true, "realized", &error_fatal);

    /* max 2GB ram */
    if (ram_size > 0x80000000) {
        ram_size = 0x80000000;
    }

    /* DDR remapped to address zero.  */
    memory_region_allocate_system_memory(ext_ram, NULL, "zynq.ext_ram",
                                         ram_size);
    memory_region_add_subregion(address_space_mem, 0, ext_ram);

    /* 256K of on-chip memory */
    memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 << 10,
                           &error_fatal);
    vmstate_register_ram_global(ocm_ram);
    memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);

    DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);

    /* AMD */
    pflash_cfi02_register(0xe2000000, NULL, "zynq.pflash", FLASH_SIZE,
                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
                          FLASH_SECTOR_SIZE,
                          FLASH_SIZE/FLASH_SECTOR_SIZE, 1,
                          1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
                              0);

    dev = qdev_create(NULL, "xilinx,zynq_slcr");
    qdev_init_nofail(dev);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000);

    dev = qdev_create(NULL, "a9mpcore_priv");
    qdev_prop_set_uint32(dev, "num-cpu", 1);
    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
    sysbus_connect_irq(busdev, 0,
                       qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));

    for (n = 0; n < 64; n++) {
        pic[n] = qdev_get_gpio_in(dev, n);
    }

    zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false);
    zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false);
    zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true);

    sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]);
    sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]);

    sysbus_create_simple("cadence_uart", 0xE0000000, pic[59-IRQ_OFFSET]);
    sysbus_create_simple("cadence_uart", 0xE0001000, pic[82-IRQ_OFFSET]);

    sysbus_create_varargs("cadence_ttc", 0xF8001000,
            pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
    sysbus_create_varargs("cadence_ttc", 0xF8002000,
            pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL);

    gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]);
    gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]);

    dev = qdev_create(NULL, "generic-sdhci");
    qdev_init_nofail(dev);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0100000);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[56-IRQ_OFFSET]);

    dev = qdev_create(NULL, "generic-sdhci");
    qdev_init_nofail(dev);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0101000);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[79-IRQ_OFFSET]);

    dev = qdev_create(NULL, TYPE_ZYNQ_XADC);
    qdev_init_nofail(dev);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);

    dev = qdev_create(NULL, "pl330");
    qdev_prop_set_uint8(dev, "num_chnls",  8);
    qdev_prop_set_uint8(dev, "num_periph_req",  4);
    qdev_prop_set_uint8(dev, "num_events",  16);

    qdev_prop_set_uint8(dev, "data_width",  64);
    qdev_prop_set_uint8(dev, "wr_cap",  8);
    qdev_prop_set_uint8(dev, "wr_q_dep",  16);
    qdev_prop_set_uint8(dev, "rd_cap",  8);
    qdev_prop_set_uint8(dev, "rd_q_dep",  16);
    qdev_prop_set_uint16(dev, "data_buffer_dep",  256);

    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(busdev, 0, 0xF8003000);
    sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */
    for (n = 0; n < 8; ++n) { /* event irqs */
        sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
    }

    zynq_binfo.ram_size = ram_size;
    zynq_binfo.kernel_filename = kernel_filename;
    zynq_binfo.kernel_cmdline = kernel_cmdline;
    zynq_binfo.initrd_filename = initrd_filename;
    zynq_binfo.nb_cpus = 1;
    zynq_binfo.board_id = 0xd32;
    zynq_binfo.loader_start = 0;
    zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR;
    zynq_binfo.write_board_setup = zynq_write_board_setup;

    arm_load_kernel(ARM_CPU(first_cpu), &zynq_binfo);
}

static void zynq_machine_init(MachineClass *mc)
{
    mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
    mc->init = zynq_init;
    mc->block_default_type = IF_SCSI;
    mc->max_cpus = 1;
    mc->no_sdcard = 1;
}

DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init)
Commit	Line	Data
e3260506 PC	1	/*
	2	* Xilinx Zynq Baseboard System emulation.
	3	*
	4	* Copyright (c) 2010 Xilinx.
	5	* Copyright (c) 2012 Peter A.G. Crosthwaite ([email protected])
	6	* Copyright (c) 2012 Petalogix Pty Ltd.
	7	* Written by Haibing Ma
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version
	12	* 2 of the License, or (at your option) any later version.
	13	*
	14	* You should have received a copy of the GNU General Public License along
	15	* with this program; if not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
12b16722	18	#include "qemu/osdep.h"
83c9f4ca	19	#include "hw/sysbus.h"
bd2be150	20	#include "hw/arm/arm.h"
1422e32d	21	#include "net/net.h"
022c62cb	22	#include "exec/address-spaces.h"
9c17d615	23	#include "sysemu/sysemu.h"
83c9f4ca	24	#include "hw/boards.h"
0d09e41a	25	#include "hw/block/flash.h"
fa1d36df	26	#include "sysemu/block-backend.h"
83c9f4ca	27	#include "hw/loader.h"
74fcbd22	28	#include "hw/misc/zynq-xadc.h"
83c9f4ca	29	#include "hw/ssi.h"
d8bbdcf8	30	#include "qemu/error-report.h"
559d489f PC	31
559d489f PC	32	#define NUM_SPI_FLASHES 4
7b482bcf PC	33	#define NUM_QSPI_FLASHES 2
7b482bcf PC	34	#define NUM_QSPI_BUSSES 2
e3260506 PC	35
	36	#define FLASH_SIZE (64 * 1024 * 1024)
	37	#define FLASH_SECTOR_SIZE (128 * 1024)
	38
	39	#define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
	40
c2577128	41	#define MPCORE_PERIPHBASE 0xF8F00000
b48adc0d	42	#define ZYNQ_BOARD_MIDR 0x413FC090
c2577128	43
7451afb6 PC	44	static const int dma_irqs[8] = {
	45	46, 47, 48, 49, 72, 73, 74, 75
	46	};
	47
c3a9a689 PC	48	#define BOARD_SETUP_ADDR 0x100
	49
	50	#define SLCR_LOCK_OFFSET 0x004
	51	#define SLCR_UNLOCK_OFFSET 0x008
	52	#define SLCR_ARM_PLL_OFFSET 0x100
	53
	54	#define SLCR_XILINX_UNLOCK_KEY 0xdf0d
	55	#define SLCR_XILINX_LOCK_KEY 0x767b
	56
	57	#define ARMV7_IMM16(x) (extract32((x), 0, 12) \| \
	58	extract32((x), 12, 4) << 16)
	59
	60	/* Write immediate val to address r0 + addr. r0 should contain base offset
	61	* of the SLCR block. Clobbers r1.
	62	*/
	63
	64	#define SLCR_WRITE(addr, val) \
	65	0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), /* movw r1 ... */ \
	66	0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \
	67	0xe5801000 + (addr)
	68
	69	static void zynq_write_board_setup(ARMCPU *cpu,
	70	const struct arm_boot_info *info)
	71	{
	72	int n;
	73	uint32_t board_setup_blob[] = {
	74	0xe3a004f8, /* mov r0, #0xf8000000 */
	75	SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY),
	76	SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008),
	77	SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY),
	78	0xe12fff1e, /* bx lr */
	79	};
	80	for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {
	81	board_setup_blob[n] = tswap32(board_setup_blob[n]);
	82	}
	83	rom_add_blob_fixed("board-setup", board_setup_blob,
	84	sizeof(board_setup_blob), BOARD_SETUP_ADDR);
	85	}
	86
e3260506 PC	87	static struct arm_boot_info zynq_binfo = {};
	88
	89	static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
	90	{
	91	DeviceState *dev;
	92	SysBusDevice *s;
	93
e3260506	94	dev = qdev_create(NULL, "cadence_gem");
7fcd57e8 PC	95	if (nd->used) {
	96	qemu_check_nic_model(nd, "cadence_gem");
	97	qdev_set_nic_properties(dev, nd);
	98	}
e3260506	99	qdev_init_nofail(dev);
1356b98d	100	s = SYS_BUS_DEVICE(dev);
e3260506 PC	101	sysbus_mmio_map(s, 0, base);
	102	sysbus_connect_irq(s, 0, irq);
	103	}
	104
7b482bcf PC	105	static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
7b482bcf PC	106	bool is_qspi)
559d489f PC	107	{
	108	DeviceState *dev;
	109	SysBusDevice *busdev;
	110	SSIBus *spi;
79f5d67e	111	DeviceState *flash_dev;
7b482bcf PC	112	int i, j;
	113	int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1;
	114	int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;
559d489f	115
6b91f015	116	dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
7b482bcf PC	117	qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
	118	qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
	119	qdev_prop_set_uint8(dev, "num-busses", num_busses);
559d489f	120	qdev_init_nofail(dev);
1356b98d	121	busdev = SYS_BUS_DEVICE(dev);
559d489f	122	sysbus_mmio_map(busdev, 0, base_addr);
7b482bcf PC	123	if (is_qspi) {
	124	sysbus_mmio_map(busdev, 1, 0xFC000000);
	125	}
559d489f PC	126	sysbus_connect_irq(busdev, 0, irq);
559d489f PC	127
7b482bcf PC	128	for (i = 0; i < num_busses; ++i) {
7b482bcf PC	129	char bus_name[16];
559d489f PC	130	qemu_irq cs_line;
559d489f PC	131
7b482bcf PC	132	snprintf(bus_name, 16, "spi%d", i);
	133	spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);
	134
	135	for (j = 0; j < num_ss; ++j) {
f1922e36	136	flash_dev = ssi_create_slave(spi, "n25q128");
559d489f	137
de77914e	138	cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
7b482bcf PC	139	sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);
7b482bcf PC	140	}
559d489f PC	141	}
	142
	143	}
	144
3ef96221	145	static void zynq_init(MachineState *machine)
e3260506	146	{
3ef96221 MA	147	ram_addr_t ram_size = machine->ram_size;
	148	const char *cpu_model = machine->cpu_model;
	149	const char *kernel_filename = machine->kernel_filename;
	150	const char *kernel_cmdline = machine->kernel_cmdline;
	151	const char *initrd_filename = machine->initrd_filename;
d8bbdcf8	152	ObjectClass *cpu_oc;
17c2f0bf	153	ARMCPU *cpu;
e3260506 PC	154	MemoryRegion *address_space_mem = get_system_memory();
	155	MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
	156	MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
	157	DeviceState *dev;
	158	SysBusDevice *busdev;
e3260506	159	qemu_irq pic[64];
e3260506	160	int n;
e3260506 PC	161
	162	if (!cpu_model) {
	163	cpu_model = "cortex-a9";
	164	}
d8bbdcf8	165	cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
e3260506	166
d8bbdcf8 PC	167	cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc)));
d8bbdcf8 PC	168
61e2f352 GB	169	/* By default A9 CPUs have EL3 enabled. This board does not
	170	* currently support EL3 so the CPU EL3 property is disabled before
	171	* realization.
	172	*/
	173	if (object_property_find(OBJECT(cpu), "has_el3", NULL)) {
007b0657	174	object_property_set_bool(OBJECT(cpu), false, "has_el3", &error_fatal);
b48adc0d AF	175	}
b48adc0d AF	176
007b0657 MA	177	object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr",
	178	&error_fatal);
	179	object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar",
	180	&error_fatal);
	181	object_property_set_bool(OBJECT(cpu), true, "realized", &error_fatal);
e3260506 PC	182
	183	/* max 2GB ram */
	184	if (ram_size > 0x80000000) {
	185	ram_size = 0x80000000;
	186	}
	187
	188	/* DDR remapped to address zero. */
c8623c02 DM	189	memory_region_allocate_system_memory(ext_ram, NULL, "zynq.ext_ram",
c8623c02 DM	190	ram_size);
e3260506 PC	191	memory_region_add_subregion(address_space_mem, 0, ext_ram);
	192
	193	/* 256K of on-chip memory */
49946538	194	memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 << 10,
f8ed85ac	195	&error_fatal);
e3260506 PC	196	vmstate_register_ram_global(ocm_ram);
	197	memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);
	198
	199	DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
	200
	201	/* AMD */
	202	pflash_cfi02_register(0xe2000000, NULL, "zynq.pflash", FLASH_SIZE,
4be74634	203	dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
fa1d36df	204	FLASH_SECTOR_SIZE,
e3260506 PC	205	FLASH_SIZE/FLASH_SECTOR_SIZE, 1,
	206	1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
	207	0);
	208
	209	dev = qdev_create(NULL, "xilinx,zynq_slcr");
	210	qdev_init_nofail(dev);
1356b98d	211	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000);
e3260506 PC	212
	213	dev = qdev_create(NULL, "a9mpcore_priv");
	214	qdev_prop_set_uint32(dev, "num-cpu", 1);
	215	qdev_init_nofail(dev);
1356b98d	216	busdev = SYS_BUS_DEVICE(dev);
c2577128	217	sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
e4a6540d PM	218	sysbus_connect_irq(busdev, 0,
e4a6540d PM	219	qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
e3260506 PC	220
	221	for (n = 0; n < 64; n++) {
	222	pic[n] = qdev_get_gpio_in(dev, n);
	223	}
	224
7b482bcf PC	225	zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false);
	226	zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false);
	227	zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true);
559d489f	228
892776ce	229	sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]);
70ef6a5b	230	sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]);
892776ce	231
e3260506 PC	232	sysbus_create_simple("cadence_uart", 0xE0000000, pic[59-IRQ_OFFSET]);
	233	sysbus_create_simple("cadence_uart", 0xE0001000, pic[82-IRQ_OFFSET]);
	234
	235	sysbus_create_varargs("cadence_ttc", 0xF8001000,
	236	pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
	237	sysbus_create_varargs("cadence_ttc", 0xF8002000,
	238	pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL);
	239
7fcd57e8 PC	240	gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]);
7fcd57e8 PC	241	gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]);
e3260506	242
b972b4e2 PC	243	dev = qdev_create(NULL, "generic-sdhci");
	244	qdev_init_nofail(dev);
	245	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0100000);
	246	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[56-IRQ_OFFSET]);
	247
	248	dev = qdev_create(NULL, "generic-sdhci");
	249	qdev_init_nofail(dev);
	250	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0101000);
	251	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[79-IRQ_OFFSET]);
	252
74fcbd22 GR	253	dev = qdev_create(NULL, TYPE_ZYNQ_XADC);
	254	qdev_init_nofail(dev);
	255	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100);
	256	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);
	257
7451afb6 PC	258	dev = qdev_create(NULL, "pl330");
	259	qdev_prop_set_uint8(dev, "num_chnls", 8);
	260	qdev_prop_set_uint8(dev, "num_periph_req", 4);
	261	qdev_prop_set_uint8(dev, "num_events", 16);
	262
	263	qdev_prop_set_uint8(dev, "data_width", 64);
	264	qdev_prop_set_uint8(dev, "wr_cap", 8);
	265	qdev_prop_set_uint8(dev, "wr_q_dep", 16);
	266	qdev_prop_set_uint8(dev, "rd_cap", 8);
	267	qdev_prop_set_uint8(dev, "rd_q_dep", 16);
	268	qdev_prop_set_uint16(dev, "data_buffer_dep", 256);
	269
	270	qdev_init_nofail(dev);
	271	busdev = SYS_BUS_DEVICE(dev);
	272	sysbus_mmio_map(busdev, 0, 0xF8003000);
	273	sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */
	274	for (n = 0; n < 8; ++n) { /* event irqs */
	275	sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
	276	}
	277
e3260506 PC	278	zynq_binfo.ram_size = ram_size;
	279	zynq_binfo.kernel_filename = kernel_filename;
	280	zynq_binfo.kernel_cmdline = kernel_cmdline;
	281	zynq_binfo.initrd_filename = initrd_filename;
	282	zynq_binfo.nb_cpus = 1;
	283	zynq_binfo.board_id = 0xd32;
	284	zynq_binfo.loader_start = 0;
c3a9a689 PC	285	zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR;
	286	zynq_binfo.write_board_setup = zynq_write_board_setup;
	287
182735ef	288	arm_load_kernel(ARM_CPU(first_cpu), &zynq_binfo);
e3260506 PC	289	}
e3260506 PC	290
e264d29d	291	static void zynq_machine_init(MachineClass *mc)
e3260506	292	{
e264d29d EH	293	mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
	294	mc->init = zynq_init;
	295	mc->block_default_type = IF_SCSI;
	296	mc->max_cpus = 1;
	297	mc->no_sdcard = 1;
e3260506 PC	298	}
e3260506 PC	299
e264d29d	300	DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init)