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1/*
2 * QEMU SuperH CPU
3 *
c4bb0f99 4 * Copyright (c) 2005 Samuel Tardieu
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5 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see
19 * <http://www.gnu.org/licenses/lgpl-2.1.html>
20 */
21
9d4c9946 22#include "qemu/osdep.h"
da34e65c 23#include "qapi/error.h"
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24#include "cpu.h"
25#include "qemu-common.h"
1e45d31b 26#include "migration/vmstate.h"
63c91552 27#include "exec/exec-all.h"
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28
29
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30static void superh_cpu_set_pc(CPUState *cs, vaddr value)
31{
32 SuperHCPU *cpu = SUPERH_CPU(cs);
33
34 cpu->env.pc = value;
35}
36
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37static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
38{
39 SuperHCPU *cpu = SUPERH_CPU(cs);
40
41 cpu->env.pc = tb->pc;
ca69176d 42 cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK;
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43}
44
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45static bool superh_cpu_has_work(CPUState *cs)
46{
47 return cs->interrupt_request & CPU_INTERRUPT_HARD;
48}
49
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50/* CPUClass::reset() */
51static void superh_cpu_reset(CPUState *s)
52{
53 SuperHCPU *cpu = SUPERH_CPU(s);
54 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu);
55 CPUSH4State *env = &cpu->env;
56
57 scc->parent_reset(s);
58
1f5c00cf 59 memset(env, 0, offsetof(CPUSH4State, end_reset_fields));
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60
61 env->pc = 0xA0000000;
62#if defined(CONFIG_USER_ONLY)
63 env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
64 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
65#else
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66 env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) |
67 (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0);
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68 env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */
69 set_float_rounding_mode(float_round_to_zero, &env->fp_status);
70 set_flush_to_zero(1, &env->fp_status);
71#endif
72 set_default_nan_mode(1, &env->fp_status);
af39bc8c 73 set_snan_bit_is_one(1, &env->fp_status);
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74}
75
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76static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
77{
78 info->mach = bfd_mach_sh4;
79 info->print_insn = print_insn_sh;
80}
81
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82typedef struct SuperHCPUListState {
83 fprintf_function cpu_fprintf;
84 FILE *file;
85} SuperHCPUListState;
86
87/* Sort alphabetically by type name. */
88static gint superh_cpu_list_compare(gconstpointer a, gconstpointer b)
89{
90 ObjectClass *class_a = (ObjectClass *)a;
91 ObjectClass *class_b = (ObjectClass *)b;
92 const char *name_a, *name_b;
93
94 name_a = object_class_get_name(class_a);
95 name_b = object_class_get_name(class_b);
96 return strcmp(name_a, name_b);
97}
98
99static void superh_cpu_list_entry(gpointer data, gpointer user_data)
100{
101 ObjectClass *oc = data;
102 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
103 SuperHCPUListState *s = user_data;
104
105 (*s->cpu_fprintf)(s->file, "%s\n",
106 scc->name);
107}
108
109void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf)
110{
111 SuperHCPUListState s = {
112 .cpu_fprintf = cpu_fprintf,
113 .file = f,
114 };
115 GSList *list;
116
117 list = object_class_get_list(TYPE_SUPERH_CPU, false);
118 list = g_slist_sort(list, superh_cpu_list_compare);
119 g_slist_foreach(list, superh_cpu_list_entry, &s);
120 g_slist_free(list);
121}
122
123static gint superh_cpu_name_compare(gconstpointer a, gconstpointer b)
124{
125 const SuperHCPUClass *scc = SUPERH_CPU_CLASS(a);
126 const char *name = b;
127
128 return strcasecmp(scc->name, name);
129}
130
131static ObjectClass *superh_cpu_class_by_name(const char *cpu_model)
132{
133 ObjectClass *oc;
134 GSList *list, *item;
135
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136 if (strcasecmp(cpu_model, "any") == 0) {
137 return object_class_by_name(TYPE_SH7750R_CPU);
138 }
139
140 oc = object_class_by_name(cpu_model);
141 if (oc != NULL && object_class_dynamic_cast(oc, TYPE_SUPERH_CPU) != NULL
142 && !object_class_is_abstract(oc)) {
143 return oc;
144 }
145
146 oc = NULL;
147 list = object_class_get_list(TYPE_SUPERH_CPU, false);
148 item = g_slist_find_custom(list, cpu_model, superh_cpu_name_compare);
149 if (item != NULL) {
150 oc = item->data;
151 }
152 g_slist_free(list);
153 return oc;
154}
155
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156static void sh7750r_cpu_initfn(Object *obj)
157{
158 SuperHCPU *cpu = SUPERH_CPU(obj);
159 CPUSH4State *env = &cpu->env;
160
161 env->id = SH_CPU_SH7750R;
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162 env->features = SH_FEATURE_BCR3_AND_BCR4;
163}
164
165static void sh7750r_class_init(ObjectClass *oc, void *data)
166{
167 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
168
169 scc->name = "SH7750R";
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170 scc->pvr = 0x00050000;
171 scc->prr = 0x00000100;
172 scc->cvr = 0x00110000;
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173}
174
175static const TypeInfo sh7750r_type_info = {
176 .name = TYPE_SH7750R_CPU,
177 .parent = TYPE_SUPERH_CPU,
178 .class_init = sh7750r_class_init,
179 .instance_init = sh7750r_cpu_initfn,
180};
181
182static void sh7751r_cpu_initfn(Object *obj)
183{
184 SuperHCPU *cpu = SUPERH_CPU(obj);
185 CPUSH4State *env = &cpu->env;
186
187 env->id = SH_CPU_SH7751R;
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188 env->features = SH_FEATURE_BCR3_AND_BCR4;
189}
190
191static void sh7751r_class_init(ObjectClass *oc, void *data)
192{
193 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
194
195 scc->name = "SH7751R";
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196 scc->pvr = 0x04050005;
197 scc->prr = 0x00000113;
198 scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */
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199}
200
201static const TypeInfo sh7751r_type_info = {
202 .name = TYPE_SH7751R_CPU,
203 .parent = TYPE_SUPERH_CPU,
204 .class_init = sh7751r_class_init,
205 .instance_init = sh7751r_cpu_initfn,
206};
207
208static void sh7785_cpu_initfn(Object *obj)
209{
210 SuperHCPU *cpu = SUPERH_CPU(obj);
211 CPUSH4State *env = &cpu->env;
212
213 env->id = SH_CPU_SH7785;
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214 env->features = SH_FEATURE_SH4A;
215}
216
217static void sh7785_class_init(ObjectClass *oc, void *data)
218{
219 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
220
221 scc->name = "SH7785";
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222 scc->pvr = 0x10300700;
223 scc->prr = 0x00000200;
224 scc->cvr = 0x71440211;
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225}
226
227static const TypeInfo sh7785_type_info = {
228 .name = TYPE_SH7785_CPU,
229 .parent = TYPE_SUPERH_CPU,
230 .class_init = sh7785_class_init,
231 .instance_init = sh7785_cpu_initfn,
232};
233
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234static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
235{
14a10fc3 236 CPUState *cs = CPU(dev);
55acb588 237 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev);
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238 Error *local_err = NULL;
239
240 cpu_exec_realizefn(cs, &local_err);
241 if (local_err != NULL) {
242 error_propagate(errp, local_err);
243 return;
244 }
55acb588 245
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246 cpu_reset(cs);
247 qemu_init_vcpu(cs);
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248
249 scc->parent_realize(dev, errp);
250}
251
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252static void superh_cpu_initfn(Object *obj)
253{
c05efcb1 254 CPUState *cs = CPU(obj);
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255 SuperHCPU *cpu = SUPERH_CPU(obj);
256 CPUSH4State *env = &cpu->env;
257
c05efcb1 258 cs->env_ptr = env;
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259
260 env->movcal_backup_tail = &(env->movcal_backup);
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261
262 if (tcg_enabled()) {
263 sh4_translate_init();
264 }
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265}
266
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267static const VMStateDescription vmstate_sh_cpu = {
268 .name = "cpu",
269 .unmigratable = 1,
270};
271
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272static void superh_cpu_class_init(ObjectClass *oc, void *data)
273{
1e45d31b 274 DeviceClass *dc = DEVICE_CLASS(oc);
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275 CPUClass *cc = CPU_CLASS(oc);
276 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
277
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278 scc->parent_realize = dc->realize;
279 dc->realize = superh_cpu_realizefn;
280
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281 scc->parent_reset = cc->reset;
282 cc->reset = superh_cpu_reset;
1e45d31b 283
c1b382e7 284 cc->class_by_name = superh_cpu_class_by_name;
8c2e1b00 285 cc->has_work = superh_cpu_has_work;
97a8ea5a 286 cc->do_interrupt = superh_cpu_do_interrupt;
f47ede19 287 cc->cpu_exec_interrupt = superh_cpu_exec_interrupt;
878096ee 288 cc->dump_state = superh_cpu_dump_state;
f45748f1 289 cc->set_pc = superh_cpu_set_pc;
bdf7ae5b 290 cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
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291 cc->gdb_read_register = superh_cpu_gdb_read_register;
292 cc->gdb_write_register = superh_cpu_gdb_write_register;
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293#ifdef CONFIG_USER_ONLY
294 cc->handle_mmu_fault = superh_cpu_handle_mmu_fault;
295#else
34257c21 296 cc->do_unaligned_access = superh_cpu_do_unaligned_access;
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297 cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
298#endif
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299 cc->disas_set_info = superh_cpu_disas_set_info;
300
a0e372f0 301 cc->gdb_num_core_regs = 59;
4c315c27 302
d49dd523 303 dc->vmsd = &vmstate_sh_cpu;
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304}
305
306static const TypeInfo superh_cpu_type_info = {
307 .name = TYPE_SUPERH_CPU,
308 .parent = TYPE_CPU,
309 .instance_size = sizeof(SuperHCPU),
2b4b4906 310 .instance_init = superh_cpu_initfn,
c1b382e7 311 .abstract = true,
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312 .class_size = sizeof(SuperHCPUClass),
313 .class_init = superh_cpu_class_init,
314};
315
316static void superh_cpu_register_types(void)
317{
318 type_register_static(&superh_cpu_type_info);
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319 type_register_static(&sh7750r_type_info);
320 type_register_static(&sh7751r_type_info);
321 type_register_static(&sh7785_type_info);
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322}
323
324type_init(superh_cpu_register_types)
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