[qemu.git] / hw / intc / imx_avic.c

/*
 * i.MX31 Vectored Interrupt Controller
 *
 * Note this is NOT the PL192 provided by ARM, but
 * a custom implementation by Freescale.
 *
 * Copyright (c) 2008 OKL
 * Copyright (c) 2011 NICTA Pty Ltd
 * Originally written by Hans Jiang
 *
 * This code is licensed under the GPL version 2 or later.  See
 * the COPYING file in the top-level directory.
 *
 * TODO: implement vectors.
 */

#include "hw/hw.h"
#include "hw/sysbus.h"
#include "qemu/host-utils.h"

#define DEBUG_INT 1
#undef DEBUG_INT /* comment out for debugging */

#ifdef DEBUG_INT
#define DPRINTF(fmt, args...) \
do { printf("imx_avic: " fmt , ##args); } while (0)
#else
#define DPRINTF(fmt, args...) do {} while (0)
#endif

/*
 * Define to 1 for messages about attempts to
 * access unimplemented registers or similar.
 */
#define DEBUG_IMPLEMENTATION 1
#if DEBUG_IMPLEMENTATION
#  define IPRINTF(fmt, args...) \
    do  { fprintf(stderr, "imx_avic: " fmt, ##args); } while (0)
#else
#  define IPRINTF(fmt, args...) do {} while (0)
#endif

#define IMX_AVIC_NUM_IRQS 64

/* Interrupt Control Bits */
#define ABFLAG (1<<25)
#define ABFEN (1<<24)
#define NIDIS (1<<22) /* Normal Interrupt disable */
#define FIDIS (1<<21) /* Fast interrupt disable */
#define NIAD  (1<<20) /* Normal Interrupt Arbiter Rise ARM level */
#define FIAD  (1<<19) /* Fast Interrupt Arbiter Rise ARM level */
#define NM    (1<<18) /* Normal interrupt mode */


#define PRIO_PER_WORD (sizeof(uint32_t) * 8 / 4)
#define PRIO_WORDS (IMX_AVIC_NUM_IRQS/PRIO_PER_WORD)

#define TYPE_IMX_AVIC "imx_avic"
#define IMX_AVIC(obj) \
    OBJECT_CHECK(IMXAVICState, (obj), TYPE_IMX_AVIC)

typedef struct IMXAVICState {
    SysBusDevice parent_obj;

    MemoryRegion iomem;
    uint64_t pending;
    uint64_t enabled;
    uint64_t is_fiq;
    uint32_t intcntl;
    uint32_t intmask;
    qemu_irq irq;
    qemu_irq fiq;
    uint32_t prio[PRIO_WORDS]; /* Priorities are 4-bits each */
} IMXAVICState;

static const VMStateDescription vmstate_imx_avic = {
    .name = "imx-avic",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64(pending, IMXAVICState),
        VMSTATE_UINT64(enabled, IMXAVICState),
        VMSTATE_UINT64(is_fiq, IMXAVICState),
        VMSTATE_UINT32(intcntl, IMXAVICState),
        VMSTATE_UINT32(intmask, IMXAVICState),
        VMSTATE_UINT32_ARRAY(prio, IMXAVICState, PRIO_WORDS),
        VMSTATE_END_OF_LIST()
    },
};


static inline int imx_avic_prio(IMXAVICState *s, int irq)
{
    uint32_t word = irq / PRIO_PER_WORD;
    uint32_t part = 4 * (irq % PRIO_PER_WORD);
    return 0xf & (s->prio[word] >> part);
}

/* Update interrupts.  */
static void imx_avic_update(IMXAVICState *s)
{
    int i;
    uint64_t new = s->pending & s->enabled;
    uint64_t flags;

    flags = new & s->is_fiq;
    qemu_set_irq(s->fiq, !!flags);

    flags = new & ~s->is_fiq;
    if (!flags || (s->intmask == 0x1f)) {
        qemu_set_irq(s->irq, !!flags);
        return;
    }

    /*
     * Take interrupt if there's a pending interrupt with
     * priority higher than the value of intmask
     */
    for (i = 0; i < IMX_AVIC_NUM_IRQS; i++) {
        if (flags & (1UL << i)) {
            if (imx_avic_prio(s, i) > s->intmask) {
                qemu_set_irq(s->irq, 1);
                return;
            }
        }
    }
    qemu_set_irq(s->irq, 0);
}

static void imx_avic_set_irq(void *opaque, int irq, int level)
{
    IMXAVICState *s = (IMXAVICState *)opaque;

    if (level) {
        DPRINTF("Raising IRQ %d, prio %d\n",
                irq, imx_avic_prio(s, irq));
        s->pending |= (1ULL << irq);
    } else {
        DPRINTF("Clearing IRQ %d, prio %d\n",
                irq, imx_avic_prio(s, irq));
        s->pending &= ~(1ULL << irq);
    }

    imx_avic_update(s);
}


static uint64_t imx_avic_read(void *opaque,
                             hwaddr offset, unsigned size)
{
    IMXAVICState *s = (IMXAVICState *)opaque;


    DPRINTF("read(offset = 0x%x)\n", offset >> 2);
    switch (offset >> 2) {
    case 0: /* INTCNTL */
        return s->intcntl;

    case 1: /* Normal Interrupt Mask Register, NIMASK */
        return s->intmask;

    case 2: /* Interrupt Enable Number Register, INTENNUM */
    case 3: /* Interrupt Disable Number Register, INTDISNUM */
        return 0;

    case 4: /* Interrupt Enabled Number Register High */
        return s->enabled >> 32;

    case 5: /* Interrupt Enabled Number Register Low */
        return s->enabled & 0xffffffffULL;

    case 6: /* Interrupt Type Register High */
        return s->is_fiq >> 32;

    case 7: /* Interrupt Type Register Low */
        return s->is_fiq & 0xffffffffULL;

    case 8: /* Normal Interrupt Priority Register 7 */
    case 9: /* Normal Interrupt Priority Register 6 */
    case 10:/* Normal Interrupt Priority Register 5 */
    case 11:/* Normal Interrupt Priority Register 4 */
    case 12:/* Normal Interrupt Priority Register 3 */
    case 13:/* Normal Interrupt Priority Register 2 */
    case 14:/* Normal Interrupt Priority Register 1 */
    case 15:/* Normal Interrupt Priority Register 0 */
        return s->prio[15-(offset>>2)];

    case 16: /* Normal interrupt vector and status register */
    {
        /*
         * This returns the highest priority
         * outstanding interrupt.  Where there is more than
         * one pending IRQ with the same priority,
         * take the highest numbered one.
         */
        uint64_t flags = s->pending & s->enabled & ~s->is_fiq;
        int i;
        int prio = -1;
        int irq = -1;
        for (i = 63; i >= 0; --i) {
            if (flags & (1ULL<<i)) {
                int irq_prio = imx_avic_prio(s, i);
                if (irq_prio > prio) {
                    irq = i;
                    prio = irq_prio;
                }
            }
        }
        if (irq >= 0) {
            imx_avic_set_irq(s, irq, 0);
            return irq << 16 | prio;
        }
        return 0xffffffffULL;
    }
    case 17:/* Fast Interrupt vector and status register */
    {
        uint64_t flags = s->pending & s->enabled & s->is_fiq;
        int i = ctz64(flags);
        if (i < 64) {
            imx_avic_set_irq(opaque, i, 0);
            return i;
        }
        return 0xffffffffULL;
    }
    case 18:/* Interrupt source register high */
        return s->pending >> 32;

    case 19:/* Interrupt source register low */
        return s->pending & 0xffffffffULL;

    case 20:/* Interrupt Force Register high */
    case 21:/* Interrupt Force Register low */
        return 0;

    case 22:/* Normal Interrupt Pending Register High */
        return (s->pending & s->enabled & ~s->is_fiq) >> 32;

    case 23:/* Normal Interrupt Pending Register Low */
        return (s->pending & s->enabled & ~s->is_fiq) & 0xffffffffULL;

    case 24: /* Fast Interrupt Pending Register High  */
        return (s->pending & s->enabled & s->is_fiq) >> 32;

    case 25: /* Fast Interrupt Pending Register Low  */
        return (s->pending & s->enabled & s->is_fiq) & 0xffffffffULL;

    case 0x40:            /* AVIC vector 0, use for WFI WAR */
        return 0x4;

    default:
        IPRINTF("imx_avic_read: Bad offset 0x%x\n", (int)offset);
        return 0;
    }
}

static void imx_avic_write(void *opaque, hwaddr offset,
                          uint64_t val, unsigned size)
{
    IMXAVICState *s = (IMXAVICState *)opaque;

    /* Vector Registers not yet supported */
    if (offset >= 0x100 && offset <= 0x2fc) {
        IPRINTF("imx_avic_write to vector register %d ignored\n",
                (unsigned int)((offset - 0x100) >> 2));
        return;
    }

    DPRINTF("imx_avic_write(0x%x) = %x\n",
            (unsigned int)offset>>2, (unsigned int)val);
    switch (offset >> 2) {
    case 0: /* Interrupt Control Register, INTCNTL */
        s->intcntl = val & (ABFEN | NIDIS | FIDIS | NIAD | FIAD | NM);
        if (s->intcntl & ABFEN) {
            s->intcntl &= ~(val & ABFLAG);
        }
        break;

    case 1: /* Normal Interrupt Mask Register, NIMASK */
        s->intmask = val & 0x1f;
        break;

    case 2: /* Interrupt Enable Number Register, INTENNUM */
        DPRINTF("enable(%d)\n", (int)val);
        val &= 0x3f;
        s->enabled |= (1ULL << val);
        break;

    case 3: /* Interrupt Disable Number Register, INTDISNUM */
        DPRINTF("disable(%d)\n", (int)val);
        val &= 0x3f;
        s->enabled &= ~(1ULL << val);
        break;

    case 4: /* Interrupt Enable Number Register High */
        s->enabled = (s->enabled & 0xffffffffULL) | (val << 32);
        break;

    case 5: /* Interrupt Enable Number Register Low */
        s->enabled = (s->enabled & 0xffffffff00000000ULL) | val;
        break;

    case 6: /* Interrupt Type Register High */
        s->is_fiq = (s->is_fiq & 0xffffffffULL) | (val << 32);
        break;

    case 7: /* Interrupt Type Register Low */
        s->is_fiq = (s->is_fiq & 0xffffffff00000000ULL) | val;
        break;

    case 8: /* Normal Interrupt Priority Register 7 */
    case 9: /* Normal Interrupt Priority Register 6 */
    case 10:/* Normal Interrupt Priority Register 5 */
    case 11:/* Normal Interrupt Priority Register 4 */
    case 12:/* Normal Interrupt Priority Register 3 */
    case 13:/* Normal Interrupt Priority Register 2 */
    case 14:/* Normal Interrupt Priority Register 1 */
    case 15:/* Normal Interrupt Priority Register 0 */
        s->prio[15-(offset>>2)] = val;
        break;

        /* Read-only registers, writes ignored */
    case 16:/* Normal Interrupt Vector and Status register */
    case 17:/* Fast Interrupt vector and status register */
    case 18:/* Interrupt source register high */
    case 19:/* Interrupt source register low */
        return;

    case 20:/* Interrupt Force Register high */
        s->pending = (s->pending & 0xffffffffULL) | (val << 32);
        break;

    case 21:/* Interrupt Force Register low */
        s->pending = (s->pending & 0xffffffff00000000ULL) | val;
        break;

    case 22:/* Normal Interrupt Pending Register High */
    case 23:/* Normal Interrupt Pending Register Low */
    case 24: /* Fast Interrupt Pending Register High  */
    case 25: /* Fast Interrupt Pending Register Low  */
        return;

    default:
        IPRINTF("imx_avic_write: Bad offset %x\n", (int)offset);
    }
    imx_avic_update(s);
}

static const MemoryRegionOps imx_avic_ops = {
    .read = imx_avic_read,
    .write = imx_avic_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void imx_avic_reset(DeviceState *dev)
{
    IMXAVICState *s = IMX_AVIC(dev);

    s->pending = 0;
    s->enabled = 0;
    s->is_fiq = 0;
    s->intmask = 0x1f;
    s->intcntl = 0;
    memset(s->prio, 0, sizeof s->prio);
}

static int imx_avic_init(SysBusDevice *sbd)
{
    DeviceState *dev = DEVICE(sbd);
    IMXAVICState *s = IMX_AVIC(dev);

    memory_region_init_io(&s->iomem, OBJECT(s), &imx_avic_ops, s,
                          "imx_avic", 0x1000);
    sysbus_init_mmio(sbd, &s->iomem);

    qdev_init_gpio_in(dev, imx_avic_set_irq, IMX_AVIC_NUM_IRQS);
    sysbus_init_irq(sbd, &s->irq);
    sysbus_init_irq(sbd, &s->fiq);

    return 0;
}


static void imx_avic_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
    k->init = imx_avic_init;
    dc->vmsd = &vmstate_imx_avic;
    dc->reset = imx_avic_reset;
    dc->desc = "i.MX Advanced Vector Interrupt Controller";
}

static const TypeInfo imx_avic_info = {
    .name = TYPE_IMX_AVIC,
    .parent = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(IMXAVICState),
    .class_init = imx_avic_class_init,
};

static void imx_avic_register_types(void)
{
    type_register_static(&imx_avic_info);
}

type_init(imx_avic_register_types)
Commit	Line	Data
ff53d4c6 PC	1	/*
	2	* i.MX31 Vectored Interrupt Controller
	3	*
	4	* Note this is NOT the PL192 provided by ARM, but
	5	* a custom implementation by Freescale.
	6	*
	7	* Copyright (c) 2008 OKL
	8	* Copyright (c) 2011 NICTA Pty Ltd
aade7b91	9	* Originally written by Hans Jiang
ff53d4c6	10	*
aade7b91	11	* This code is licensed under the GPL version 2 or later. See
ff53d4c6 PC	12	* the COPYING file in the top-level directory.
	13	*
	14	* TODO: implement vectors.
	15	*/
	16
83c9f4ca PB	17	#include "hw/hw.h"
83c9f4ca PB	18	#include "hw/sysbus.h"
1de7afc9	19	#include "qemu/host-utils.h"
ff53d4c6 PC	20
	21	#define DEBUG_INT 1
	22	#undef DEBUG_INT /* comment out for debugging */
	23
	24	#ifdef DEBUG_INT
	25	#define DPRINTF(fmt, args...) \
	26	do { printf("imx_avic: " fmt , ##args); } while (0)
	27	#else
	28	#define DPRINTF(fmt, args...) do {} while (0)
	29	#endif
	30
	31	/*
	32	* Define to 1 for messages about attempts to
	33	* access unimplemented registers or similar.
	34	*/
	35	#define DEBUG_IMPLEMENTATION 1
	36	#if DEBUG_IMPLEMENTATION
	37	# define IPRINTF(fmt, args...) \
	38	do { fprintf(stderr, "imx_avic: " fmt, ##args); } while (0)
	39	#else
	40	# define IPRINTF(fmt, args...) do {} while (0)
	41	#endif
	42
	43	#define IMX_AVIC_NUM_IRQS 64
	44
	45	/* Interrupt Control Bits */
	46	#define ABFLAG (1<<25)
	47	#define ABFEN (1<<24)
	48	#define NIDIS (1<<22) /* Normal Interrupt disable */
	49	#define FIDIS (1<<21) /* Fast interrupt disable */
	50	#define NIAD (1<<20) /* Normal Interrupt Arbiter Rise ARM level */
	51	#define FIAD (1<<19) /* Fast Interrupt Arbiter Rise ARM level */
	52	#define NM (1<<18) /* Normal interrupt mode */
	53
	54
	55	#define PRIO_PER_WORD (sizeof(uint32_t) * 8 / 4)
	56	#define PRIO_WORDS (IMX_AVIC_NUM_IRQS/PRIO_PER_WORD)
	57
5ff94a61 AF	58	#define TYPE_IMX_AVIC "imx_avic"
	59	#define IMX_AVIC(obj) \
	60	OBJECT_CHECK(IMXAVICState, (obj), TYPE_IMX_AVIC)
	61
	62	typedef struct IMXAVICState {
	63	SysBusDevice parent_obj;
	64
ff53d4c6 PC	65	MemoryRegion iomem;
	66	uint64_t pending;
	67	uint64_t enabled;
	68	uint64_t is_fiq;
	69	uint32_t intcntl;
	70	uint32_t intmask;
	71	qemu_irq irq;
	72	qemu_irq fiq;
	73	uint32_t prio[PRIO_WORDS]; /* Priorities are 4-bits each */
	74	} IMXAVICState;
	75
	76	static const VMStateDescription vmstate_imx_avic = {
	77	.name = "imx-avic",
	78	.version_id = 1,
	79	.minimum_version_id = 1,
ff53d4c6 PC	80	.fields = (VMStateField[]) {
	81	VMSTATE_UINT64(pending, IMXAVICState),
	82	VMSTATE_UINT64(enabled, IMXAVICState),
	83	VMSTATE_UINT64(is_fiq, IMXAVICState),
	84	VMSTATE_UINT32(intcntl, IMXAVICState),
	85	VMSTATE_UINT32(intmask, IMXAVICState),
	86	VMSTATE_UINT32_ARRAY(prio, IMXAVICState, PRIO_WORDS),
	87	VMSTATE_END_OF_LIST()
	88	},
	89	};
	90
	91
	92
	93	static inline int imx_avic_prio(IMXAVICState *s, int irq)
	94	{
	95	uint32_t word = irq / PRIO_PER_WORD;
	96	uint32_t part = 4 * (irq % PRIO_PER_WORD);
	97	return 0xf & (s->prio[word] >> part);
	98	}
	99
ff53d4c6 PC	100	/* Update interrupts. */
	101	static void imx_avic_update(IMXAVICState *s)
	102	{
	103	int i;
	104	uint64_t new = s->pending & s->enabled;
	105	uint64_t flags;
	106
	107	flags = new & s->is_fiq;
	108	qemu_set_irq(s->fiq, !!flags);
	109
	110	flags = new & ~s->is_fiq;
	111	if (!flags \|\| (s->intmask == 0x1f)) {
	112	qemu_set_irq(s->irq, !!flags);
	113	return;
	114	}
	115
	116	/*
	117	* Take interrupt if there's a pending interrupt with
	118	* priority higher than the value of intmask
	119	*/
	120	for (i = 0; i < IMX_AVIC_NUM_IRQS; i++) {
	121	if (flags & (1UL << i)) {
	122	if (imx_avic_prio(s, i) > s->intmask) {
	123	qemu_set_irq(s->irq, 1);
	124	return;
	125	}
	126	}
	127	}
	128	qemu_set_irq(s->irq, 0);
	129	}
	130
	131	static void imx_avic_set_irq(void *opaque, int irq, int level)
	132	{
	133	IMXAVICState s = (IMXAVICState )opaque;
	134
	135	if (level) {
	136	DPRINTF("Raising IRQ %d, prio %d\n",
	137	irq, imx_avic_prio(s, irq));
	138	s->pending \|= (1ULL << irq);
	139	} else {
	140	DPRINTF("Clearing IRQ %d, prio %d\n",
	141	irq, imx_avic_prio(s, irq));
	142	s->pending &= ~(1ULL << irq);
	143	}
	144
	145	imx_avic_update(s);
	146	}
	147
	148
	149	static uint64_t imx_avic_read(void *opaque,
a8170e5e	150	hwaddr offset, unsigned size)
ff53d4c6 PC	151	{
	152	IMXAVICState s = (IMXAVICState )opaque;
	153
	154
	155	DPRINTF("read(offset = 0x%x)\n", offset >> 2);
	156	switch (offset >> 2) {
	157	case 0: /* INTCNTL */
	158	return s->intcntl;
	159
	160	case 1: /* Normal Interrupt Mask Register, NIMASK */
	161	return s->intmask;
	162
	163	case 2: /* Interrupt Enable Number Register, INTENNUM */
	164	case 3: /* Interrupt Disable Number Register, INTDISNUM */
	165	return 0;
	166
	167	case 4: /* Interrupt Enabled Number Register High */
	168	return s->enabled >> 32;
	169
	170	case 5: /* Interrupt Enabled Number Register Low */
	171	return s->enabled & 0xffffffffULL;
	172
	173	case 6: /* Interrupt Type Register High */
	174	return s->is_fiq >> 32;
	175
	176	case 7: /* Interrupt Type Register Low */
	177	return s->is_fiq & 0xffffffffULL;
	178
	179	case 8: /* Normal Interrupt Priority Register 7 */
	180	case 9: /* Normal Interrupt Priority Register 6 */
	181	case 10:/* Normal Interrupt Priority Register 5 */
	182	case 11:/* Normal Interrupt Priority Register 4 */
	183	case 12:/* Normal Interrupt Priority Register 3 */
	184	case 13:/* Normal Interrupt Priority Register 2 */
	185	case 14:/* Normal Interrupt Priority Register 1 */
	186	case 15:/* Normal Interrupt Priority Register 0 */
	187	return s->prio[15-(offset>>2)];
	188
	189	case 16: /* Normal interrupt vector and status register */
	190	{
	191	/*
	192	* This returns the highest priority
	193	* outstanding interrupt. Where there is more than
	194	* one pending IRQ with the same priority,
	195	* take the highest numbered one.
	196	*/
	197	uint64_t flags = s->pending & s->enabled & ~s->is_fiq;
	198	int i;
	199	int prio = -1;
	200	int irq = -1;
	201	for (i = 63; i >= 0; --i) {
	202	if (flags & (1ULL<<i)) {
	203	int irq_prio = imx_avic_prio(s, i);
	204	if (irq_prio > prio) {
	205	irq = i;
	206	prio = irq_prio;
	207	}
	208	}
	209	}
	210	if (irq >= 0) {
	211	imx_avic_set_irq(s, irq, 0);
	212	return irq << 16 \| prio;
	213	}
	214	return 0xffffffffULL;
215	}
216	case 17:/* Fast Interrupt vector and status register */
217	{
218	uint64_t flags = s->pending & s->enabled & s->is_fiq;
219	int i = ctz64(flags);
220	if (i < 64) {
221	imx_avic_set_irq(opaque, i, 0);
222	return i;
223	}
224	return 0xffffffffULL;
225	}
226	case 18:/* Interrupt source register high */
227	return s->pending >> 32;
228
229	case 19:/* Interrupt source register low */
230	return s->pending & 0xffffffffULL;
231
232	case 20:/* Interrupt Force Register high */
233	case 21:/* Interrupt Force Register low */
234	return 0;
235
236	case 22:/* Normal Interrupt Pending Register High */
237	return (s->pending & s->enabled & ~s->is_fiq) >> 32;
238
239	case 23:/* Normal Interrupt Pending Register Low */
240	return (s->pending & s->enabled & ~s->is_fiq) & 0xffffffffULL;
241
242	case 24: /* Fast Interrupt Pending Register High */
243	return (s->pending & s->enabled & s->is_fiq) >> 32;
244
245	case 25: /* Fast Interrupt Pending Register Low */
246	return (s->pending & s->enabled & s->is_fiq) & 0xffffffffULL;
247
248	case 0x40: /* AVIC vector 0, use for WFI WAR */
249	return 0x4;
250
251	default:
252	IPRINTF("imx_avic_read: Bad offset 0x%x\n", (int)offset);
253	return 0;
254	}
255	}
256
a8170e5e	257	static void imx_avic_write(void *opaque, hwaddr offset,
ff53d4c6 PC	258	uint64_t val, unsigned size)
	259	{
	260	IMXAVICState s = (IMXAVICState )opaque;
	261
	262	/* Vector Registers not yet supported */
	263	if (offset >= 0x100 && offset <= 0x2fc) {
	264	IPRINTF("imx_avic_write to vector register %d ignored\n",
40291d61	265	(unsigned int)((offset - 0x100) >> 2));
ff53d4c6 PC	266	return;
	267	}
	268
	269	DPRINTF("imx_avic_write(0x%x) = %x\n",
	270	(unsigned int)offset>>2, (unsigned int)val);
	271	switch (offset >> 2) {
	272	case 0: /* Interrupt Control Register, INTCNTL */
	273	s->intcntl = val & (ABFEN \| NIDIS \| FIDIS \| NIAD \| FIAD \| NM);
	274	if (s->intcntl & ABFEN) {
	275	s->intcntl &= ~(val & ABFLAG);
	276	}
	277	break;
	278
	279	case 1: /* Normal Interrupt Mask Register, NIMASK */
	280	s->intmask = val & 0x1f;
	281	break;
	282
	283	case 2: /* Interrupt Enable Number Register, INTENNUM */
	284	DPRINTF("enable(%d)\n", (int)val);
	285	val &= 0x3f;
	286	s->enabled \|= (1ULL << val);
	287	break;
	288
	289	case 3: /* Interrupt Disable Number Register, INTDISNUM */
	290	DPRINTF("disable(%d)\n", (int)val);
	291	val &= 0x3f;
	292	s->enabled &= ~(1ULL << val);
	293	break;
	294
	295	case 4: /* Interrupt Enable Number Register High */
	296	s->enabled = (s->enabled & 0xffffffffULL) \| (val << 32);
	297	break;
	298
	299	case 5: /* Interrupt Enable Number Register Low */
	300	s->enabled = (s->enabled & 0xffffffff00000000ULL) \| val;
	301	break;
	302
	303	case 6: /* Interrupt Type Register High */
	304	s->is_fiq = (s->is_fiq & 0xffffffffULL) \| (val << 32);
	305	break;
	306
	307	case 7: /* Interrupt Type Register Low */
	308	s->is_fiq = (s->is_fiq & 0xffffffff00000000ULL) \| val;
	309	break;
	310
	311	case 8: /* Normal Interrupt Priority Register 7 */
	312	case 9: /* Normal Interrupt Priority Register 6 */
	313	case 10:/* Normal Interrupt Priority Register 5 */
	314	case 11:/* Normal Interrupt Priority Register 4 */
	315	case 12:/* Normal Interrupt Priority Register 3 */
	316	case 13:/* Normal Interrupt Priority Register 2 */
	317	case 14:/* Normal Interrupt Priority Register 1 */
	318	case 15:/* Normal Interrupt Priority Register 0 */
	319	s->prio[15-(offset>>2)] = val;
	320	break;
	321
	322	/* Read-only registers, writes ignored */
	323	case 16:/* Normal Interrupt Vector and Status register */
	324	case 17:/* Fast Interrupt vector and status register */
	325	case 18:/* Interrupt source register high */
	326	case 19:/* Interrupt source register low */
	327	return;
	328
	329	case 20:/* Interrupt Force Register high */
330	s->pending = (s->pending & 0xffffffffULL) \| (val << 32);
331	break;
332
333	case 21:/* Interrupt Force Register low */
334	s->pending = (s->pending & 0xffffffff00000000ULL) \| val;
335	break;
336
337	case 22:/* Normal Interrupt Pending Register High */
338	case 23:/* Normal Interrupt Pending Register Low */
339	case 24: /* Fast Interrupt Pending Register High */
340	case 25: /* Fast Interrupt Pending Register Low */
341	return;
342
343	default:
344	IPRINTF("imx_avic_write: Bad offset %x\n", (int)offset);
345	}
346	imx_avic_update(s);
347	}
348
349	static const MemoryRegionOps imx_avic_ops = {
350	.read = imx_avic_read,
351	.write = imx_avic_write,
352	.endianness = DEVICE_NATIVE_ENDIAN,
353	};
354
355	static void imx_avic_reset(DeviceState *dev)
356	{
5ff94a61 AF	357	IMXAVICState *s = IMX_AVIC(dev);
5ff94a61 AF	358
ff53d4c6 PC	359	s->pending = 0;
	360	s->enabled = 0;
	361	s->is_fiq = 0;
	362	s->intmask = 0x1f;
	363	s->intcntl = 0;
	364	memset(s->prio, 0, sizeof s->prio);
	365	}
	366
5ff94a61	367	static int imx_avic_init(SysBusDevice *sbd)
ff53d4c6	368	{
5ff94a61 AF	369	DeviceState *dev = DEVICE(sbd);
5ff94a61 AF	370	IMXAVICState *s = IMX_AVIC(dev);
ff53d4c6	371
1437c94b PB	372	memory_region_init_io(&s->iomem, OBJECT(s), &imx_avic_ops, s,
1437c94b PB	373	"imx_avic", 0x1000);
5ff94a61	374	sysbus_init_mmio(sbd, &s->iomem);
ff53d4c6	375
5ff94a61 AF	376	qdev_init_gpio_in(dev, imx_avic_set_irq, IMX_AVIC_NUM_IRQS);
	377	sysbus_init_irq(sbd, &s->irq);
	378	sysbus_init_irq(sbd, &s->fiq);
ff53d4c6 PC	379
	380	return 0;
	381	}
	382
	383
	384	static void imx_avic_class_init(ObjectClass klass, void data)
	385	{
	386	DeviceClass *dc = DEVICE_CLASS(klass);
	387	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	388	k->init = imx_avic_init;
	389	dc->vmsd = &vmstate_imx_avic;
	390	dc->reset = imx_avic_reset;
	391	dc->desc = "i.MX Advanced Vector Interrupt Controller";
	392	}
	393
	394	static const TypeInfo imx_avic_info = {
5ff94a61	395	.name = TYPE_IMX_AVIC,
ff53d4c6 PC	396	.parent = TYPE_SYS_BUS_DEVICE,
	397	.instance_size = sizeof(IMXAVICState),
	398	.class_init = imx_avic_class_init,
	399	};
	400
	401	static void imx_avic_register_types(void)
	402	{
	403	type_register_static(&imx_avic_info);
	404	}
	405
	406	type_init(imx_avic_register_types)