[qemu.git] / hw / misc / puv3_pm.c

/*
 * Power Management device simulation in PKUnity SoC
 *
 * Copyright (C) 2010-2012 Guan Xuetao
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation, or any later version.
 * See the COPYING file in the top-level directory.
 */
#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/sysbus.h"

#undef DEBUG_PUV3
#include "hw/unicore32/puv3.h"

#define TYPE_PUV3_PM "puv3_pm"
#define PUV3_PM(obj) OBJECT_CHECK(PUV3PMState, (obj), TYPE_PUV3_PM)

typedef struct PUV3PMState {
    SysBusDevice parent_obj;

    MemoryRegion iomem;

    uint32_t reg_PMCR;
    uint32_t reg_PCGR;
    uint32_t reg_PLL_SYS_CFG;
    uint32_t reg_PLL_DDR_CFG;
    uint32_t reg_PLL_VGA_CFG;
    uint32_t reg_DIVCFG;
} PUV3PMState;

static uint64_t puv3_pm_read(void *opaque, hwaddr offset,
        unsigned size)
{
    PUV3PMState *s = opaque;
    uint32_t ret = 0;

    switch (offset) {
    case 0x14:
        ret = s->reg_PCGR;
        break;
    case 0x18:
        ret = s->reg_PLL_SYS_CFG;
        break;
    case 0x1c:
        ret = s->reg_PLL_DDR_CFG;
        break;
    case 0x20:
        ret = s->reg_PLL_VGA_CFG;
        break;
    case 0x24:
        ret = s->reg_DIVCFG;
        break;
    case 0x28: /* PLL SYS STATUS */
        ret = 0x00002401;
        break;
    case 0x2c: /* PLL DDR STATUS */
        ret = 0x00100c00;
        break;
    case 0x30: /* PLL VGA STATUS */
        ret = 0x00003801;
        break;
    case 0x34: /* DIV STATUS */
        ret = 0x22f52015;
        break;
    case 0x38: /* SW RESET */
        ret = 0x0;
        break;
    case 0x44: /* PLL DFC DONE */
        ret = 0x7;
        break;
    default:
        DPRINTF("Bad offset 0x%x\n", offset);
    }
    DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);

    return ret;
}

static void puv3_pm_write(void *opaque, hwaddr offset,
        uint64_t value, unsigned size)
{
    PUV3PMState *s = opaque;

    switch (offset) {
    case 0x0:
        s->reg_PMCR = value;
        break;
    case 0x14:
        s->reg_PCGR = value;
        break;
    case 0x18:
        s->reg_PLL_SYS_CFG = value;
        break;
    case 0x1c:
        s->reg_PLL_DDR_CFG = value;
        break;
    case 0x20:
        s->reg_PLL_VGA_CFG = value;
        break;
    case 0x24:
    case 0x38:
        break;
    default:
        DPRINTF("Bad offset 0x%x\n", offset);
    }
    DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
}

static const MemoryRegionOps puv3_pm_ops = {
    .read = puv3_pm_read,
    .write = puv3_pm_write,
    .impl = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void puv3_pm_realize(DeviceState *dev, Error **errp)
{
    PUV3PMState *s = PUV3_PM(dev);

    s->reg_PCGR = 0x0;

    memory_region_init_io(&s->iomem, OBJECT(s), &puv3_pm_ops, s, "puv3_pm",
            PUV3_REGS_OFFSET);
    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
}

static void puv3_pm_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = puv3_pm_realize;
}

static const TypeInfo puv3_pm_info = {
    .name = TYPE_PUV3_PM,
    .parent = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PUV3PMState),
    .class_init = puv3_pm_class_init,
};

static void puv3_pm_register_type(void)
{
    type_register_static(&puv3_pm_info);
}

type_init(puv3_pm_register_type)
Commit	Line	Data
f716c197 GX	1	/*
	2	* Power Management device simulation in PKUnity SoC
	3	*
	4	* Copyright (C) 2010-2012 Guan Xuetao
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation, or any later version.
	9	* See the COPYING file in the top-level directory.
	10	*/
5af98cc5	11	#include "qemu/osdep.h"
83c9f4ca PB	12	#include "hw/hw.h"
83c9f4ca PB	13	#include "hw/sysbus.h"
f716c197 GX	14
f716c197 GX	15	#undef DEBUG_PUV3
0d09e41a	16	#include "hw/unicore32/puv3.h"
f716c197	17
af89a444 AF	18	#define TYPE_PUV3_PM "puv3_pm"
	19	#define PUV3_PM(obj) OBJECT_CHECK(PUV3PMState, (obj), TYPE_PUV3_PM)
	20
	21	typedef struct PUV3PMState {
	22	SysBusDevice parent_obj;
	23
f716c197 GX	24	MemoryRegion iomem;
	25
	26	uint32_t reg_PMCR;
	27	uint32_t reg_PCGR;
	28	uint32_t reg_PLL_SYS_CFG;
	29	uint32_t reg_PLL_DDR_CFG;
	30	uint32_t reg_PLL_VGA_CFG;
	31	uint32_t reg_DIVCFG;
	32	} PUV3PMState;
	33
a8170e5e	34	static uint64_t puv3_pm_read(void *opaque, hwaddr offset,
f716c197 GX	35	unsigned size)
	36	{
	37	PUV3PMState *s = opaque;
	38	uint32_t ret = 0;
	39
	40	switch (offset) {
	41	case 0x14:
	42	ret = s->reg_PCGR;
	43	break;
	44	case 0x18:
	45	ret = s->reg_PLL_SYS_CFG;
	46	break;
	47	case 0x1c:
	48	ret = s->reg_PLL_DDR_CFG;
	49	break;
	50	case 0x20:
	51	ret = s->reg_PLL_VGA_CFG;
	52	break;
	53	case 0x24:
	54	ret = s->reg_DIVCFG;
	55	break;
	56	case 0x28: /* PLL SYS STATUS */
	57	ret = 0x00002401;
	58	break;
	59	case 0x2c: /* PLL DDR STATUS */
	60	ret = 0x00100c00;
	61	break;
	62	case 0x30: /* PLL VGA STATUS */
	63	ret = 0x00003801;
	64	break;
	65	case 0x34: /* DIV STATUS */
	66	ret = 0x22f52015;
	67	break;
	68	case 0x38: /* SW RESET */
	69	ret = 0x0;
	70	break;
	71	case 0x44: /* PLL DFC DONE */
	72	ret = 0x7;
	73	break;
	74	default:
	75	DPRINTF("Bad offset 0x%x\n", offset);
	76	}
	77	DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
	78
	79	return ret;
	80	}
	81
a8170e5e	82	static void puv3_pm_write(void *opaque, hwaddr offset,
f716c197 GX	83	uint64_t value, unsigned size)
	84	{
	85	PUV3PMState *s = opaque;
	86
	87	switch (offset) {
	88	case 0x0:
	89	s->reg_PMCR = value;
	90	break;
	91	case 0x14:
	92	s->reg_PCGR = value;
	93	break;
	94	case 0x18:
	95	s->reg_PLL_SYS_CFG = value;
	96	break;
	97	case 0x1c:
	98	s->reg_PLL_DDR_CFG = value;
	99	break;
	100	case 0x20:
	101	s->reg_PLL_VGA_CFG = value;
	102	break;
	103	case 0x24:
	104	case 0x38:
	105	break;
	106	default:
	107	DPRINTF("Bad offset 0x%x\n", offset);
	108	}
	109	DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
	110	}
	111
	112	static const MemoryRegionOps puv3_pm_ops = {
	113	.read = puv3_pm_read,
	114	.write = puv3_pm_write,
	115	.impl = {
	116	.min_access_size = 4,
	117	.max_access_size = 4,
	118	},
	119	.endianness = DEVICE_NATIVE_ENDIAN,
	120	};
	121
96cd4594	122	static void puv3_pm_realize(DeviceState dev, Error *errp)
f716c197	123	{
af89a444	124	PUV3PMState *s = PUV3_PM(dev);
f716c197 GX	125
	126	s->reg_PCGR = 0x0;
	127
3c161542	128	memory_region_init_io(&s->iomem, OBJECT(s), &puv3_pm_ops, s, "puv3_pm",
f716c197	129	PUV3_REGS_OFFSET);
96cd4594	130	sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
f716c197 GX	131	}
	132
	133	static void puv3_pm_class_init(ObjectClass klass, void data)
	134	{
96cd4594	135	DeviceClass *dc = DEVICE_CLASS(klass);
f716c197	136
96cd4594	137	dc->realize = puv3_pm_realize;
f716c197 GX	138	}
	139
	140	static const TypeInfo puv3_pm_info = {
af89a444	141	.name = TYPE_PUV3_PM,
f716c197 GX	142	.parent = TYPE_SYS_BUS_DEVICE,
	143	.instance_size = sizeof(PUV3PMState),
	144	.class_init = puv3_pm_class_init,
	145	};
	146
	147	static void puv3_pm_register_type(void)
	148	{
	149	type_register_static(&puv3_pm_info);
	150	}
	151
	152	type_init(puv3_pm_register_type)