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Commit | Line | Data |
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39ac8455 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * Hypercall based emulated RTAS | |
5 | * | |
6 | * Copyright (c) 2010-2011 David Gibson, IBM Corporation. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | * | |
26 | */ | |
54d31236 | 27 | |
0d75590d | 28 | #include "qemu/osdep.h" |
39ac8455 | 29 | #include "cpu.h" |
03dd024f | 30 | #include "qemu/log.h" |
ce9863b7 | 31 | #include "qemu/error-report.h" |
9c17d615 | 32 | #include "sysemu/sysemu.h" |
9c17d615 | 33 | #include "sysemu/device_tree.h" |
db4ef288 | 34 | #include "sysemu/cpus.h" |
cf116ad4 | 35 | #include "sysemu/hw_accel.h" |
54d31236 | 36 | #include "sysemu/runstate.h" |
a84f7179 | 37 | #include "kvm_ppc.h" |
39ac8455 | 38 | |
0d09e41a PB |
39 | #include "hw/ppc/spapr.h" |
40 | #include "hw/ppc/spapr_vio.h" | |
eeddd59f | 41 | #include "hw/ppc/spapr_rtas.h" |
84369f63 | 42 | #include "hw/ppc/spapr_cpu_core.h" |
af81cf32 | 43 | #include "hw/ppc/ppc.h" |
e3943228 | 44 | #include "hw/boards.h" |
39ac8455 DG |
45 | |
46 | #include <libfdt.h> | |
8c8639df | 47 | #include "hw/ppc/spapr_drc.h" |
f348b6d1 | 48 | #include "qemu/cutils.h" |
028ec3ce | 49 | #include "trace.h" |
3f5dabce | 50 | #include "hw/ppc/fdt.h" |
cf116ad4 | 51 | #include "target/ppc/mmu-hash64.h" |
f00bed95 | 52 | #include "target/ppc/mmu-book3s-v3.h" |
8c8639df | 53 | |
ce2918cb | 54 | static void rtas_display_character(PowerPCCPU *cpu, SpaprMachineState *spapr, |
821303f5 DG |
55 | uint32_t token, uint32_t nargs, |
56 | target_ulong args, | |
57 | uint32_t nret, target_ulong rets) | |
58 | { | |
59 | uint8_t c = rtas_ld(args, 0); | |
ce2918cb | 60 | SpaprVioDevice *sdev = vty_lookup(spapr, 0); |
821303f5 DG |
61 | |
62 | if (!sdev) { | |
a64d325d | 63 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
821303f5 DG |
64 | } else { |
65 | vty_putchars(sdev, &c, sizeof(c)); | |
a64d325d | 66 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
821303f5 DG |
67 | } |
68 | } | |
69 | ||
ce2918cb | 70 | static void rtas_power_off(PowerPCCPU *cpu, SpaprMachineState *spapr, |
821303f5 DG |
71 | uint32_t token, uint32_t nargs, target_ulong args, |
72 | uint32_t nret, target_ulong rets) | |
73 | { | |
74 | if (nargs != 2 || nret != 1) { | |
a64d325d | 75 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
821303f5 DG |
76 | return; |
77 | } | |
cf83f140 | 78 | qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); |
8a9c1b77 | 79 | cpu_stop_current(); |
a64d325d | 80 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
821303f5 DG |
81 | } |
82 | ||
ce2918cb | 83 | static void rtas_system_reboot(PowerPCCPU *cpu, SpaprMachineState *spapr, |
c821a43c DG |
84 | uint32_t token, uint32_t nargs, |
85 | target_ulong args, | |
86 | uint32_t nret, target_ulong rets) | |
87 | { | |
88 | if (nargs != 0 || nret != 1) { | |
a64d325d | 89 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
c821a43c DG |
90 | return; |
91 | } | |
cf83f140 | 92 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
a64d325d | 93 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
c821a43c DG |
94 | } |
95 | ||
210b580b | 96 | static void rtas_query_cpu_stopped_state(PowerPCCPU *cpu_, |
ce2918cb | 97 | SpaprMachineState *spapr, |
a9f8ad8f DG |
98 | uint32_t token, uint32_t nargs, |
99 | target_ulong args, | |
100 | uint32_t nret, target_ulong rets) | |
101 | { | |
102 | target_ulong id; | |
0f20ba62 | 103 | PowerPCCPU *cpu; |
a9f8ad8f DG |
104 | |
105 | if (nargs != 1 || nret != 2) { | |
a64d325d | 106 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
a9f8ad8f DG |
107 | return; |
108 | } | |
109 | ||
110 | id = rtas_ld(args, 0); | |
2e886fb3 | 111 | cpu = spapr_find_cpu(id); |
05318a85 | 112 | if (cpu != NULL) { |
0f20ba62 | 113 | if (CPU(cpu)->halted) { |
a9f8ad8f DG |
114 | rtas_st(rets, 1, 0); |
115 | } else { | |
116 | rtas_st(rets, 1, 2); | |
117 | } | |
118 | ||
a64d325d | 119 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
a9f8ad8f DG |
120 | return; |
121 | } | |
122 | ||
123 | /* Didn't find a matching cpu */ | |
a64d325d | 124 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
a9f8ad8f DG |
125 | } |
126 | ||
ce2918cb | 127 | static void rtas_start_cpu(PowerPCCPU *callcpu, SpaprMachineState *spapr, |
a9f8ad8f DG |
128 | uint32_t token, uint32_t nargs, |
129 | target_ulong args, | |
130 | uint32_t nret, target_ulong rets) | |
131 | { | |
132 | target_ulong id, start, r3; | |
cf116ad4 DG |
133 | PowerPCCPU *newcpu; |
134 | CPUPPCState *env; | |
135 | PowerPCCPUClass *pcc; | |
98248918 | 136 | target_ulong lpcr; |
a9f8ad8f DG |
137 | |
138 | if (nargs != 3 || nret != 1) { | |
a64d325d | 139 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
a9f8ad8f DG |
140 | return; |
141 | } | |
142 | ||
143 | id = rtas_ld(args, 0); | |
144 | start = rtas_ld(args, 1); | |
145 | r3 = rtas_ld(args, 2); | |
146 | ||
cf116ad4 DG |
147 | newcpu = spapr_find_cpu(id); |
148 | if (!newcpu) { | |
149 | /* Didn't find a matching cpu */ | |
150 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
151 | return; | |
152 | } | |
a9f8ad8f | 153 | |
cf116ad4 DG |
154 | env = &newcpu->env; |
155 | pcc = POWERPC_CPU_GET_CLASS(newcpu); | |
a9f8ad8f | 156 | |
cf116ad4 DG |
157 | if (!CPU(newcpu)->halted) { |
158 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); | |
159 | return; | |
160 | } | |
048706d9 | 161 | |
cf116ad4 | 162 | cpu_synchronize_state(CPU(newcpu)); |
9a94ee5b | 163 | |
cf116ad4 | 164 | env->msr = (1ULL << MSR_SF) | (1ULL << MSR_ME); |
98248918 | 165 | |
cf116ad4 | 166 | /* Enable Power-saving mode Exit Cause exceptions for the new CPU */ |
47a9b551 | 167 | lpcr = env->spr[SPR_LPCR]; |
98248918 DG |
168 | if (!pcc->interrupts_big_endian(callcpu)) { |
169 | lpcr |= LPCR_ILE; | |
170 | } | |
f00bed95 DG |
171 | if (env->mmu_model == POWERPC_MMU_3_00) { |
172 | /* | |
173 | * New cpus are expected to start in the same radix/hash mode | |
174 | * as the existing CPUs | |
175 | */ | |
00fd075e BH |
176 | if (ppc64_v3_radix(callcpu)) { |
177 | lpcr |= LPCR_UPRT | LPCR_GTSE | LPCR_HR; | |
f00bed95 | 178 | } else { |
00fd075e | 179 | lpcr &= ~(LPCR_UPRT | LPCR_GTSE | LPCR_HR); |
f00bed95 | 180 | } |
70de0967 | 181 | env->spr[SPR_PSSCR] &= ~PSSCR_EC; |
f00bed95 | 182 | } |
98248918 DG |
183 | ppc_store_lpcr(newcpu, lpcr); |
184 | ||
185 | /* | |
186 | * Set the timebase offset of the new CPU to that of the invoking | |
187 | * CPU. This helps hotplugged CPU to have the correct timebase | |
188 | * offset. | |
189 | */ | |
190 | newcpu->env.tb_env->tb_offset = callcpu->env.tb_env->tb_offset; | |
9a94ee5b | 191 | |
84369f63 | 192 | spapr_cpu_set_entry_state(newcpu, start, r3); |
a9f8ad8f | 193 | |
cf116ad4 | 194 | qemu_cpu_kick(CPU(newcpu)); |
a9f8ad8f | 195 | |
cf116ad4 | 196 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
a9f8ad8f DG |
197 | } |
198 | ||
ce2918cb | 199 | static void rtas_stop_self(PowerPCCPU *cpu, SpaprMachineState *spapr, |
59760f2d AK |
200 | uint32_t token, uint32_t nargs, |
201 | target_ulong args, | |
202 | uint32_t nret, target_ulong rets) | |
203 | { | |
204 | CPUState *cs = CPU(cpu); | |
205 | CPUPPCState *env = &cpu->env; | |
9a94ee5b | 206 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); |
59760f2d | 207 | |
9a94ee5b CLG |
208 | /* Disable Power-saving mode Exit Cause exceptions for the CPU. |
209 | * This could deliver an interrupt on a dying CPU and crash the | |
70de0967 SJS |
210 | * guest. |
211 | * For the same reason, set PSSCR_EC. | |
212 | */ | |
cf116ad4 | 213 | ppc_store_lpcr(cpu, env->spr[SPR_LPCR] & ~pcc->lpcr_pm); |
70de0967 | 214 | env->spr[SPR_PSSCR] |= PSSCR_EC; |
cf116ad4 | 215 | cs->halted = 1; |
a84f7179 | 216 | kvmppc_set_reg_ppc_online(cpu, 0); |
cf116ad4 | 217 | qemu_cpu_kick(cs); |
59760f2d AK |
218 | } |
219 | ||
93eac7b8 NP |
220 | static void rtas_ibm_suspend_me(PowerPCCPU *cpu, SpaprMachineState *spapr, |
221 | uint32_t token, uint32_t nargs, | |
222 | target_ulong args, | |
223 | uint32_t nret, target_ulong rets) | |
224 | { | |
225 | CPUState *cs; | |
226 | ||
227 | if (nargs != 0 || nret != 1) { | |
228 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
229 | return; | |
230 | } | |
231 | ||
232 | CPU_FOREACH(cs) { | |
233 | PowerPCCPU *c = POWERPC_CPU(cs); | |
234 | CPUPPCState *e = &c->env; | |
235 | if (c == cpu) { | |
236 | continue; | |
237 | } | |
238 | ||
239 | /* See h_join */ | |
240 | if (!cs->halted || (e->msr & (1ULL << MSR_EE))) { | |
241 | rtas_st(rets, 0, H_MULTI_THREADS_ACTIVE); | |
242 | return; | |
243 | } | |
244 | } | |
245 | ||
246 | qemu_system_suspend_request(); | |
247 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); | |
248 | } | |
249 | ||
c920f7b4 DG |
250 | static inline int sysparm_st(target_ulong addr, target_ulong len, |
251 | const void *val, uint16_t vallen) | |
252 | { | |
253 | hwaddr phys = ppc64_phys_to_real(addr); | |
254 | ||
255 | if (len < 2) { | |
256 | return RTAS_OUT_SYSPARM_PARAM_ERROR; | |
257 | } | |
258 | stw_be_phys(&address_space_memory, phys, vallen); | |
259 | cpu_physical_memory_write(phys + 2, val, MIN(len - 2, vallen)); | |
260 | return RTAS_OUT_SUCCESS; | |
261 | } | |
262 | ||
3ada6b11 | 263 | static void rtas_ibm_get_system_parameter(PowerPCCPU *cpu, |
ce2918cb | 264 | SpaprMachineState *spapr, |
3ada6b11 AK |
265 | uint32_t token, uint32_t nargs, |
266 | target_ulong args, | |
267 | uint32_t nret, target_ulong rets) | |
268 | { | |
289af4ac | 269 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); |
fe6b6346 LX |
270 | MachineState *ms = MACHINE(qdev_get_machine()); |
271 | unsigned int max_cpus = ms->smp.max_cpus; | |
3ada6b11 AK |
272 | target_ulong parameter = rtas_ld(args, 0); |
273 | target_ulong buffer = rtas_ld(args, 1); | |
274 | target_ulong length = rtas_ld(args, 2); | |
c920f7b4 | 275 | target_ulong ret; |
3ada6b11 AK |
276 | |
277 | switch (parameter) { | |
3b50d897 | 278 | case RTAS_SYSPARM_SPLPAR_CHARACTERISTICS: { |
e3943228 | 279 | char *param_val = g_strdup_printf("MaxEntCap=%d," |
ab3dd749 | 280 | "DesMem=%" PRIu64 "," |
e3943228 SB |
281 | "DesProcs=%d," |
282 | "MaxPlatProcs=%d", | |
283 | max_cpus, | |
d23b6caa | 284 | current_machine->ram_size / MiB, |
fe6b6346 | 285 | ms->smp.cpus, |
e3943228 | 286 | max_cpus); |
289af4ac SJS |
287 | if (pcc->n_host_threads > 0) { |
288 | char *hostthr_val, *old = param_val; | |
289 | ||
290 | /* | |
291 | * Add HostThrs property. This property is not present in PAPR but | |
292 | * is expected by some guests to communicate the number of physical | |
293 | * host threads per core on the system so that they can scale | |
294 | * information which varies based on the thread configuration. | |
295 | */ | |
296 | hostthr_val = g_strdup_printf(",HostThrs=%d", pcc->n_host_threads); | |
297 | param_val = g_strconcat(param_val, hostthr_val, NULL); | |
298 | g_free(hostthr_val); | |
299 | g_free(old); | |
300 | } | |
c920f7b4 | 301 | ret = sysparm_st(buffer, length, param_val, strlen(param_val) + 1); |
3b50d897 S |
302 | g_free(param_val); |
303 | break; | |
304 | } | |
3052d951 S |
305 | case RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE: { |
306 | uint8_t param_val = DIAGNOSTICS_RUN_MODE_DISABLED; | |
307 | ||
c920f7b4 | 308 | ret = sysparm_st(buffer, length, ¶m_val, sizeof(param_val)); |
3ada6b11 AK |
309 | break; |
310 | } | |
b907d7b0 | 311 | case RTAS_SYSPARM_UUID: |
9c5ce8db FZ |
312 | ret = sysparm_st(buffer, length, (unsigned char *)&qemu_uuid, |
313 | (qemu_uuid_set ? 16 : 0)); | |
b907d7b0 | 314 | break; |
3052d951 S |
315 | default: |
316 | ret = RTAS_OUT_NOT_SUPPORTED; | |
317 | } | |
3ada6b11 AK |
318 | |
319 | rtas_st(rets, 0, ret); | |
320 | } | |
321 | ||
322 | static void rtas_ibm_set_system_parameter(PowerPCCPU *cpu, | |
ce2918cb | 323 | SpaprMachineState *spapr, |
3ada6b11 AK |
324 | uint32_t token, uint32_t nargs, |
325 | target_ulong args, | |
326 | uint32_t nret, target_ulong rets) | |
327 | { | |
328 | target_ulong parameter = rtas_ld(args, 0); | |
329 | target_ulong ret = RTAS_OUT_NOT_SUPPORTED; | |
330 | ||
331 | switch (parameter) { | |
3b50d897 | 332 | case RTAS_SYSPARM_SPLPAR_CHARACTERISTICS: |
3052d951 | 333 | case RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE: |
b907d7b0 | 334 | case RTAS_SYSPARM_UUID: |
3ada6b11 AK |
335 | ret = RTAS_OUT_NOT_AUTHORIZED; |
336 | break; | |
337 | } | |
338 | ||
339 | rtas_st(rets, 0, ret); | |
340 | } | |
341 | ||
2e14072f | 342 | static void rtas_ibm_os_term(PowerPCCPU *cpu, |
ce2918cb | 343 | SpaprMachineState *spapr, |
2e14072f ND |
344 | uint32_t token, uint32_t nargs, |
345 | target_ulong args, | |
346 | uint32_t nret, target_ulong rets) | |
347 | { | |
2c553477 | 348 | qemu_system_guest_panicked(NULL); |
2e14072f | 349 | |
2c553477 | 350 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
2e14072f ND |
351 | } |
352 | ||
ce2918cb | 353 | static void rtas_set_power_level(PowerPCCPU *cpu, SpaprMachineState *spapr, |
094d2058 NF |
354 | uint32_t token, uint32_t nargs, |
355 | target_ulong args, uint32_t nret, | |
356 | target_ulong rets) | |
357 | { | |
358 | int32_t power_domain; | |
359 | ||
360 | if (nargs != 2 || nret != 2) { | |
361 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
362 | return; | |
363 | } | |
364 | ||
365 | /* we currently only use a single, "live insert" powerdomain for | |
366 | * hotplugged/dlpar'd resources, so the power is always live/full (100) | |
367 | */ | |
368 | power_domain = rtas_ld(args, 0); | |
369 | if (power_domain != -1) { | |
370 | rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); | |
371 | return; | |
372 | } | |
373 | ||
374 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); | |
375 | rtas_st(rets, 1, 100); | |
376 | } | |
377 | ||
ce2918cb | 378 | static void rtas_get_power_level(PowerPCCPU *cpu, SpaprMachineState *spapr, |
094d2058 NF |
379 | uint32_t token, uint32_t nargs, |
380 | target_ulong args, uint32_t nret, | |
381 | target_ulong rets) | |
382 | { | |
383 | int32_t power_domain; | |
384 | ||
385 | if (nargs != 1 || nret != 2) { | |
386 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
387 | return; | |
388 | } | |
389 | ||
390 | /* we currently only use a single, "live insert" powerdomain for | |
391 | * hotplugged/dlpar'd resources, so the power is always live/full (100) | |
392 | */ | |
393 | power_domain = rtas_ld(args, 0); | |
394 | if (power_domain != -1) { | |
395 | rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); | |
396 | return; | |
397 | } | |
398 | ||
399 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); | |
400 | rtas_st(rets, 1, 100); | |
401 | } | |
402 | ||
39ac8455 DG |
403 | static struct rtas_call { |
404 | const char *name; | |
405 | spapr_rtas_fn fn; | |
3a3b8502 | 406 | } rtas_table[RTAS_TOKEN_MAX - RTAS_TOKEN_BASE]; |
39ac8455 | 407 | |
ce2918cb | 408 | target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *spapr, |
39ac8455 DG |
409 | uint32_t token, uint32_t nargs, target_ulong args, |
410 | uint32_t nret, target_ulong rets) | |
411 | { | |
3a3b8502 AK |
412 | if ((token >= RTAS_TOKEN_BASE) && (token < RTAS_TOKEN_MAX)) { |
413 | struct rtas_call *call = rtas_table + (token - RTAS_TOKEN_BASE); | |
39ac8455 DG |
414 | |
415 | if (call->fn) { | |
210b580b | 416 | call->fn(cpu, spapr, token, nargs, args, nret, rets); |
39ac8455 DG |
417 | return H_SUCCESS; |
418 | } | |
419 | } | |
420 | ||
821303f5 DG |
421 | /* HACK: Some Linux early debug code uses RTAS display-character, |
422 | * but assumes the token value is 0xa (which it is on some real | |
423 | * machines) without looking it up in the device tree. This | |
424 | * special case makes this work */ | |
425 | if (token == 0xa) { | |
210b580b | 426 | rtas_display_character(cpu, spapr, 0xa, nargs, args, nret, rets); |
821303f5 DG |
427 | return H_SUCCESS; |
428 | } | |
429 | ||
39ac8455 | 430 | hcall_dprintf("Unknown RTAS token 0x%x\n", token); |
a64d325d | 431 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
39ac8455 DG |
432 | return H_PARAMETER; |
433 | } | |
434 | ||
eeddd59f LV |
435 | uint64_t qtest_rtas_call(char *cmd, uint32_t nargs, uint64_t args, |
436 | uint32_t nret, uint64_t rets) | |
437 | { | |
438 | int token; | |
439 | ||
440 | for (token = 0; token < RTAS_TOKEN_MAX - RTAS_TOKEN_BASE; token++) { | |
441 | if (strcmp(cmd, rtas_table[token].name) == 0) { | |
ce2918cb | 442 | SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
eeddd59f LV |
443 | PowerPCCPU *cpu = POWERPC_CPU(first_cpu); |
444 | ||
445 | rtas_table[token].fn(cpu, spapr, token + RTAS_TOKEN_BASE, | |
446 | nargs, args, nret, rets); | |
447 | return H_SUCCESS; | |
448 | } | |
449 | } | |
450 | return H_PARAMETER; | |
451 | } | |
452 | ||
3a3b8502 | 453 | void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn) |
39ac8455 | 454 | { |
adf9ac50 | 455 | assert((token >= RTAS_TOKEN_BASE) && (token < RTAS_TOKEN_MAX)); |
c89d5299 | 456 | |
3a3b8502 | 457 | token -= RTAS_TOKEN_BASE; |
adf9ac50 | 458 | |
64db6c70 | 459 | assert(!name || !rtas_table[token].name); |
39ac8455 | 460 | |
3a3b8502 AK |
461 | rtas_table[token].name = name; |
462 | rtas_table[token].fn = fn; | |
39ac8455 DG |
463 | } |
464 | ||
3f5dabce | 465 | void spapr_dt_rtas_tokens(void *fdt, int rtas) |
39ac8455 | 466 | { |
39ac8455 DG |
467 | int i; |
468 | ||
3a3b8502 | 469 | for (i = 0; i < RTAS_TOKEN_MAX - RTAS_TOKEN_BASE; i++) { |
39ac8455 DG |
470 | struct rtas_call *call = &rtas_table[i]; |
471 | ||
d36b66f7 | 472 | if (!call->name) { |
39ac8455 DG |
473 | continue; |
474 | } | |
475 | ||
3f5dabce | 476 | _FDT(fdt_setprop_cell(fdt, rtas, call->name, i + RTAS_TOKEN_BASE)); |
39ac8455 | 477 | } |
39ac8455 | 478 | } |
821303f5 | 479 | |
83f7d43a | 480 | static void core_rtas_register_types(void) |
821303f5 | 481 | { |
3a3b8502 AK |
482 | spapr_rtas_register(RTAS_DISPLAY_CHARACTER, "display-character", |
483 | rtas_display_character); | |
3a3b8502 AK |
484 | spapr_rtas_register(RTAS_POWER_OFF, "power-off", rtas_power_off); |
485 | spapr_rtas_register(RTAS_SYSTEM_REBOOT, "system-reboot", | |
486 | rtas_system_reboot); | |
487 | spapr_rtas_register(RTAS_QUERY_CPU_STOPPED_STATE, "query-cpu-stopped-state", | |
a9f8ad8f | 488 | rtas_query_cpu_stopped_state); |
3a3b8502 AK |
489 | spapr_rtas_register(RTAS_START_CPU, "start-cpu", rtas_start_cpu); |
490 | spapr_rtas_register(RTAS_STOP_SELF, "stop-self", rtas_stop_self); | |
93eac7b8 NP |
491 | spapr_rtas_register(RTAS_IBM_SUSPEND_ME, "ibm,suspend-me", |
492 | rtas_ibm_suspend_me); | |
3a3b8502 AK |
493 | spapr_rtas_register(RTAS_IBM_GET_SYSTEM_PARAMETER, |
494 | "ibm,get-system-parameter", | |
3ada6b11 | 495 | rtas_ibm_get_system_parameter); |
3a3b8502 AK |
496 | spapr_rtas_register(RTAS_IBM_SET_SYSTEM_PARAMETER, |
497 | "ibm,set-system-parameter", | |
3ada6b11 | 498 | rtas_ibm_set_system_parameter); |
2e14072f ND |
499 | spapr_rtas_register(RTAS_IBM_OS_TERM, "ibm,os-term", |
500 | rtas_ibm_os_term); | |
094d2058 NF |
501 | spapr_rtas_register(RTAS_SET_POWER_LEVEL, "set-power-level", |
502 | rtas_set_power_level); | |
503 | spapr_rtas_register(RTAS_GET_POWER_LEVEL, "get-power-level", | |
504 | rtas_get_power_level); | |
821303f5 | 505 | } |
83f7d43a AF |
506 | |
507 | type_init(core_rtas_register_types) |