projects / qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 6af0bf9c FB |
1 | #if !defined(__QEMU_MIPS_EXEC_H__) |
| 2 | #define __QEMU_MIPS_EXEC_H__ | |
| 3 | ||
| 01dbbdf1 | 4 | //#define DEBUG_OP |
| 6af0bf9c | 5 | |
| c570fd16 | 6 | #include "config.h" |
| 6af0bf9c FB |
7 | #include "mips-defs.h" |
| 8 | #include "dyngen-exec.h" | |
| 01179c38 | 9 | #include "cpu-defs.h" |
| 6af0bf9c FB |
10 | |
| 11 | register struct CPUMIPSState *env asm(AREG0); | |
| 12 | ||
| 6af0bf9c | 13 | #include "cpu.h" |
| 6af0bf9c FB |
14 | |
| 15 | #if !defined(CONFIG_USER_ONLY) | |
| a9049a07 | 16 | #include "softmmu_exec.h" |
| 6af0bf9c FB |
17 | #endif /* !defined(CONFIG_USER_ONLY) */ |
| 18 | ||
| c904ef0e | 19 | static inline void compute_hflags(CPUState *env) |
| 08fa4bab | 20 | { |
| b8aa4598 | 21 | env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | |
| 2623c1ec AJ |
22 | MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | |
| 23 | MIPS_HFLAG_UX); | |
| 08fa4bab TS |
24 | if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
| 25 | !(env->CP0_Status & (1 << CP0St_ERL)) && | |
| 671880e6 | 26 | !(env->hflags & MIPS_HFLAG_DM)) { |
| 623a930e | 27 | env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU; |
| 671880e6 | 28 | } |
| d26bc211 | 29 | #if defined(TARGET_MIPS64) |
| 623a930e | 30 | if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) || |
| 08fa4bab TS |
31 | (env->CP0_Status & (1 << CP0St_PX)) || |
| 32 | (env->CP0_Status & (1 << CP0St_UX))) | |
| 33 | env->hflags |= MIPS_HFLAG_64; | |
| 2623c1ec AJ |
34 | if (env->CP0_Status & (1 << CP0St_UX)) |
| 35 | env->hflags |= MIPS_HFLAG_UX; | |
| 08fa4bab | 36 | #endif |
| 671880e6 | 37 | if ((env->CP0_Status & (1 << CP0St_CU0)) || |
| 623a930e | 38 | !(env->hflags & MIPS_HFLAG_KSU)) |
| 08fa4bab TS |
39 | env->hflags |= MIPS_HFLAG_CP0; |
| 40 | if (env->CP0_Status & (1 << CP0St_CU1)) | |
| 41 | env->hflags |= MIPS_HFLAG_FPU; | |
| 42 | if (env->CP0_Status & (1 << CP0St_FR)) | |
| 43 | env->hflags |= MIPS_HFLAG_F64; | |
| b8aa4598 | 44 | if (env->insn_flags & ISA_MIPS32R2) { |
| f01be154 | 45 | if (env->active_fpu.fcr0 & (1 << FCR0_F64)) |
| b8aa4598 TS |
46 | env->hflags |= MIPS_HFLAG_COP1X; |
| 47 | } else if (env->insn_flags & ISA_MIPS32) { | |
| 48 | if (env->hflags & MIPS_HFLAG_64) | |
| 49 | env->hflags |= MIPS_HFLAG_COP1X; | |
| 50 | } else if (env->insn_flags & ISA_MIPS4) { | |
| 51 | /* All supported MIPS IV CPUs use the XX (CU3) to enable | |
| 52 | and disable the MIPS IV extensions to the MIPS III ISA. | |
| 53 | Some other MIPS IV CPUs ignore the bit, so the check here | |
| 54 | would be too restrictive for them. */ | |
| 55 | if (env->CP0_Status & (1 << CP0St_CU3)) | |
| 56 | env->hflags |= MIPS_HFLAG_COP1X; | |
| 57 | } | |
| 08fa4bab TS |
58 | } |
| 59 | ||
| 6af0bf9c | 60 | #endif /* !defined(__QEMU_MIPS_EXEC_H__) */ |