[qemu.git] / hw / sd / milkymist-memcard.c

/*
 *  QEMU model of the Milkymist SD Card Controller.
 *
 *  Copyright (c) 2010 Michael Walle <[email protected]>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 *
 *
 * Specification available at:
 *   http://milkymist.walle.cc/socdoc/memcard.pdf
 */

#include "qemu/osdep.h"
#include "qemu/log.h"
#include "hw/hw.h"
#include "hw/sysbus.h"
#include "sysemu/sysemu.h"
#include "trace.h"
#include "include/qapi/error.h"
#include "sysemu/block-backend.h"
#include "sysemu/blockdev.h"
#include "hw/sd/sd.h"

enum {
    ENABLE_CMD_TX   = (1<<0),
    ENABLE_CMD_RX   = (1<<1),
    ENABLE_DAT_TX   = (1<<2),
    ENABLE_DAT_RX   = (1<<3),
};

enum {
    PENDING_CMD_TX   = (1<<0),
    PENDING_CMD_RX   = (1<<1),
    PENDING_DAT_TX   = (1<<2),
    PENDING_DAT_RX   = (1<<3),
};

enum {
    START_CMD_TX    = (1<<0),
    START_DAT_RX    = (1<<1),
};

enum {
    R_CLK2XDIV = 0,
    R_ENABLE,
    R_PENDING,
    R_START,
    R_CMD,
    R_DAT,
    R_MAX
};

#define TYPE_MILKYMIST_MEMCARD "milkymist-memcard"
#define MILKYMIST_MEMCARD(obj) \
    OBJECT_CHECK(MilkymistMemcardState, (obj), TYPE_MILKYMIST_MEMCARD)

struct MilkymistMemcardState {
    SysBusDevice parent_obj;

    MemoryRegion regs_region;
    SDBus sdbus;

    int command_write_ptr;
    int response_read_ptr;
    int response_len;
    int ignore_next_cmd;
    int enabled;
    uint8_t command[6];
    uint8_t response[17];
    uint32_t regs[R_MAX];
};
typedef struct MilkymistMemcardState MilkymistMemcardState;

static void update_pending_bits(MilkymistMemcardState *s)
{
    /* transmits are instantaneous, thus tx pending bits are never set */
    s->regs[R_PENDING] = 0;
    /* if rx is enabled the corresponding pending bits are always set */
    if (s->regs[R_ENABLE] & ENABLE_CMD_RX) {
        s->regs[R_PENDING] |= PENDING_CMD_RX;
    }
    if (s->regs[R_ENABLE] & ENABLE_DAT_RX) {
        s->regs[R_PENDING] |= PENDING_DAT_RX;
    }
}

static void memcard_sd_command(MilkymistMemcardState *s)
{
    SDRequest req;

    req.cmd = s->command[0] & 0x3f;
    req.arg = (s->command[1] << 24) | (s->command[2] << 16)
              | (s->command[3] << 8) | s->command[4];
    req.crc = s->command[5];

    s->response[0] = req.cmd;
    s->response_len = sdbus_do_command(&s->sdbus, &req, s->response + 1);
    s->response_read_ptr = 0;

    if (s->response_len == 16) {
        /* R2 response */
        s->response[0] = 0x3f;
        s->response_len += 1;
    } else if (s->response_len == 4) {
        /* no crc calculation, insert dummy byte */
        s->response[5] = 0;
        s->response_len += 2;
    }

    if (req.cmd == 0) {
        /* next write is a dummy byte to clock the initialization of the sd
         * card */
        s->ignore_next_cmd = 1;
    }
}

static uint64_t memcard_read(void *opaque, hwaddr addr,
                             unsigned size)
{
    MilkymistMemcardState *s = opaque;
    uint32_t r = 0;

    addr >>= 2;
    switch (addr) {
    case R_CMD:
        if (!s->enabled) {
            r = 0xff;
        } else {
            r = s->response[s->response_read_ptr++];
            if (s->response_read_ptr > s->response_len) {
                qemu_log_mask(LOG_GUEST_ERROR, "milkymist_memcard: "
                              "read more cmd bytes than available. Clipping.");
                s->response_read_ptr = 0;
            }
        }
        break;
    case R_DAT:
        if (!s->enabled) {
            r = 0xffffffff;
        } else {
            r = 0;
            r |= sdbus_read_data(&s->sdbus) << 24;
            r |= sdbus_read_data(&s->sdbus) << 16;
            r |= sdbus_read_data(&s->sdbus) << 8;
            r |= sdbus_read_data(&s->sdbus);
        }
        break;
    case R_CLK2XDIV:
    case R_ENABLE:
    case R_PENDING:
    case R_START:
        r = s->regs[addr];
        break;

    default:
        qemu_log_mask(LOG_UNIMP, "milkymist_memcard: "
                      "read access to unknown register 0x%" HWADDR_PRIx "\n",
                      addr << 2);
        break;
    }

    trace_milkymist_memcard_memory_read(addr << 2, r);

    return r;
}

static void memcard_write(void *opaque, hwaddr addr, uint64_t value,
                          unsigned size)
{
    MilkymistMemcardState *s = opaque;

    trace_milkymist_memcard_memory_write(addr, value);

    addr >>= 2;
    switch (addr) {
    case R_PENDING:
        /* clear rx pending bits */
        s->regs[R_PENDING] &= ~(value & (PENDING_CMD_RX | PENDING_DAT_RX));
        update_pending_bits(s);
        break;
    case R_CMD:
        if (!s->enabled) {
            break;
        }
        if (s->ignore_next_cmd) {
            s->ignore_next_cmd = 0;
            break;
        }
        s->command[s->command_write_ptr] = value & 0xff;
        s->command_write_ptr = (s->command_write_ptr + 1) % 6;
        if (s->command_write_ptr == 0) {
            memcard_sd_command(s);
        }
        break;
    case R_DAT:
        if (!s->enabled) {
            break;
        }
        sdbus_write_data(&s->sdbus, (value >> 24) & 0xff);
        sdbus_write_data(&s->sdbus, (value >> 16) & 0xff);
        sdbus_write_data(&s->sdbus, (value >> 8) & 0xff);
        sdbus_write_data(&s->sdbus, value & 0xff);
        break;
    case R_ENABLE:
        s->regs[addr] = value;
        update_pending_bits(s);
        break;
    case R_CLK2XDIV:
    case R_START:
        s->regs[addr] = value;
        break;

    default:
        qemu_log_mask(LOG_UNIMP, "milkymist_memcard: "
                      "write access to unknown register 0x%" HWADDR_PRIx " "
                      "(value 0x%" PRIx64 ")\n", addr << 2, value);
        break;
    }
}

static const MemoryRegionOps memcard_mmio_ops = {
    .read = memcard_read,
    .write = memcard_write,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void milkymist_memcard_reset(DeviceState *d)
{
    MilkymistMemcardState *s = MILKYMIST_MEMCARD(d);
    int i;

    s->command_write_ptr = 0;
    s->response_read_ptr = 0;
    s->response_len = 0;

    for (i = 0; i < R_MAX; i++) {
        s->regs[i] = 0;
    }
}

static void milkymist_memcard_init(Object *obj)
{
    MilkymistMemcardState *s = MILKYMIST_MEMCARD(obj);
    SysBusDevice *dev = SYS_BUS_DEVICE(obj);

    memory_region_init_io(&s->regs_region, OBJECT(s), &memcard_mmio_ops, s,
            "milkymist-memcard", R_MAX * 4);
    sysbus_init_mmio(dev, &s->regs_region);
}

static void milkymist_memcard_realize(DeviceState *dev, Error **errp)
{
    MilkymistMemcardState *s = MILKYMIST_MEMCARD(dev);
    DeviceState *carddev;
    BlockBackend *blk;
    DriveInfo *dinfo;
    Error *err = NULL;

    qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS,
                        dev, "sd-bus");

    /* Create and plug in the sd card */
    /* FIXME use a qdev drive property instead of drive_get_next() */
    dinfo = drive_get_next(IF_SD);
    blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
    carddev = qdev_create(&s->sdbus.qbus, TYPE_SD_CARD);
    qdev_prop_set_drive(carddev, "drive", blk, &err);
    object_property_set_bool(OBJECT(carddev), true, "realized", &err);
    if (err) {
        error_setg(errp, "failed to init SD card: %s", error_get_pretty(err));
        return;
    }
    s->enabled = blk && blk_is_inserted(blk);
}

static const VMStateDescription vmstate_milkymist_memcard = {
    .name = "milkymist-memcard",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_INT32(command_write_ptr, MilkymistMemcardState),
        VMSTATE_INT32(response_read_ptr, MilkymistMemcardState),
        VMSTATE_INT32(response_len, MilkymistMemcardState),
        VMSTATE_INT32(ignore_next_cmd, MilkymistMemcardState),
        VMSTATE_INT32(enabled, MilkymistMemcardState),
        VMSTATE_UINT8_ARRAY(command, MilkymistMemcardState, 6),
        VMSTATE_UINT8_ARRAY(response, MilkymistMemcardState, 17),
        VMSTATE_UINT32_ARRAY(regs, MilkymistMemcardState, R_MAX),
        VMSTATE_END_OF_LIST()
    }
};

static void milkymist_memcard_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = milkymist_memcard_realize;
    dc->reset = milkymist_memcard_reset;
    dc->vmsd = &vmstate_milkymist_memcard;
    /* Reason: init() method uses drive_get_next() */
    dc->user_creatable = false;
}

static const TypeInfo milkymist_memcard_info = {
    .name          = TYPE_MILKYMIST_MEMCARD,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(MilkymistMemcardState),
    .instance_init = milkymist_memcard_init,
    .class_init    = milkymist_memcard_class_init,
};

static void milkymist_memcard_register_types(void)
{
    type_register_static(&milkymist_memcard_info);
}

type_init(milkymist_memcard_register_types)
Commit	Line	Data
b4e37d98 MW	1	/*
	2	* QEMU model of the Milkymist SD Card Controller.
	3	*
	4	* Copyright (c) 2010 Michael Walle <[email protected]>
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*
	19	*
	20	* Specification available at:
6dbbe243	21	* http://milkymist.walle.cc/socdoc/memcard.pdf
b4e37d98 MW	22	*/
b4e37d98 MW	23
ea99dde1	24	#include "qemu/osdep.h"
d9f98aab	25	#include "qemu/log.h"
83c9f4ca PB	26	#include "hw/hw.h"
83c9f4ca PB	27	#include "hw/sysbus.h"
9c17d615	28	#include "sysemu/sysemu.h"
b4e37d98	29	#include "trace.h"
d9f98aab	30	#include "include/qapi/error.h"
fa1d36df	31	#include "sysemu/block-backend.h"
9c17d615	32	#include "sysemu/blockdev.h"
e3382ef0	33	#include "hw/sd/sd.h"
b4e37d98 MW	34
	35	enum {
	36	ENABLE_CMD_TX = (1<<0),
	37	ENABLE_CMD_RX = (1<<1),
	38	ENABLE_DAT_TX = (1<<2),
	39	ENABLE_DAT_RX = (1<<3),
	40	};
	41
	42	enum {
	43	PENDING_CMD_TX = (1<<0),
	44	PENDING_CMD_RX = (1<<1),
	45	PENDING_DAT_TX = (1<<2),
	46	PENDING_DAT_RX = (1<<3),
	47	};
	48
	49	enum {
	50	START_CMD_TX = (1<<0),
	51	START_DAT_RX = (1<<1),
	52	};
	53
	54	enum {
	55	R_CLK2XDIV = 0,
	56	R_ENABLE,
	57	R_PENDING,
	58	R_START,
	59	R_CMD,
	60	R_DAT,
	61	R_MAX
	62	};
	63
7a239e46 AF	64	#define TYPE_MILKYMIST_MEMCARD "milkymist-memcard"
	65	#define MILKYMIST_MEMCARD(obj) \
	66	OBJECT_CHECK(MilkymistMemcardState, (obj), TYPE_MILKYMIST_MEMCARD)
	67
b4e37d98	68	struct MilkymistMemcardState {
7a239e46 AF	69	SysBusDevice parent_obj;
7a239e46 AF	70
8c85d15b	71	MemoryRegion regs_region;
3d0369ba	72	SDBus sdbus;
b4e37d98 MW	73
	74	int command_write_ptr;
	75	int response_read_ptr;
	76	int response_len;
	77	int ignore_next_cmd;
	78	int enabled;
	79	uint8_t command[6];
	80	uint8_t response[17];
	81	uint32_t regs[R_MAX];
	82	};
	83	typedef struct MilkymistMemcardState MilkymistMemcardState;
	84
	85	static void update_pending_bits(MilkymistMemcardState *s)
	86	{
	87	/* transmits are instantaneous, thus tx pending bits are never set */
	88	s->regs[R_PENDING] = 0;
	89	/* if rx is enabled the corresponding pending bits are always set */
	90	if (s->regs[R_ENABLE] & ENABLE_CMD_RX) {
	91	s->regs[R_PENDING] \|= PENDING_CMD_RX;
	92	}
	93	if (s->regs[R_ENABLE] & ENABLE_DAT_RX) {
	94	s->regs[R_PENDING] \|= PENDING_DAT_RX;
	95	}
	96	}
	97
	98	static void memcard_sd_command(MilkymistMemcardState *s)
	99	{
	100	SDRequest req;
	101
	102	req.cmd = s->command[0] & 0x3f;
	103	req.arg = (s->command[1] << 24) \| (s->command[2] << 16)
	104	\| (s->command[3] << 8) \| s->command[4];
	105	req.crc = s->command[5];
	106
	107	s->response[0] = req.cmd;
3d0369ba	108	s->response_len = sdbus_do_command(&s->sdbus, &req, s->response + 1);
b4e37d98 MW	109	s->response_read_ptr = 0;
	110
	111	if (s->response_len == 16) {
	112	/* R2 response */
	113	s->response[0] = 0x3f;
	114	s->response_len += 1;
	115	} else if (s->response_len == 4) {
	116	/* no crc calculation, insert dummy byte */
	117	s->response[5] = 0;
	118	s->response_len += 2;
	119	}
	120
	121	if (req.cmd == 0) {
	122	/* next write is a dummy byte to clock the initialization of the sd
	123	* card */
	124	s->ignore_next_cmd = 1;
	125	}
	126	}
	127
a8170e5e	128	static uint64_t memcard_read(void *opaque, hwaddr addr,
8c85d15b	129	unsigned size)
b4e37d98 MW	130	{
	131	MilkymistMemcardState *s = opaque;
	132	uint32_t r = 0;
	133
	134	addr >>= 2;
	135	switch (addr) {
	136	case R_CMD:
	137	if (!s->enabled) {
	138	r = 0xff;
	139	} else {
	140	r = s->response[s->response_read_ptr++];
	141	if (s->response_read_ptr > s->response_len) {
d9f98aab PMD	142	qemu_log_mask(LOG_GUEST_ERROR, "milkymist_memcard: "
d9f98aab PMD	143	"read more cmd bytes than available. Clipping.");
b4e37d98 MW	144	s->response_read_ptr = 0;
	145	}
	146	}
	147	break;
	148	case R_DAT:
	149	if (!s->enabled) {
	150	r = 0xffffffff;
	151	} else {
	152	r = 0;
3d0369ba PMD	153	r \|= sdbus_read_data(&s->sdbus) << 24;
	154	r \|= sdbus_read_data(&s->sdbus) << 16;
	155	r \|= sdbus_read_data(&s->sdbus) << 8;
	156	r \|= sdbus_read_data(&s->sdbus);
b4e37d98 MW	157	}
	158	break;
	159	case R_CLK2XDIV:
	160	case R_ENABLE:
	161	case R_PENDING:
	162	case R_START:
	163	r = s->regs[addr];
	164	break;
	165
	166	default:
d9f98aab PMD	167	qemu_log_mask(LOG_UNIMP, "milkymist_memcard: "
	168	"read access to unknown register 0x%" HWADDR_PRIx "\n",
	169	addr << 2);
b4e37d98 MW	170	break;
	171	}
	172
	173	trace_milkymist_memcard_memory_read(addr << 2, r);
	174
	175	return r;
	176	}
	177
a8170e5e	178	static void memcard_write(void *opaque, hwaddr addr, uint64_t value,
8c85d15b	179	unsigned size)
b4e37d98 MW	180	{
	181	MilkymistMemcardState *s = opaque;
	182
	183	trace_milkymist_memcard_memory_write(addr, value);
	184
	185	addr >>= 2;
	186	switch (addr) {
	187	case R_PENDING:
	188	/* clear rx pending bits */
	189	s->regs[R_PENDING] &= ~(value & (PENDING_CMD_RX \| PENDING_DAT_RX));
	190	update_pending_bits(s);
	191	break;
	192	case R_CMD:
	193	if (!s->enabled) {
	194	break;
	195	}
	196	if (s->ignore_next_cmd) {
	197	s->ignore_next_cmd = 0;
	198	break;
	199	}
	200	s->command[s->command_write_ptr] = value & 0xff;
	201	s->command_write_ptr = (s->command_write_ptr + 1) % 6;
	202	if (s->command_write_ptr == 0) {
	203	memcard_sd_command(s);
	204	}
	205	break;
	206	case R_DAT:
	207	if (!s->enabled) {
	208	break;
	209	}
3d0369ba PMD	210	sdbus_write_data(&s->sdbus, (value >> 24) & 0xff);
	211	sdbus_write_data(&s->sdbus, (value >> 16) & 0xff);
	212	sdbus_write_data(&s->sdbus, (value >> 8) & 0xff);
	213	sdbus_write_data(&s->sdbus, value & 0xff);
b4e37d98 MW	214	break;
	215	case R_ENABLE:
	216	s->regs[addr] = value;
	217	update_pending_bits(s);
	218	break;
	219	case R_CLK2XDIV:
	220	case R_START:
	221	s->regs[addr] = value;
	222	break;
	223
	224	default:
d9f98aab PMD	225	qemu_log_mask(LOG_UNIMP, "milkymist_memcard: "
	226	"write access to unknown register 0x%" HWADDR_PRIx " "
	227	"(value 0x%" PRIx64 ")\n", addr << 2, value);
b4e37d98 MW	228	break;
	229	}
	230	}
	231
8c85d15b MW	232	static const MemoryRegionOps memcard_mmio_ops = {
	233	.read = memcard_read,
	234	.write = memcard_write,
	235	.valid = {
	236	.min_access_size = 4,
	237	.max_access_size = 4,
	238	},
	239	.endianness = DEVICE_NATIVE_ENDIAN,
b4e37d98 MW	240	};
	241
	242	static void milkymist_memcard_reset(DeviceState *d)
	243	{
7a239e46	244	MilkymistMemcardState *s = MILKYMIST_MEMCARD(d);
b4e37d98 MW	245	int i;
	246
	247	s->command_write_ptr = 0;
	248	s->response_read_ptr = 0;
	249	s->response_len = 0;
	250
	251	for (i = 0; i < R_MAX; i++) {
	252	s->regs[i] = 0;
	253	}
	254	}
	255
85fd6e5d PMD	256	static void milkymist_memcard_init(Object *obj)
	257	{
	258	MilkymistMemcardState *s = MILKYMIST_MEMCARD(obj);
	259	SysBusDevice *dev = SYS_BUS_DEVICE(obj);
	260
	261	memory_region_init_io(&s->regs_region, OBJECT(s), &memcard_mmio_ops, s,
	262	"milkymist-memcard", R_MAX * 4);
	263	sysbus_init_mmio(dev, &s->regs_region);
	264	}
	265
	266	static void milkymist_memcard_realize(DeviceState dev, Error *errp)
b4e37d98	267	{
7a239e46	268	MilkymistMemcardState *s = MILKYMIST_MEMCARD(dev);
3d0369ba	269	DeviceState *carddev;
4be74634	270	BlockBackend *blk;
85fd6e5d	271	DriveInfo *dinfo;
3d0369ba	272	Error *err = NULL;
b4e37d98	273
3d0369ba PMD	274	qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS,
	275	dev, "sd-bus");
	276
	277	/* Create and plug in the sd card */
af9e40aa	278	/* FIXME use a qdev drive property instead of drive_get_next() */
b4e37d98	279	dinfo = drive_get_next(IF_SD);
4be74634	280	blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
3d0369ba PMD	281	carddev = qdev_create(&s->sdbus.qbus, TYPE_SD_CARD);
	282	qdev_prop_set_drive(carddev, "drive", blk, &err);
	283	object_property_set_bool(OBJECT(carddev), true, "realized", &err);
	284	if (err) {
	285	error_setg(errp, "failed to init SD card: %s", error_get_pretty(err));
85fd6e5d	286	return;
4f8a066b	287	}
4be74634	288	s->enabled = blk && blk_is_inserted(blk);
b4e37d98 MW	289	}
	290
	291	static const VMStateDescription vmstate_milkymist_memcard = {
	292	.name = "milkymist-memcard",
	293	.version_id = 1,
	294	.minimum_version_id = 1,
35d08458	295	.fields = (VMStateField[]) {
b4e37d98 MW	296	VMSTATE_INT32(command_write_ptr, MilkymistMemcardState),
	297	VMSTATE_INT32(response_read_ptr, MilkymistMemcardState),
	298	VMSTATE_INT32(response_len, MilkymistMemcardState),
	299	VMSTATE_INT32(ignore_next_cmd, MilkymistMemcardState),
	300	VMSTATE_INT32(enabled, MilkymistMemcardState),
	301	VMSTATE_UINT8_ARRAY(command, MilkymistMemcardState, 6),
	302	VMSTATE_UINT8_ARRAY(response, MilkymistMemcardState, 17),
	303	VMSTATE_UINT32_ARRAY(regs, MilkymistMemcardState, R_MAX),
	304	VMSTATE_END_OF_LIST()
	305	}
	306	};
	307
999e12bb AL	308	static void milkymist_memcard_class_init(ObjectClass klass, void data)
999e12bb AL	309	{
39bffca2	310	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	311
85fd6e5d	312	dc->realize = milkymist_memcard_realize;
39bffca2 AL	313	dc->reset = milkymist_memcard_reset;
39bffca2 AL	314	dc->vmsd = &vmstate_milkymist_memcard;
9f9bdf43	315	/* Reason: init() method uses drive_get_next() */
e90f2a8c	316	dc->user_creatable = false;
999e12bb AL	317	}
999e12bb AL	318
8c43a6f0	319	static const TypeInfo milkymist_memcard_info = {
7a239e46	320	.name = TYPE_MILKYMIST_MEMCARD,
39bffca2 AL	321	.parent = TYPE_SYS_BUS_DEVICE,
39bffca2 AL	322	.instance_size = sizeof(MilkymistMemcardState),
85fd6e5d	323	.instance_init = milkymist_memcard_init,
39bffca2	324	.class_init = milkymist_memcard_class_init,
b4e37d98 MW	325	};
b4e37d98 MW	326
83f7d43a	327	static void milkymist_memcard_register_types(void)
b4e37d98	328	{
39bffca2	329	type_register_static(&milkymist_memcard_info);
b4e37d98 MW	330	}
b4e37d98 MW	331
83f7d43a	332	type_init(milkymist_memcard_register_types)