[qemu.git] / hw / hppa / dino.c

/*
 * HP-PARISC Dino PCI chipset emulation, as in B160L and similiar machines
 *
 * (C) 2017-2019 by Helge Deller <[email protected]>
 *
 * This work is licensed under the GNU GPL license version 2 or later.
 *
 * Documentation available at:
 * https://parisc.wiki.kernel.org/images-parisc/9/91/Dino_ers.pdf
 * https://parisc.wiki.kernel.org/images-parisc/7/70/Dino_3_1_Errata.pdf
 */

#include "qemu/osdep.h"
#include "qemu/module.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "cpu.h"
#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bus.h"
#include "migration/vmstate.h"
#include "hppa_sys.h"
#include "exec/address-spaces.h"
#include "trace.h"


#define TYPE_DINO_PCI_HOST_BRIDGE "dino-pcihost"

#define DINO_IAR0               0x004
#define DINO_IODC               0x008
#define DINO_IRR0               0x00C  /* RO */
#define DINO_IAR1               0x010
#define DINO_IRR1               0x014  /* RO */
#define DINO_IMR                0x018
#define DINO_IPR                0x01C
#define DINO_TOC_ADDR           0x020
#define DINO_ICR                0x024
#define DINO_ILR                0x028  /* RO */
#define DINO_IO_COMMAND         0x030  /* WO */
#define DINO_IO_STATUS          0x034  /* RO */
#define DINO_IO_CONTROL         0x038
#define DINO_IO_GSC_ERR_RESP    0x040  /* RO */
#define DINO_IO_ERR_INFO        0x044  /* RO */
#define DINO_IO_PCI_ERR_RESP    0x048  /* RO */
#define DINO_IO_FBB_EN          0x05c
#define DINO_IO_ADDR_EN         0x060
#define DINO_PCI_CONFIG_ADDR    0x064
#define DINO_PCI_CONFIG_DATA    0x068
#define DINO_PCI_IO_DATA        0x06c
#define DINO_PCI_MEM_DATA       0x070  /* Dino 3.x only */
#define DINO_GSC2X_CONFIG       0x7b4  /* RO */
#define DINO_GMASK              0x800
#define DINO_PAMR               0x804
#define DINO_PAPR               0x808
#define DINO_DAMODE             0x80c
#define DINO_PCICMD             0x810
#define DINO_PCISTS             0x814  /* R/WC */
#define DINO_MLTIM              0x81c
#define DINO_BRDG_FEAT          0x820
#define DINO_PCIROR             0x824
#define DINO_PCIWOR             0x828
#define DINO_TLTIM              0x830

#define DINO_IRQS         11      /* bits 0-10 are architected */
#define DINO_IRR_MASK     0x5ff   /* only 10 bits are implemented */
#define DINO_LOCAL_IRQS   (DINO_IRQS + 1)
#define DINO_MASK_IRQ(x)  (1 << (x))

#define PCIINTA   0x001
#define PCIINTB   0x002
#define PCIINTC   0x004
#define PCIINTD   0x008
#define PCIINTE   0x010
#define PCIINTF   0x020
#define GSCEXTINT 0x040
/* #define xxx       0x080 - bit 7 is "default" */
/* #define xxx    0x100 - bit 8 not used */
/* #define xxx    0x200 - bit 9 not used */
#define RS232INT  0x400

#define DINO_MEM_CHUNK_SIZE (8 * MiB)

#define DINO_PCI_HOST_BRIDGE(obj) \
    OBJECT_CHECK(DinoState, (obj), TYPE_DINO_PCI_HOST_BRIDGE)

#define DINO800_REGS (1 + (DINO_TLTIM - DINO_GMASK) / 4)
static const uint32_t reg800_keep_bits[DINO800_REGS] = {
    MAKE_64BIT_MASK(0, 1),  /* GMASK */
    MAKE_64BIT_MASK(0, 7),  /* PAMR */
    MAKE_64BIT_MASK(0, 7),  /* PAPR */
    MAKE_64BIT_MASK(0, 8),  /* DAMODE */
    MAKE_64BIT_MASK(0, 7),  /* PCICMD */
    MAKE_64BIT_MASK(0, 9),  /* PCISTS */
    MAKE_64BIT_MASK(0, 32), /* Undefined */
    MAKE_64BIT_MASK(0, 8),  /* MLTIM */
    MAKE_64BIT_MASK(0, 30), /* BRDG_FEAT */
    MAKE_64BIT_MASK(0, 24), /* PCIROR */
    MAKE_64BIT_MASK(0, 22), /* PCIWOR */
    MAKE_64BIT_MASK(0, 32), /* Undocumented */
    MAKE_64BIT_MASK(0, 9),  /* TLTIM */
};

typedef struct DinoState {
    PCIHostState parent_obj;

    /* PCI_CONFIG_ADDR is parent_obj.config_reg, via pci_host_conf_be_ops,
       so that we can map PCI_CONFIG_DATA to pci_host_data_be_ops.  */
    uint32_t config_reg_dino; /* keep original copy, including 2 lowest bits */

    uint32_t iar0;
    uint32_t iar1;
    uint32_t imr;
    uint32_t ipr;
    uint32_t icr;
    uint32_t ilr;
    uint32_t io_fbb_en;
    uint32_t io_addr_en;
    uint32_t io_control;
    uint32_t toc_addr;

    uint32_t reg800[DINO800_REGS];

    MemoryRegion this_mem;
    MemoryRegion pci_mem;
    MemoryRegion pci_mem_alias[32];

    AddressSpace bm_as;
    MemoryRegion bm;
    MemoryRegion bm_ram_alias;
    MemoryRegion bm_pci_alias;
    MemoryRegion bm_cpu_alias;
} DinoState;

/*
 * Dino can forward memory accesses from the CPU in the range between
 * 0xf0800000 and 0xff000000 to the PCI bus.
 */
static void gsc_to_pci_forwarding(DinoState *s)
{
    uint32_t io_addr_en, tmp;
    int enabled, i;

    tmp = extract32(s->io_control, 7, 2);
    enabled = (tmp == 0x01);
    io_addr_en = s->io_addr_en;
    /* Mask out first (=firmware) and last (=Dino) areas. */
    io_addr_en &= ~(BIT(31) | BIT(0));

    memory_region_transaction_begin();
    for (i = 1; i < 31; i++) {
        MemoryRegion *mem = &s->pci_mem_alias[i];
        if (enabled && (io_addr_en & (1U << i))) {
            if (!memory_region_is_mapped(mem)) {
                uint32_t addr = 0xf0000000 + i * DINO_MEM_CHUNK_SIZE;
                memory_region_add_subregion(get_system_memory(), addr, mem);
            }
        } else if (memory_region_is_mapped(mem)) {
            memory_region_del_subregion(get_system_memory(), mem);
        }
    }
    memory_region_transaction_commit();
}

static bool dino_chip_mem_valid(void *opaque, hwaddr addr,
                                unsigned size, bool is_write,
                                MemTxAttrs attrs)
{
    bool ret = false;

    switch (addr) {
    case DINO_IAR0:
    case DINO_IAR1:
    case DINO_IRR0:
    case DINO_IRR1:
    case DINO_IMR:
    case DINO_IPR:
    case DINO_ICR:
    case DINO_ILR:
    case DINO_IO_CONTROL:
    case DINO_IO_FBB_EN:
    case DINO_IO_ADDR_EN:
    case DINO_PCI_IO_DATA:
    case DINO_TOC_ADDR:
    case DINO_GMASK ... DINO_PCISTS:
    case DINO_MLTIM ... DINO_PCIWOR:
    case DINO_TLTIM:
        ret = true;
        break;
    case DINO_PCI_IO_DATA + 2:
        ret = (size <= 2);
        break;
    case DINO_PCI_IO_DATA + 1:
    case DINO_PCI_IO_DATA + 3:
        ret = (size == 1);
    }
    trace_dino_chip_mem_valid(addr, ret);
    return ret;
}

static MemTxResult dino_chip_read_with_attrs(void *opaque, hwaddr addr,
                                             uint64_t *data, unsigned size,
                                             MemTxAttrs attrs)
{
    DinoState *s = opaque;
    MemTxResult ret = MEMTX_OK;
    AddressSpace *io;
    uint16_t ioaddr;
    uint32_t val;

    switch (addr) {
    case DINO_PCI_IO_DATA ... DINO_PCI_IO_DATA + 3:
        /* Read from PCI IO space. */
        io = &address_space_io;
        ioaddr = s->parent_obj.config_reg + (addr & 3);
        switch (size) {
        case 1:
            val = address_space_ldub(io, ioaddr, attrs, &ret);
            break;
        case 2:
            val = address_space_lduw_be(io, ioaddr, attrs, &ret);
            break;
        case 4:
            val = address_space_ldl_be(io, ioaddr, attrs, &ret);
            break;
        default:
            g_assert_not_reached();
        }
        break;

    case DINO_IO_FBB_EN:
        val = s->io_fbb_en;
        break;
    case DINO_IO_ADDR_EN:
        val = s->io_addr_en;
        break;
    case DINO_IO_CONTROL:
        val = s->io_control;
        break;

    case DINO_IAR0:
        val = s->iar0;
        break;
    case DINO_IAR1:
        val = s->iar1;
        break;
    case DINO_IMR:
        val = s->imr;
        break;
    case DINO_ICR:
        val = s->icr;
        break;
    case DINO_IPR:
        val = s->ipr;
        /* Any read to IPR clears the register.  */
        s->ipr = 0;
        break;
    case DINO_ILR:
        val = s->ilr;
        break;
    case DINO_IRR0:
        val = s->ilr & s->imr & ~s->icr;
        break;
    case DINO_IRR1:
        val = s->ilr & s->imr & s->icr;
        break;
    case DINO_TOC_ADDR:
        val = s->toc_addr;
        break;
    case DINO_GMASK ... DINO_TLTIM:
        val = s->reg800[(addr - DINO_GMASK) / 4];
        if (addr == DINO_PAMR) {
            val &= ~0x01;  /* LSB is hardwired to 0 */
        }
        if (addr == DINO_MLTIM) {
            val &= ~0x07;  /* 3 LSB are hardwired to 0 */
        }
        if (addr == DINO_BRDG_FEAT) {
            val &= ~(0x10710E0ul | 8); /* bits 5-7, 24 & 15 reserved */
        }
        break;

    default:
        /* Controlled by dino_chip_mem_valid above.  */
        g_assert_not_reached();
    }

    trace_dino_chip_read(addr, val);
    *data = val;
    return ret;
}

static MemTxResult dino_chip_write_with_attrs(void *opaque, hwaddr addr,
                                              uint64_t val, unsigned size,
                                              MemTxAttrs attrs)
{
    DinoState *s = opaque;
    AddressSpace *io;
    MemTxResult ret;
    uint16_t ioaddr;
    int i;

    trace_dino_chip_write(addr, val);

    switch (addr) {
    case DINO_IO_DATA ... DINO_PCI_IO_DATA + 3:
        /* Write into PCI IO space.  */
        io = &address_space_io;
        ioaddr = s->parent_obj.config_reg + (addr & 3);
        switch (size) {
        case 1:
            address_space_stb(io, ioaddr, val, attrs, &ret);
            break;
        case 2:
            address_space_stw_be(io, ioaddr, val, attrs, &ret);
            break;
        case 4:
            address_space_stl_be(io, ioaddr, val, attrs, &ret);
            break;
        default:
            g_assert_not_reached();
        }
        return ret;

    case DINO_IO_FBB_EN:
        s->io_fbb_en = val & 0x03;
        break;
    case DINO_IO_ADDR_EN:
        s->io_addr_en = val;
        gsc_to_pci_forwarding(s);
        break;
    case DINO_IO_CONTROL:
        s->io_control = val;
        gsc_to_pci_forwarding(s);
        break;

    case DINO_IAR0:
        s->iar0 = val;
        break;
    case DINO_IAR1:
        s->iar1 = val;
        break;
    case DINO_IMR:
        s->imr = val;
        break;
    case DINO_ICR:
        s->icr = val;
        break;
    case DINO_IPR:
        /* Any write to IPR clears the register.  */
        s->ipr = 0;
        break;
    case DINO_TOC_ADDR:
        /* IO_COMMAND of CPU with client_id bits */
        s->toc_addr = 0xFFFA0030 | (val & 0x1e000);
        break;

    case DINO_ILR:
    case DINO_IRR0:
    case DINO_IRR1:
        /* These registers are read-only.  */
        break;

    case DINO_GMASK ... DINO_TLTIM:
        i = (addr - DINO_GMASK) / 4;
        val &= reg800_keep_bits[i];
        s->reg800[i] = val;
        break;

    default:
        /* Controlled by dino_chip_mem_valid above.  */
        g_assert_not_reached();
    }
    return MEMTX_OK;
}

static const MemoryRegionOps dino_chip_ops = {
    .read_with_attrs = dino_chip_read_with_attrs,
    .write_with_attrs = dino_chip_write_with_attrs,
    .endianness = DEVICE_BIG_ENDIAN,
    .valid = {
        .min_access_size = 1,
        .max_access_size = 4,
        .accepts = dino_chip_mem_valid,
    },
    .impl = {
        .min_access_size = 1,
        .max_access_size = 4,
    },
};

static const VMStateDescription vmstate_dino = {
    .name = "Dino",
    .version_id = 2,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(iar0, DinoState),
        VMSTATE_UINT32(iar1, DinoState),
        VMSTATE_UINT32(imr, DinoState),
        VMSTATE_UINT32(ipr, DinoState),
        VMSTATE_UINT32(icr, DinoState),
        VMSTATE_UINT32(ilr, DinoState),
        VMSTATE_UINT32(io_fbb_en, DinoState),
        VMSTATE_UINT32(io_addr_en, DinoState),
        VMSTATE_UINT32(io_control, DinoState),
        VMSTATE_UINT32(toc_addr, DinoState),
        VMSTATE_END_OF_LIST()
    }
};

/* Unlike pci_config_data_le_ops, no check of high bit set in config_reg.  */

static uint64_t dino_config_data_read(void *opaque, hwaddr addr, unsigned len)
{
    PCIHostState *s = opaque;
    return pci_data_read(s->bus, s->config_reg | (addr & 3), len);
}

static void dino_config_data_write(void *opaque, hwaddr addr,
                                   uint64_t val, unsigned len)
{
    PCIHostState *s = opaque;
    pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
}

static const MemoryRegionOps dino_config_data_ops = {
    .read = dino_config_data_read,
    .write = dino_config_data_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static uint64_t dino_config_addr_read(void *opaque, hwaddr addr, unsigned len)
{
    DinoState *s = opaque;
    return s->config_reg_dino;
}

static void dino_config_addr_write(void *opaque, hwaddr addr,
                                   uint64_t val, unsigned len)
{
    PCIHostState *s = opaque;
    DinoState *ds = opaque;
    ds->config_reg_dino = val; /* keep a copy of original value */
    s->config_reg = val & ~3U;
}

static const MemoryRegionOps dino_config_addr_ops = {
    .read = dino_config_addr_read,
    .write = dino_config_addr_write,
    .valid.min_access_size = 4,
    .valid.max_access_size = 4,
    .endianness = DEVICE_BIG_ENDIAN,
};

static AddressSpace *dino_pcihost_set_iommu(PCIBus *bus, void *opaque,
                                            int devfn)
{
    DinoState *s = opaque;

    return &s->bm_as;
}

/*
 * Dino interrupts are connected as shown on Page 78, Table 23
 * (Little-endian bit numbers)
 *    0   PCI INTA
 *    1   PCI INTB
 *    2   PCI INTC
 *    3   PCI INTD
 *    4   PCI INTE
 *    5   PCI INTF
 *    6   GSC External Interrupt
 *    7   Bus Error for "less than fatal" mode
 *    8   PS2
 *    9   Unused
 *    10  RS232
 */

static void dino_set_irq(void *opaque, int irq, int level)
{
    DinoState *s = opaque;
    uint32_t bit = 1u << irq;
    uint32_t old_ilr = s->ilr;

    if (level) {
        uint32_t ena = bit & ~old_ilr;
        s->ipr |= ena;
        s->ilr = old_ilr | bit;
        if (ena & s->imr) {
            uint32_t iar = (ena & s->icr ? s->iar1 : s->iar0);
            stl_be_phys(&address_space_memory, iar & -32, iar & 31);
        }
    } else {
        s->ilr = old_ilr & ~bit;
    }
}

static int dino_pci_map_irq(PCIDevice *d, int irq_num)
{
    int slot = d->devfn >> 3;

    assert(irq_num >= 0 && irq_num <= 3);

    return slot & 0x03;
}

static void dino_set_timer_irq(void *opaque, int irq, int level)
{
    /* ??? Not connected.  */
}

static void dino_set_serial_irq(void *opaque, int irq, int level)
{
    dino_set_irq(opaque, 10, level);
}

PCIBus *dino_init(MemoryRegion *addr_space,
                  qemu_irq *p_rtc_irq, qemu_irq *p_ser_irq)
{
    DeviceState *dev;
    DinoState *s;
    PCIBus *b;
    int i;

    dev = qdev_create(NULL, TYPE_DINO_PCI_HOST_BRIDGE);
    s = DINO_PCI_HOST_BRIDGE(dev);
    s->iar0 = s->iar1 = CPU_HPA + 3;
    s->toc_addr = 0xFFFA0030; /* IO_COMMAND of CPU */

    /* Dino PCI access from main memory.  */
    memory_region_init_io(&s->this_mem, OBJECT(s), &dino_chip_ops,
                          s, "dino", 4096);
    memory_region_add_subregion(addr_space, DINO_HPA, &s->this_mem);

    /* Dino PCI config. */
    memory_region_init_io(&s->parent_obj.conf_mem, OBJECT(&s->parent_obj),
                          &dino_config_addr_ops, dev, "pci-conf-idx", 4);
    memory_region_init_io(&s->parent_obj.data_mem, OBJECT(&s->parent_obj),
                          &dino_config_data_ops, dev, "pci-conf-data", 4);
    memory_region_add_subregion(&s->this_mem, DINO_PCI_CONFIG_ADDR,
                                &s->parent_obj.conf_mem);
    memory_region_add_subregion(&s->this_mem, DINO_CONFIG_DATA,
                                &s->parent_obj.data_mem);

    /* Dino PCI bus memory.  */
    memory_region_init(&s->pci_mem, OBJECT(s), "pci-memory", 1ull << 32);

    b = pci_register_root_bus(dev, "pci", dino_set_irq, dino_pci_map_irq, s,
                              &s->pci_mem, get_system_io(),
                              PCI_DEVFN(0, 0), 32, TYPE_PCI_BUS);
    s->parent_obj.bus = b;
    qdev_init_nofail(dev);

    /* Set up windows into PCI bus memory.  */
    for (i = 1; i < 31; i++) {
        uint32_t addr = 0xf0000000 + i * DINO_MEM_CHUNK_SIZE;
        char *name = g_strdup_printf("PCI Outbound Window %d", i);
        memory_region_init_alias(&s->pci_mem_alias[i], OBJECT(s),
                                 name, &s->pci_mem, addr,
                                 DINO_MEM_CHUNK_SIZE);
        g_free(name);
    }

    /* Set up PCI view of memory: Bus master address space.  */
    memory_region_init(&s->bm, OBJECT(s), "bm-dino", 1ull << 32);
    memory_region_init_alias(&s->bm_ram_alias, OBJECT(s),
                             "bm-system", addr_space, 0,
                             0xf0000000 + DINO_MEM_CHUNK_SIZE);
    memory_region_init_alias(&s->bm_pci_alias, OBJECT(s),
                             "bm-pci", &s->pci_mem,
                             0xf0000000 + DINO_MEM_CHUNK_SIZE,
                             30 * DINO_MEM_CHUNK_SIZE);
    memory_region_init_alias(&s->bm_cpu_alias, OBJECT(s),
                             "bm-cpu", addr_space, 0xfff00000,
                             0xfffff);
    memory_region_add_subregion(&s->bm, 0,
                                &s->bm_ram_alias);
    memory_region_add_subregion(&s->bm,
                                0xf0000000 + DINO_MEM_CHUNK_SIZE,
                                &s->bm_pci_alias);
    memory_region_add_subregion(&s->bm, 0xfff00000,
                                &s->bm_cpu_alias);
    address_space_init(&s->bm_as, &s->bm, "pci-bm");
    pci_setup_iommu(b, dino_pcihost_set_iommu, s);

    *p_rtc_irq = qemu_allocate_irq(dino_set_timer_irq, s, 0);
    *p_ser_irq = qemu_allocate_irq(dino_set_serial_irq, s, 0);

    return b;
}

static void dino_pcihost_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->vmsd = &vmstate_dino;
}

static const TypeInfo dino_pcihost_info = {
    .name          = TYPE_DINO_PCI_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(DinoState),
    .class_init    = dino_pcihost_class_init,
};

static void dino_register_types(void)
{
    type_register_static(&dino_pcihost_info);
}

type_init(dino_register_types)
Commit	Line	Data
a72bd606	1	/*
18092598	2	* HP-PARISC Dino PCI chipset emulation, as in B160L and similiar machines
a72bd606	3	*
18092598	4	* (C) 2017-2019 by Helge Deller <[email protected]>
a72bd606 HD	5	*
	6	* This work is licensed under the GNU GPL license version 2 or later.
	7	*
	8	* Documentation available at:
	9	* https://parisc.wiki.kernel.org/images-parisc/9/91/Dino_ers.pdf
	10	* https://parisc.wiki.kernel.org/images-parisc/7/70/Dino_3_1_Errata.pdf
	11	*/
	12
	13	#include "qemu/osdep.h"
0b8fa32f	14	#include "qemu/module.h"
c108cc59	15	#include "qemu/units.h"
a72bd606 HD	16	#include "qapi/error.h"
a72bd606 HD	17	#include "cpu.h"
64552b6b	18	#include "hw/irq.h"
a72bd606 HD	19	#include "hw/pci/pci.h"
a72bd606 HD	20	#include "hw/pci/pci_bus.h"
d6454270	21	#include "migration/vmstate.h"
a72bd606 HD	22	#include "hppa_sys.h"
a72bd606 HD	23	#include "exec/address-spaces.h"
18092598	24	#include "trace.h"
a72bd606 HD	25
	26
	27	#define TYPE_DINO_PCI_HOST_BRIDGE "dino-pcihost"
	28
	29	#define DINO_IAR0 0x004
	30	#define DINO_IODC 0x008
	31	#define DINO_IRR0 0x00C /* RO */
	32	#define DINO_IAR1 0x010
	33	#define DINO_IRR1 0x014 /* RO */
	34	#define DINO_IMR 0x018
	35	#define DINO_IPR 0x01C
	36	#define DINO_TOC_ADDR 0x020
	37	#define DINO_ICR 0x024
	38	#define DINO_ILR 0x028 /* RO */
	39	#define DINO_IO_COMMAND 0x030 /* WO */
	40	#define DINO_IO_STATUS 0x034 /* RO */
	41	#define DINO_IO_CONTROL 0x038
	42	#define DINO_IO_GSC_ERR_RESP 0x040 /* RO */
	43	#define DINO_IO_ERR_INFO 0x044 /* RO */
	44	#define DINO_IO_PCI_ERR_RESP 0x048 /* RO */
	45	#define DINO_IO_FBB_EN 0x05c
	46	#define DINO_IO_ADDR_EN 0x060
	47	#define DINO_PCI_CONFIG_ADDR 0x064
	48	#define DINO_PCI_CONFIG_DATA 0x068
	49	#define DINO_PCI_IO_DATA 0x06c
	50	#define DINO_PCI_MEM_DATA 0x070 /* Dino 3.x only */
	51	#define DINO_GSC2X_CONFIG 0x7b4 /* RO */
	52	#define DINO_GMASK 0x800
	53	#define DINO_PAMR 0x804
	54	#define DINO_PAPR 0x808
	55	#define DINO_DAMODE 0x80c
	56	#define DINO_PCICMD 0x810
	57	#define DINO_PCISTS 0x814 /* R/WC */
	58	#define DINO_MLTIM 0x81c
	59	#define DINO_BRDG_FEAT 0x820
	60	#define DINO_PCIROR 0x824
	61	#define DINO_PCIWOR 0x828
	62	#define DINO_TLTIM 0x830
	63
	64	#define DINO_IRQS 11 /* bits 0-10 are architected */
	65	#define DINO_IRR_MASK 0x5ff /* only 10 bits are implemented */
	66	#define DINO_LOCAL_IRQS (DINO_IRQS + 1)
	67	#define DINO_MASK_IRQ(x) (1 << (x))
	68
	69	#define PCIINTA 0x001
	70	#define PCIINTB 0x002
	71	#define PCIINTC 0x004
	72	#define PCIINTD 0x008
	73	#define PCIINTE 0x010
	74	#define PCIINTF 0x020
	75	#define GSCEXTINT 0x040
	76	/* #define xxx 0x080 - bit 7 is "default" */
	77	/* #define xxx 0x100 - bit 8 not used */
	78	/* #define xxx 0x200 - bit 9 not used */
	79	#define RS232INT 0x400
	80
c108cc59	81	#define DINO_MEM_CHUNK_SIZE (8 * MiB)
a72bd606 HD	82
	83	#define DINO_PCI_HOST_BRIDGE(obj) \
	84	OBJECT_CHECK(DinoState, (obj), TYPE_DINO_PCI_HOST_BRIDGE)
	85
6e4ed423	86	#define DINO800_REGS (1 + (DINO_TLTIM - DINO_GMASK) / 4)
18092598	87	static const uint32_t reg800_keep_bits[DINO800_REGS] = {
422a2648 PMD	88	MAKE_64BIT_MASK(0, 1), /* GMASK */
	89	MAKE_64BIT_MASK(0, 7), /* PAMR */
	90	MAKE_64BIT_MASK(0, 7), /* PAPR */
	91	MAKE_64BIT_MASK(0, 8), /* DAMODE */
	92	MAKE_64BIT_MASK(0, 7), /* PCICMD */
	93	MAKE_64BIT_MASK(0, 9), /* PCISTS */
	94	MAKE_64BIT_MASK(0, 32), /* Undefined */
	95	MAKE_64BIT_MASK(0, 8), /* MLTIM */
	96	MAKE_64BIT_MASK(0, 30), /* BRDG_FEAT */
c9cbfebf	97	MAKE_64BIT_MASK(0, 24), /* PCIROR */
422a2648	98	MAKE_64BIT_MASK(0, 22), /* PCIWOR */
6e4ed423	99	MAKE_64BIT_MASK(0, 32), /* Undocumented */
422a2648	100	MAKE_64BIT_MASK(0, 9), /* TLTIM */
18092598 HD	101	};
18092598 HD	102
a72bd606 HD	103	typedef struct DinoState {
	104	PCIHostState parent_obj;
	105
	106	/* PCI_CONFIG_ADDR is parent_obj.config_reg, via pci_host_conf_be_ops,
	107	so that we can map PCI_CONFIG_DATA to pci_host_data_be_ops. */
18092598	108	uint32_t config_reg_dino; /* keep original copy, including 2 lowest bits */
a72bd606 HD	109
	110	uint32_t iar0;
	111	uint32_t iar1;
	112	uint32_t imr;
	113	uint32_t ipr;
	114	uint32_t icr;
	115	uint32_t ilr;
18092598	116	uint32_t io_fbb_en;
a72bd606 HD	117	uint32_t io_addr_en;
a72bd606 HD	118	uint32_t io_control;
18092598 HD	119	uint32_t toc_addr;
	120
	121	uint32_t reg800[DINO800_REGS];
a72bd606 HD	122
	123	MemoryRegion this_mem;
	124	MemoryRegion pci_mem;
	125	MemoryRegion pci_mem_alias[32];
	126
	127	AddressSpace bm_as;
	128	MemoryRegion bm;
	129	MemoryRegion bm_ram_alias;
	130	MemoryRegion bm_pci_alias;
cb82c572	131	MemoryRegion bm_cpu_alias;
a72bd606 HD	132	} DinoState;
	133
	134	/*
	135	* Dino can forward memory accesses from the CPU in the range between
	136	* 0xf0800000 and 0xff000000 to the PCI bus.
	137	*/
	138	static void gsc_to_pci_forwarding(DinoState *s)
	139	{
	140	uint32_t io_addr_en, tmp;
	141	int enabled, i;
	142
	143	tmp = extract32(s->io_control, 7, 2);
	144	enabled = (tmp == 0x01);
	145	io_addr_en = s->io_addr_en;
18092598 HD	146	/* Mask out first (=firmware) and last (=Dino) areas. */
18092598 HD	147	io_addr_en &= ~(BIT(31) \| BIT(0));
a72bd606 HD	148
	149	memory_region_transaction_begin();
	150	for (i = 1; i < 31; i++) {
	151	MemoryRegion *mem = &s->pci_mem_alias[i];
	152	if (enabled && (io_addr_en & (1U << i))) {
	153	if (!memory_region_is_mapped(mem)) {
	154	uint32_t addr = 0xf0000000 + i * DINO_MEM_CHUNK_SIZE;
	155	memory_region_add_subregion(get_system_memory(), addr, mem);
	156	}
	157	} else if (memory_region_is_mapped(mem)) {
	158	memory_region_del_subregion(get_system_memory(), mem);
	159	}
	160	}
	161	memory_region_transaction_commit();
	162	}
	163
	164	static bool dino_chip_mem_valid(void *opaque, hwaddr addr,
8372d383 PM	165	unsigned size, bool is_write,
8372d383 PM	166	MemTxAttrs attrs)
a72bd606	167	{
18092598 HD	168	bool ret = false;
18092598 HD	169
a72bd606 HD	170	switch (addr) {
	171	case DINO_IAR0:
	172	case DINO_IAR1:
	173	case DINO_IRR0:
	174	case DINO_IRR1:
	175	case DINO_IMR:
	176	case DINO_IPR:
	177	case DINO_ICR:
	178	case DINO_ILR:
	179	case DINO_IO_CONTROL:
18092598	180	case DINO_IO_FBB_EN:
a72bd606 HD	181	case DINO_IO_ADDR_EN:
a72bd606 HD	182	case DINO_PCI_IO_DATA:
18092598	183	case DINO_TOC_ADDR:
90e94c05 PMD	184	case DINO_GMASK ... DINO_PCISTS:
	185	case DINO_MLTIM ... DINO_PCIWOR:
	186	case DINO_TLTIM:
18092598 HD	187	ret = true;
18092598 HD	188	break;
a72bd606	189	case DINO_PCI_IO_DATA + 2:
18092598 HD	190	ret = (size <= 2);
18092598 HD	191	break;
a72bd606 HD	192	case DINO_PCI_IO_DATA + 1:
a72bd606 HD	193	case DINO_PCI_IO_DATA + 3:
18092598	194	ret = (size == 1);
a72bd606	195	}
18092598 HD	196	trace_dino_chip_mem_valid(addr, ret);
18092598 HD	197	return ret;
a72bd606 HD	198	}
	199
	200	static MemTxResult dino_chip_read_with_attrs(void *opaque, hwaddr addr,
	201	uint64_t *data, unsigned size,
	202	MemTxAttrs attrs)
	203	{
	204	DinoState *s = opaque;
	205	MemTxResult ret = MEMTX_OK;
	206	AddressSpace *io;
	207	uint16_t ioaddr;
	208	uint32_t val;
	209
	210	switch (addr) {
	211	case DINO_PCI_IO_DATA ... DINO_PCI_IO_DATA + 3:
	212	/* Read from PCI IO space. */
	213	io = &address_space_io;
368bec88	214	ioaddr = s->parent_obj.config_reg + (addr & 3);
a72bd606 HD	215	switch (size) {
	216	case 1:
	217	val = address_space_ldub(io, ioaddr, attrs, &ret);
	218	break;
	219	case 2:
	220	val = address_space_lduw_be(io, ioaddr, attrs, &ret);
	221	break;
	222	case 4:
	223	val = address_space_ldl_be(io, ioaddr, attrs, &ret);
	224	break;
	225	default:
	226	g_assert_not_reached();
	227	}
	228	break;
	229
18092598 HD	230	case DINO_IO_FBB_EN:
	231	val = s->io_fbb_en;
	232	break;
a72bd606 HD	233	case DINO_IO_ADDR_EN:
	234	val = s->io_addr_en;
	235	break;
	236	case DINO_IO_CONTROL:
	237	val = s->io_control;
	238	break;
	239
	240	case DINO_IAR0:
	241	val = s->iar0;
	242	break;
	243	case DINO_IAR1:
	244	val = s->iar1;
	245	break;
	246	case DINO_IMR:
	247	val = s->imr;
	248	break;
	249	case DINO_ICR:
	250	val = s->icr;
	251	break;
	252	case DINO_IPR:
	253	val = s->ipr;
	254	/* Any read to IPR clears the register. */
	255	s->ipr = 0;
	256	break;
	257	case DINO_ILR:
	258	val = s->ilr;
	259	break;
	260	case DINO_IRR0:
	261	val = s->ilr & s->imr & ~s->icr;
	262	break;
	263	case DINO_IRR1:
	264	val = s->ilr & s->imr & s->icr;
	265	break;
18092598 HD	266	case DINO_TOC_ADDR:
	267	val = s->toc_addr;
	268	break;
	269	case DINO_GMASK ... DINO_TLTIM:
	270	val = s->reg800[(addr - DINO_GMASK) / 4];
	271	if (addr == DINO_PAMR) {
	272	val &= ~0x01; /* LSB is hardwired to 0 */
	273	}
	274	if (addr == DINO_MLTIM) {
	275	val &= ~0x07; /* 3 LSB are hardwired to 0 */
	276	}
	277	if (addr == DINO_BRDG_FEAT) {
	278	val &= ~(0x10710E0ul \| 8); /* bits 5-7, 24 & 15 reserved */
	279	}
	280	break;
a72bd606 HD	281
	282	default:
	283	/* Controlled by dino_chip_mem_valid above. */
	284	g_assert_not_reached();
	285	}
	286
18092598	287	trace_dino_chip_read(addr, val);
a72bd606 HD	288	*data = val;
	289	return ret;
	290	}
	291
	292	static MemTxResult dino_chip_write_with_attrs(void *opaque, hwaddr addr,
	293	uint64_t val, unsigned size,
	294	MemTxAttrs attrs)
	295	{
	296	DinoState *s = opaque;
	297	AddressSpace *io;
	298	MemTxResult ret;
	299	uint16_t ioaddr;
18092598 HD	300	int i;
	301
	302	trace_dino_chip_write(addr, val);
a72bd606 HD	303
	304	switch (addr) {
	305	case DINO_IO_DATA ... DINO_PCI_IO_DATA + 3:
	306	/* Write into PCI IO space. */
	307	io = &address_space_io;
368bec88	308	ioaddr = s->parent_obj.config_reg + (addr & 3);
a72bd606 HD	309	switch (size) {
	310	case 1:
	311	address_space_stb(io, ioaddr, val, attrs, &ret);
	312	break;
	313	case 2:
	314	address_space_stw_be(io, ioaddr, val, attrs, &ret);
	315	break;
	316	case 4:
	317	address_space_stl_be(io, ioaddr, val, attrs, &ret);
	318	break;
	319	default:
	320	g_assert_not_reached();
	321	}
	322	return ret;
	323
18092598 HD	324	case DINO_IO_FBB_EN:
	325	s->io_fbb_en = val & 0x03;
	326	break;
a72bd606	327	case DINO_IO_ADDR_EN:
18092598	328	s->io_addr_en = val;
a72bd606 HD	329	gsc_to_pci_forwarding(s);
	330	break;
	331	case DINO_IO_CONTROL:
	332	s->io_control = val;
	333	gsc_to_pci_forwarding(s);
	334	break;
	335
	336	case DINO_IAR0:
	337	s->iar0 = val;
	338	break;
	339	case DINO_IAR1:
	340	s->iar1 = val;
	341	break;
	342	case DINO_IMR:
	343	s->imr = val;
	344	break;
	345	case DINO_ICR:
	346	s->icr = val;
	347	break;
	348	case DINO_IPR:
	349	/* Any write to IPR clears the register. */
	350	s->ipr = 0;
	351	break;
18092598 HD	352	case DINO_TOC_ADDR:
	353	/* IO_COMMAND of CPU with client_id bits */
	354	s->toc_addr = 0xFFFA0030 \| (val & 0x1e000);
	355	break;
a72bd606 HD	356
	357	case DINO_ILR:
	358	case DINO_IRR0:
	359	case DINO_IRR1:
	360	/* These registers are read-only. */
	361	break;
	362
18092598 HD	363	case DINO_GMASK ... DINO_TLTIM:
	364	i = (addr - DINO_GMASK) / 4;
	365	val &= reg800_keep_bits[i];
	366	s->reg800[i] = val;
	367	break;
	368
a72bd606 HD	369	default:
	370	/* Controlled by dino_chip_mem_valid above. */
	371	g_assert_not_reached();
	372	}
	373	return MEMTX_OK;
	374	}
	375
	376	static const MemoryRegionOps dino_chip_ops = {
	377	.read_with_attrs = dino_chip_read_with_attrs,
	378	.write_with_attrs = dino_chip_write_with_attrs,
	379	.endianness = DEVICE_BIG_ENDIAN,
	380	.valid = {
	381	.min_access_size = 1,
	382	.max_access_size = 4,
	383	.accepts = dino_chip_mem_valid,
	384	},
	385	.impl = {
	386	.min_access_size = 1,
	387	.max_access_size = 4,
	388	},
	389	};
	390
	391	static const VMStateDescription vmstate_dino = {
	392	.name = "Dino",
18092598	393	.version_id = 2,
a72bd606 HD	394	.minimum_version_id = 1,
	395	.fields = (VMStateField[]) {
	396	VMSTATE_UINT32(iar0, DinoState),
	397	VMSTATE_UINT32(iar1, DinoState),
	398	VMSTATE_UINT32(imr, DinoState),
	399	VMSTATE_UINT32(ipr, DinoState),
	400	VMSTATE_UINT32(icr, DinoState),
	401	VMSTATE_UINT32(ilr, DinoState),
18092598	402	VMSTATE_UINT32(io_fbb_en, DinoState),
a72bd606 HD	403	VMSTATE_UINT32(io_addr_en, DinoState),
a72bd606 HD	404	VMSTATE_UINT32(io_control, DinoState),
18092598	405	VMSTATE_UINT32(toc_addr, DinoState),
a72bd606 HD	406	VMSTATE_END_OF_LIST()
	407	}
	408	};
	409
a72bd606 HD	410	/* Unlike pci_config_data_le_ops, no check of high bit set in config_reg. */
	411
	412	static uint64_t dino_config_data_read(void *opaque, hwaddr addr, unsigned len)
	413	{
	414	PCIHostState *s = opaque;
	415	return pci_data_read(s->bus, s->config_reg \| (addr & 3), len);
	416	}
	417
	418	static void dino_config_data_write(void *opaque, hwaddr addr,
	419	uint64_t val, unsigned len)
	420	{
	421	PCIHostState *s = opaque;
	422	pci_data_write(s->bus, s->config_reg \| (addr & 3), val, len);
	423	}
	424
	425	static const MemoryRegionOps dino_config_data_ops = {
	426	.read = dino_config_data_read,
	427	.write = dino_config_data_write,
	428	.endianness = DEVICE_LITTLE_ENDIAN,
	429	};
	430
368bec88 SS	431	static uint64_t dino_config_addr_read(void *opaque, hwaddr addr, unsigned len)
368bec88 SS	432	{
18092598 HD	433	DinoState *s = opaque;
18092598 HD	434	return s->config_reg_dino;
368bec88 SS	435	}
	436
	437	static void dino_config_addr_write(void *opaque, hwaddr addr,
	438	uint64_t val, unsigned len)
	439	{
	440	PCIHostState *s = opaque;
18092598 HD	441	DinoState *ds = opaque;
18092598 HD	442	ds->config_reg_dino = val; /* keep a copy of original value */
368bec88 SS	443	s->config_reg = val & ~3U;
	444	}
	445
	446	static const MemoryRegionOps dino_config_addr_ops = {
	447	.read = dino_config_addr_read,
	448	.write = dino_config_addr_write,
	449	.valid.min_access_size = 4,
	450	.valid.max_access_size = 4,
	451	.endianness = DEVICE_BIG_ENDIAN,
	452	};
	453
a72bd606 HD	454	static AddressSpace dino_pcihost_set_iommu(PCIBus bus, void *opaque,
	455	int devfn)
	456	{
	457	DinoState *s = opaque;
	458
	459	return &s->bm_as;
	460	}
	461
	462	/*
	463	* Dino interrupts are connected as shown on Page 78, Table 23
	464	* (Little-endian bit numbers)
	465	* 0 PCI INTA
	466	* 1 PCI INTB
	467	* 2 PCI INTC
	468	* 3 PCI INTD
	469	* 4 PCI INTE
	470	* 5 PCI INTF
	471	* 6 GSC External Interrupt
	472	* 7 Bus Error for "less than fatal" mode
	473	* 8 PS2
	474	* 9 Unused
	475	* 10 RS232
	476	*/
	477
	478	static void dino_set_irq(void *opaque, int irq, int level)
	479	{
	480	DinoState *s = opaque;
	481	uint32_t bit = 1u << irq;
	482	uint32_t old_ilr = s->ilr;
	483
	484	if (level) {
	485	uint32_t ena = bit & ~old_ilr;
	486	s->ipr \|= ena;
	487	s->ilr = old_ilr \| bit;
	488	if (ena & s->imr) {
	489	uint32_t iar = (ena & s->icr ? s->iar1 : s->iar0);
	490	stl_be_phys(&address_space_memory, iar & -32, iar & 31);
	491	}
	492	} else {
	493	s->ilr = old_ilr & ~bit;
	494	}
	495	}
	496
	497	static int dino_pci_map_irq(PCIDevice *d, int irq_num)
	498	{
	499	int slot = d->devfn >> 3;
a72bd606 HD	500
	501	assert(irq_num >= 0 && irq_num <= 3);
	502
4a4ff4c5	503	return slot & 0x03;
a72bd606 HD	504	}
	505
	506	static void dino_set_timer_irq(void *opaque, int irq, int level)
	507	{
	508	/* ??? Not connected. */
	509	}
	510
	511	static void dino_set_serial_irq(void *opaque, int irq, int level)
	512	{
	513	dino_set_irq(opaque, 10, level);
	514	}
	515
	516	PCIBus dino_init(MemoryRegion addr_space,
	517	qemu_irq p_rtc_irq, qemu_irq p_ser_irq)
	518	{
	519	DeviceState *dev;
	520	DinoState *s;
	521	PCIBus *b;
	522	int i;
	523
	524	dev = qdev_create(NULL, TYPE_DINO_PCI_HOST_BRIDGE);
	525	s = DINO_PCI_HOST_BRIDGE(dev);
18092598 HD	526	s->iar0 = s->iar1 = CPU_HPA + 3;
18092598 HD	527	s->toc_addr = 0xFFFA0030; /* IO_COMMAND of CPU */
a72bd606 HD	528
	529	/* Dino PCI access from main memory. */
	530	memory_region_init_io(&s->this_mem, OBJECT(s), &dino_chip_ops,
	531	s, "dino", 4096);
	532	memory_region_add_subregion(addr_space, DINO_HPA, &s->this_mem);
	533
	534	/* Dino PCI config. */
	535	memory_region_init_io(&s->parent_obj.conf_mem, OBJECT(&s->parent_obj),
368bec88	536	&dino_config_addr_ops, dev, "pci-conf-idx", 4);
a72bd606 HD	537	memory_region_init_io(&s->parent_obj.data_mem, OBJECT(&s->parent_obj),
	538	&dino_config_data_ops, dev, "pci-conf-data", 4);
	539	memory_region_add_subregion(&s->this_mem, DINO_PCI_CONFIG_ADDR,
	540	&s->parent_obj.conf_mem);
	541	memory_region_add_subregion(&s->this_mem, DINO_CONFIG_DATA,
	542	&s->parent_obj.data_mem);
	543
	544	/* Dino PCI bus memory. */
	545	memory_region_init(&s->pci_mem, OBJECT(s), "pci-memory", 1ull << 32);
	546
	547	b = pci_register_root_bus(dev, "pci", dino_set_irq, dino_pci_map_irq, s,
	548	&s->pci_mem, get_system_io(),
	549	PCI_DEVFN(0, 0), 32, TYPE_PCI_BUS);
	550	s->parent_obj.bus = b;
	551	qdev_init_nofail(dev);
	552
	553	/* Set up windows into PCI bus memory. */
	554	for (i = 1; i < 31; i++) {
	555	uint32_t addr = 0xf0000000 + i * DINO_MEM_CHUNK_SIZE;
	556	char *name = g_strdup_printf("PCI Outbound Window %d", i);
	557	memory_region_init_alias(&s->pci_mem_alias[i], OBJECT(s),
	558	name, &s->pci_mem, addr,
	559	DINO_MEM_CHUNK_SIZE);
266a880e	560	g_free(name);
a72bd606 HD	561	}
	562
	563	/* Set up PCI view of memory: Bus master address space. */
	564	memory_region_init(&s->bm, OBJECT(s), "bm-dino", 1ull << 32);
	565	memory_region_init_alias(&s->bm_ram_alias, OBJECT(s),
	566	"bm-system", addr_space, 0,
	567	0xf0000000 + DINO_MEM_CHUNK_SIZE);
	568	memory_region_init_alias(&s->bm_pci_alias, OBJECT(s),
	569	"bm-pci", &s->pci_mem,
	570	0xf0000000 + DINO_MEM_CHUNK_SIZE,
cb82c572 SS	571	30 * DINO_MEM_CHUNK_SIZE);
	572	memory_region_init_alias(&s->bm_cpu_alias, OBJECT(s),
	573	"bm-cpu", addr_space, 0xfff00000,
	574	0xfffff);
a72bd606 HD	575	memory_region_add_subregion(&s->bm, 0,
	576	&s->bm_ram_alias);
	577	memory_region_add_subregion(&s->bm,
	578	0xf0000000 + DINO_MEM_CHUNK_SIZE,
	579	&s->bm_pci_alias);
cb82c572 SS	580	memory_region_add_subregion(&s->bm, 0xfff00000,
cb82c572 SS	581	&s->bm_cpu_alias);
a72bd606 HD	582	address_space_init(&s->bm_as, &s->bm, "pci-bm");
	583	pci_setup_iommu(b, dino_pcihost_set_iommu, s);
	584
	585	*p_rtc_irq = qemu_allocate_irq(dino_set_timer_irq, s, 0);
	586	*p_ser_irq = qemu_allocate_irq(dino_set_serial_irq, s, 0);
	587
	588	return b;
	589	}
	590
a72bd606 HD	591	static void dino_pcihost_class_init(ObjectClass klass, void data)
a72bd606 HD	592	{
a72bd606 HD	593	DeviceClass *dc = DEVICE_CLASS(klass);
a72bd606 HD	594
a72bd606 HD	595	dc->vmsd = &vmstate_dino;
	596	}
	597
	598	static const TypeInfo dino_pcihost_info = {
	599	.name = TYPE_DINO_PCI_HOST_BRIDGE,
	600	.parent = TYPE_PCI_HOST_BRIDGE,
	601	.instance_size = sizeof(DinoState),
	602	.class_init = dino_pcihost_class_init,
	603	};
	604
	605	static void dino_register_types(void)
	606	{
	607	type_register_static(&dino_pcihost_info);
	608	}
	609
	610	type_init(dino_register_types)