]> Git Repo - qemu.git/blame - hw/blizzard.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Introduce accessors for DisplayState (Stefano Stabellini)
[qemu.git] / hw / blizzard.c
CommitLineData
7e7c5e4c
AZ		 1/*
2 * Epson S1D13744/S1D13745 (Blizzard/Hailstorm/Tornado) LCD/TV controller.
3 *
4 * Copyright (C) 2008 Nokia Corporation
5 * Written by Andrzej Zaborowski <[email protected]>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include "qemu-common.h"
24#include "sysemu.h"
25#include "console.h"
26#include "devices.h"
27#include "vga_int.h"
28#include "pixel_ops.h"
29
30typedef void (*blizzard_fn_t)(uint8_t *, const uint8_t *, unsigned int);
31
32struct blizzard_s {
33 uint8_t reg;
34 uint32_t addr;
35 int swallow;
36
37 int pll;
38 int pll_range;
39 int pll_ctrl;
40 uint8_t pll_mode;
41 uint8_t clksel;
42 int memenable;
43 int memrefresh;
44 uint8_t timing[3];
45 int priority;
46
47 uint8_t lcd_config;
48 int x;
49 int y;
50 int skipx;
51 int skipy;
52 uint8_t hndp;
53 uint8_t vndp;
54 uint8_t hsync;
55 uint8_t vsync;
56 uint8_t pclk;
57 uint8_t u;
58 uint8_t v;
59 uint8_t yrc[2];
60 int ix[2];
61 int iy[2];
62 int ox[2];
63 int oy[2];
64
65 int enable;
66 int blank;
67 int bpp;
68 int invalidate;
69 int mx[2];
70 int my[2];
71 uint8_t mode;
72 uint8_t effect;
73 uint8_t iformat;
74 uint8_t source;
75 DisplayState *state;
c60e08d9 76 QEMUConsole *console;
7e7c5e4c
AZ		 77 blizzard_fn_t *line_fn_tab[2];
78 void *fb;
79
80 uint8_t hssi_config[3];
81 uint8_t tv_config;
82 uint8_t tv_timing[4];
83 uint8_t vbi;
84 uint8_t tv_x;
85 uint8_t tv_y;
86 uint8_t tv_test;
87 uint8_t tv_filter_config;
88 uint8_t tv_filter_idx;
89 uint8_t tv_filter_coeff[0x20];
90 uint8_t border_r;
91 uint8_t border_g;
92 uint8_t border_b;
93 uint8_t gamma_config;
94 uint8_t gamma_idx;
95 uint8_t gamma_lut[0x100];
96 uint8_t matrix_ena;
97 uint8_t matrix_coeff[0x12];
98 uint8_t matrix_r;
99 uint8_t matrix_g;
100 uint8_t matrix_b;
101 uint8_t pm;
102 uint8_t status;
103 uint8_t rgbgpio_dir;
104 uint8_t rgbgpio;
105 uint8_t gpio_dir;
106 uint8_t gpio;
107 uint8_t gpio_edge[2];
108 uint8_t gpio_irq;
109 uint8_t gpio_pdown;
110
111 struct {
112 int x;
113 int y;
114 int dx;
115 int dy;
116 int len;
117 int buflen;
118 void *buf;
119 void *data;
120 uint16_t *ptr;
121 int angle;
122 int pitch;
123 blizzard_fn_t line_fn;
124 } data;
125};
126
127/* Bytes(!) per pixel */
128static const int blizzard_iformat_bpp[0x10] = {
129 0,
130 2, /* RGB 5:6:5*/
131 3, /* RGB 6:6:6 mode 1 */
132 3, /* RGB 8:8:8 mode 1 */
133 0, 0,
134 4, /* RGB 6:6:6 mode 2 */
135 4, /* RGB 8:8:8 mode 2 */
136 0, /* YUV 4:2:2 */
137 0, /* YUV 4:2:0 */
138 0, 0, 0, 0, 0, 0,
139};
140
141static inline void blizzard_rgb2yuv(int r, int g, int b,
142 int *y, int *u, int *v)
143{
144 *y = 0x10 + ((0x838 * r + 0x1022 * g + 0x322 * b) >> 13);
145 *u = 0x80 + ((0xe0e * b - 0x04c1 * r - 0x94e * g) >> 13);
146 *v = 0x80 + ((0xe0e * r - 0x0bc7 * g - 0x247 * b) >> 13);
147}
148
149static void blizzard_window(struct blizzard_s *s)
150{
151 uint8_t *src, *dst;
152 int bypp[2];
153 int bypl[3];
154 int y;
155 blizzard_fn_t fn = s->data.line_fn;
156
157 if (!fn)
158 return;
159 if (s->mx[0] > s->data.x)
160 s->mx[0] = s->data.x;
161 if (s->my[0] > s->data.y)
162 s->my[0] = s->data.y;
163 if (s->mx[1] < s->data.x + s->data.dx)
164 s->mx[1] = s->data.x + s->data.dx;
165 if (s->my[1] < s->data.y + s->data.dy)
166 s->my[1] = s->data.y + s->data.dy;
167
168 bypp[0] = s->bpp;
0e1f5a0c 169 bypp[1] = (ds_get_bits_per_pixel(s->state) + 7) >> 3;
7e7c5e4c
AZ		 170 bypl[0] = bypp[0] * s->data.pitch;
171 bypl[1] = bypp[1] * s->x;
172 bypl[2] = bypp[0] * s->data.dx;
173
174 src = s->data.data;
175 dst = s->fb + bypl[1] * s->data.y + bypp[1] * s->data.x;
176 for (y = s->data.dy; y > 0; y --, src += bypl[0], dst += bypl[1])
177 fn(dst, src, bypl[2]);
178}
179
180static int blizzard_transfer_setup(struct blizzard_s *s)
181{
182 if (s->source > 3 || !s->bpp ||
183 s->ix[1] < s->ix[0] || s->iy[1] < s->iy[0])
184 return 0;
185
186 s->data.angle = s->effect & 3;
187 s->data.line_fn = s->line_fn_tab[!!s->data.angle][s->iformat];
188 s->data.x = s->ix[0];
189 s->data.y = s->iy[0];
190 s->data.dx = s->ix[1] - s->ix[0] + 1;
191 s->data.dy = s->iy[1] - s->iy[0] + 1;
192 s->data.len = s->bpp * s->data.dx * s->data.dy;
193 s->data.pitch = s->data.dx;
194 if (s->data.len > s->data.buflen) {
2137b4cc 195 s->data.buf = qemu_realloc(s->data.buf, s->data.len);
7e7c5e4c
AZ		 196 s->data.buflen = s->data.len;
197 }
198 s->data.ptr = s->data.buf;
199 s->data.data = s->data.buf;
200 s->data.len /= 2;
201 return 1;
202}
203
204static void blizzard_reset(struct blizzard_s *s)
205{
206 s->reg = 0;
207 s->swallow = 0;
208
209 s->pll = 9;
210 s->pll_range = 1;
211 s->pll_ctrl = 0x14;
212 s->pll_mode = 0x32;
213 s->clksel = 0x00;
214 s->memenable = 0;
215 s->memrefresh = 0x25c;
216 s->timing[0] = 0x3f;
217 s->timing[1] = 0x13;
218 s->timing[2] = 0x21;
219 s->priority = 0;
220
221 s->lcd_config = 0x74;
222 s->x = 8;
223 s->y = 1;
224 s->skipx = 0;
225 s->skipy = 0;
226 s->hndp = 3;
227 s->vndp = 2;
228 s->hsync = 1;
229 s->vsync = 1;
230 s->pclk = 0x80;
231
232 s->ix[0] = 0;
233 s->ix[1] = 0;
234 s->iy[0] = 0;
235 s->iy[1] = 0;
236 s->ox[0] = 0;
237 s->ox[1] = 0;
238 s->oy[0] = 0;
239 s->oy[1] = 0;
240
241 s->yrc[0] = 0x00;
242 s->yrc[1] = 0x30;
243 s->u = 0;
244 s->v = 0;
245
246 s->iformat = 3;
247 s->source = 0;
248 s->bpp = blizzard_iformat_bpp[s->iformat];
249
250 s->hssi_config[0] = 0x00;
251 s->hssi_config[1] = 0x00;
252 s->hssi_config[2] = 0x01;
253 s->tv_config = 0x00;
254 s->tv_timing[0] = 0x00;
255 s->tv_timing[1] = 0x00;
256 s->tv_timing[2] = 0x00;
257 s->tv_timing[3] = 0x00;
258 s->vbi = 0x10;
259 s->tv_x = 0x14;
260 s->tv_y = 0x03;
261 s->tv_test = 0x00;
262 s->tv_filter_config = 0x80;
263 s->tv_filter_idx = 0x00;
264 s->border_r = 0x10;
265 s->border_g = 0x80;
266 s->border_b = 0x80;
267 s->gamma_config = 0x00;
268 s->gamma_idx = 0x00;
269 s->matrix_ena = 0x00;
270 memset(&s->matrix_coeff, 0, sizeof(s->matrix_coeff));
271 s->matrix_r = 0x00;
272 s->matrix_g = 0x00;
273 s->matrix_b = 0x00;
274 s->pm = 0x02;
275 s->status = 0x00;
276 s->rgbgpio_dir = 0x00;
277 s->gpio_dir = 0x00;
278 s->gpio_edge[0] = 0x00;
279 s->gpio_edge[1] = 0x00;
280 s->gpio_irq = 0x00;
281 s->gpio_pdown = 0xff;
282}
283
284static inline void blizzard_invalidate_display(void *opaque) {
285 struct blizzard_s *s = (struct blizzard_s *) opaque;
286
287 s->invalidate = 1;
288}
289
290static uint16_t blizzard_reg_read(void *opaque, uint8_t reg)
291{
292 struct blizzard_s *s = (struct blizzard_s *) opaque;
293
294 switch (reg) {
295 case 0x00: /* Revision Code */
296 return 0xa5;
297
298 case 0x02: /* Configuration Readback */
299 return 0x83; /* Macrovision OK, CNF[2:0] = 3 */
300
301 case 0x04: /* PLL M-Divider */
302 return (s->pll - 1) | (1 << 7);
303 case 0x06: /* PLL Lock Range Control */
304 return s->pll_range;
305 case 0x08: /* PLL Lock Synthesis Control 0 */
306 return s->pll_ctrl & 0xff;
307 case 0x0a: /* PLL Lock Synthesis Control 1 */
308 return s->pll_ctrl >> 8;
309 case 0x0c: /* PLL Mode Control 0 */
310 return s->pll_mode;
311
312 case 0x0e: /* Clock-Source Select */
313 return s->clksel;
314
315 case 0x10: /* Memory Controller Activate */
316 case 0x14: /* Memory Controller Bank 0 Status Flag */
317 return s->memenable;
318
319 case 0x18: /* Auto-Refresh Interval Setting 0 */
320 return s->memrefresh & 0xff;
321 case 0x1a: /* Auto-Refresh Interval Setting 1 */
322 return s->memrefresh >> 8;
323
324 case 0x1c: /* Power-On Sequence Timing Control */
325 return s->timing[0];
326 case 0x1e: /* Timing Control 0 */
327 return s->timing[1];
328 case 0x20: /* Timing Control 1 */
329 return s->timing[2];
330
331 case 0x24: /* Arbitration Priority Control */
332 return s->priority;
333
334 case 0x28: /* LCD Panel Configuration */
335 return s->lcd_config;
336
337 case 0x2a: /* LCD Horizontal Display Width */
338 return s->x >> 3;
339 case 0x2c: /* LCD Horizontal Non-display Period */
340 return s->hndp;
341 case 0x2e: /* LCD Vertical Display Height 0 */
342 return s->y & 0xff;
343 case 0x30: /* LCD Vertical Display Height 1 */
344 return s->y >> 8;
345 case 0x32: /* LCD Vertical Non-display Period */
346 return s->vndp;
347 case 0x34: /* LCD HS Pulse-width */
348 return s->hsync;
349 case 0x36: /* LCd HS Pulse Start Position */
350 return s->skipx >> 3;
351 case 0x38: /* LCD VS Pulse-width */
352 return s->vsync;
353 case 0x3a: /* LCD VS Pulse Start Position */
354 return s->skipy;
355
356 case 0x3c: /* PCLK Polarity */
357 return s->pclk;
358
359 case 0x3e: /* High-speed Serial Interface Tx Configuration Port 0 */
360 return s->hssi_config[0];
361 case 0x40: /* High-speed Serial Interface Tx Configuration Port 1 */
362 return s->hssi_config[1];
363 case 0x42: /* High-speed Serial Interface Tx Mode */
364 return s->hssi_config[2];
365 case 0x44: /* TV Display Configuration */
366 return s->tv_config;
367 case 0x46 ... 0x4c: /* TV Vertical Blanking Interval Data bits */
368 return s->tv_timing[(reg - 0x46) >> 1];
369 case 0x4e: /* VBI: Closed Caption / XDS Control / Status */
370 return s->vbi;
371 case 0x50: /* TV Horizontal Start Position */
372 return s->tv_x;
373 case 0x52: /* TV Vertical Start Position */
374 return s->tv_y;
375 case 0x54: /* TV Test Pattern Setting */
376 return s->tv_test;
377 case 0x56: /* TV Filter Setting */
378 return s->tv_filter_config;
379 case 0x58: /* TV Filter Coefficient Index */
380 return s->tv_filter_idx;
381 case 0x5a: /* TV Filter Coefficient Data */
382 if (s->tv_filter_idx < 0x20)
383 return s->tv_filter_coeff[s->tv_filter_idx ++];
384 return 0;
385
386 case 0x60: /* Input YUV/RGB Translate Mode 0 */
387 return s->yrc[0];
388 case 0x62: /* Input YUV/RGB Translate Mode 1 */
389 return s->yrc[1];
390 case 0x64: /* U Data Fix */
391 return s->u;
392 case 0x66: /* V Data Fix */
393 return s->v;
394
395 case 0x68: /* Display Mode */
396 return s->mode;
397
398 case 0x6a: /* Special Effects */
399 return s->effect;
400
401 case 0x6c: /* Input Window X Start Position 0 */
402 return s->ix[0] & 0xff;
403 case 0x6e: /* Input Window X Start Position 1 */
404 return s->ix[0] >> 3;
405 case 0x70: /* Input Window Y Start Position 0 */
406 return s->ix[0] & 0xff;
407 case 0x72: /* Input Window Y Start Position 1 */
408 return s->ix[0] >> 3;
409 case 0x74: /* Input Window X End Position 0 */
410 return s->ix[1] & 0xff;
411 case 0x76: /* Input Window X End Position 1 */
412 return s->ix[1] >> 3;
413 case 0x78: /* Input Window Y End Position 0 */
414 return s->ix[1] & 0xff;
415 case 0x7a: /* Input Window Y End Position 1 */
416 return s->ix[1] >> 3;
417 case 0x7c: /* Output Window X Start Position 0 */
418 return s->ox[0] & 0xff;
419 case 0x7e: /* Output Window X Start Position 1 */
420 return s->ox[0] >> 3;
421 case 0x80: /* Output Window Y Start Position 0 */
422 return s->oy[0] & 0xff;
423 case 0x82: /* Output Window Y Start Position 1 */
424 return s->oy[0] >> 3;
425 case 0x84: /* Output Window X End Position 0 */
426 return s->ox[1] & 0xff;
427 case 0x86: /* Output Window X End Position 1 */
428 return s->ox[1] >> 3;
429 case 0x88: /* Output Window Y End Position 0 */
430 return s->oy[1] & 0xff;
431 case 0x8a: /* Output Window Y End Position 1 */
432 return s->oy[1] >> 3;
433
434 case 0x8c: /* Input Data Format */
435 return s->iformat;
436 case 0x8e: /* Data Source Select */
437 return s->source;
438 case 0x90: /* Display Memory Data Port */
439 return 0;
440
441 case 0xa8: /* Border Color 0 */
442 return s->border_r;
443 case 0xaa: /* Border Color 1 */
444 return s->border_g;
445 case 0xac: /* Border Color 2 */
446 return s->border_b;
447
448 case 0xb4: /* Gamma Correction Enable */
449 return s->gamma_config;
450 case 0xb6: /* Gamma Correction Table Index */
451 return s->gamma_idx;
452 case 0xb8: /* Gamma Correction Table Data */
453 return s->gamma_lut[s->gamma_idx ++];
454
455 case 0xba: /* 3x3 Matrix Enable */
456 return s->matrix_ena;
457 case 0xbc ... 0xde: /* Coefficient Registers */
458 return s->matrix_coeff[(reg - 0xbc) >> 1];
459 case 0xe0: /* 3x3 Matrix Red Offset */
460 return s->matrix_r;
461 case 0xe2: /* 3x3 Matrix Green Offset */
462 return s->matrix_g;
463 case 0xe4: /* 3x3 Matrix Blue Offset */
464 return s->matrix_b;
465
466 case 0xe6: /* Power-save */
467 return s->pm;
468 case 0xe8: /* Non-display Period Control / Status */
469 return s->status | (1 << 5);
470 case 0xea: /* RGB Interface Control */
471 return s->rgbgpio_dir;
472 case 0xec: /* RGB Interface Status */
473 return s->rgbgpio;
474 case 0xee: /* General-purpose IO Pins Configuration */
475 return s->gpio_dir;
476 case 0xf0: /* General-purpose IO Pins Status / Control */
477 return s->gpio;
478 case 0xf2: /* GPIO Positive Edge Interrupt Trigger */
479 return s->gpio_edge[0];
480 case 0xf4: /* GPIO Negative Edge Interrupt Trigger */
481 return s->gpio_edge[1];
482 case 0xf6: /* GPIO Interrupt Status */
483 return s->gpio_irq;
484 case 0xf8: /* GPIO Pull-down Control */
485 return s->gpio_pdown;
486
487 default:
488 fprintf(stderr, "%s: unknown register %02x\n", __FUNCTION__, reg);
489 return 0;
490 }
491}
492
493static void blizzard_reg_write(void *opaque, uint8_t reg, uint16_t value)
494{
495 struct blizzard_s *s = (struct blizzard_s *) opaque;
496
497 switch (reg) {
498 case 0x04: /* PLL M-Divider */
499 s->pll = (value & 0x3f) + 1;
500 break;
501 case 0x06: /* PLL Lock Range Control */
502 s->pll_range = value & 3;
503 break;
504 case 0x08: /* PLL Lock Synthesis Control 0 */
505 s->pll_ctrl &= 0xf00;
506 s->pll_ctrl |= (value << 0) & 0x0ff;
507 break;
508 case 0x0a: /* PLL Lock Synthesis Control 1 */
509 s->pll_ctrl &= 0x0ff;
510 s->pll_ctrl |= (value << 8) & 0xf00;
511 break;
512 case 0x0c: /* PLL Mode Control 0 */
513 s->pll_mode = value & 0x77;
514 if ((value & 3) == 0 || (value & 3) == 3)
515 fprintf(stderr, "%s: wrong PLL Control bits (%i)\n",
516 __FUNCTION__, value & 3);
517 break;
518
519 case 0x0e: /* Clock-Source Select */
520 s->clksel = value & 0xff;
521 break;
522
523 case 0x10: /* Memory Controller Activate */
524 s->memenable = value & 1;
525 break;
526 case 0x14: /* Memory Controller Bank 0 Status Flag */
527 break;
528
529 case 0x18: /* Auto-Refresh Interval Setting 0 */
530 s->memrefresh &= 0xf00;
531 s->memrefresh |= (value << 0) & 0x0ff;
532 break;
533 case 0x1a: /* Auto-Refresh Interval Setting 1 */
534 s->memrefresh &= 0x0ff;
535 s->memrefresh |= (value << 8) & 0xf00;
536 break;
537
538 case 0x1c: /* Power-On Sequence Timing Control */
539 s->timing[0] = value & 0x7f;
540 break;
541 case 0x1e: /* Timing Control 0 */
542 s->timing[1] = value & 0x17;
543 break;
544 case 0x20: /* Timing Control 1 */
545 s->timing[2] = value & 0x35;
546 break;
547
548 case 0x24: /* Arbitration Priority Control */
549 s->priority = value & 1;
550 break;
551
552 case 0x28: /* LCD Panel Configuration */
553 s->lcd_config = value & 0xff;
554 if (value & (1 << 7))
555 fprintf(stderr, "%s: data swap not supported!\n", __FUNCTION__);
556 break;
557
558 case 0x2a: /* LCD Horizontal Display Width */
559 s->x = value << 3;
560 break;
561 case 0x2c: /* LCD Horizontal Non-display Period */
562 s->hndp = value & 0xff;
563 break;
564 case 0x2e: /* LCD Vertical Display Height 0 */
565 s->y &= 0x300;
566 s->y |= (value << 0) & 0x0ff;
567 break;
568 case 0x30: /* LCD Vertical Display Height 1 */
569 s->y &= 0x0ff;
570 s->y |= (value << 8) & 0x300;
571 break;
572 case 0x32: /* LCD Vertical Non-display Period */
573 s->vndp = value & 0xff;
574 break;
575 case 0x34: /* LCD HS Pulse-width */
576 s->hsync = value & 0xff;
577 break;
578 case 0x36: /* LCD HS Pulse Start Position */
579 s->skipx = value & 0xff;
580 break;
581 case 0x38: /* LCD VS Pulse-width */
582 s->vsync = value & 0xbf;
583 break;
584 case 0x3a: /* LCD VS Pulse Start Position */
585 s->skipy = value & 0xff;
586 break;
587
588 case 0x3c: /* PCLK Polarity */
589 s->pclk = value & 0x82;
590 /* Affects calculation of s->hndp, s->hsync and s->skipx. */
591 break;
592
593 case 0x3e: /* High-speed Serial Interface Tx Configuration Port 0 */
594 s->hssi_config[0] = value;
595 break;
596 case 0x40: /* High-speed Serial Interface Tx Configuration Port 1 */
597 s->hssi_config[1] = value;
598 if (((value >> 4) & 3) == 3)
599 fprintf(stderr, "%s: Illegal active-data-links value\n",
600 __FUNCTION__);
601 break;
602 case 0x42: /* High-speed Serial Interface Tx Mode */
603 s->hssi_config[2] = value & 0xbd;
604 break;
605
606 case 0x44: /* TV Display Configuration */
607 s->tv_config = value & 0xfe;
608 break;
609 case 0x46 ... 0x4c: /* TV Vertical Blanking Interval Data bits 0 */
610 s->tv_timing[(reg - 0x46) >> 1] = value;
611 break;
612 case 0x4e: /* VBI: Closed Caption / XDS Control / Status */
613 s->vbi = value;
614 break;
615 case 0x50: /* TV Horizontal Start Position */
616 s->tv_x = value;
617 break;
618 case 0x52: /* TV Vertical Start Position */
619 s->tv_y = value & 0x7f;
620 break;
621 case 0x54: /* TV Test Pattern Setting */
622 s->tv_test = value;
623 break;
624 case 0x56: /* TV Filter Setting */
625 s->tv_filter_config = value & 0xbf;
626 break;
627 case 0x58: /* TV Filter Coefficient Index */
628 s->tv_filter_idx = value & 0x1f;
629 break;
630 case 0x5a: /* TV Filter Coefficient Data */
631 if (s->tv_filter_idx < 0x20)
632 s->tv_filter_coeff[s->tv_filter_idx ++] = value;
633 break;
634
635 case 0x60: /* Input YUV/RGB Translate Mode 0 */
636 s->yrc[0] = value & 0xb0;
637 break;
638 case 0x62: /* Input YUV/RGB Translate Mode 1 */
639 s->yrc[1] = value & 0x30;
640 break;
641 case 0x64: /* U Data Fix */
642 s->u = value & 0xff;
643 break;
644 case 0x66: /* V Data Fix */
645 s->v = value & 0xff;
646 break;
647
648 case 0x68: /* Display Mode */
649 if ((s->mode ^ value) & 3)
650 s->invalidate = 1;
651 s->mode = value & 0xb7;
652 s->enable = value & 1;
653 s->blank = (value >> 1) & 1;
654 if (value & (1 << 4))
655 fprintf(stderr, "%s: Macrovision enable attempt!\n", __FUNCTION__);
656 break;
657
658 case 0x6a: /* Special Effects */
659 s->effect = value & 0xfb;
660 break;
661
662 case 0x6c: /* Input Window X Start Position 0 */
663 s->ix[0] &= 0x300;
664 s->ix[0] |= (value << 0) & 0x0ff;
665 break;
666 case 0x6e: /* Input Window X Start Position 1 */
667 s->ix[0] &= 0x0ff;
668 s->ix[0] |= (value << 8) & 0x300;
669 break;
670 case 0x70: /* Input Window Y Start Position 0 */
671 s->iy[0] &= 0x300;
672 s->iy[0] |= (value << 0) & 0x0ff;
673 break;
674 case 0x72: /* Input Window Y Start Position 1 */
675 s->iy[0] &= 0x0ff;
676 s->iy[0] |= (value << 8) & 0x300;
677 break;
678 case 0x74: /* Input Window X End Position 0 */
679 s->ix[1] &= 0x300;
680 s->ix[1] |= (value << 0) & 0x0ff;
681 break;
682 case 0x76: /* Input Window X End Position 1 */
683 s->ix[1] &= 0x0ff;
684 s->ix[1] |= (value << 8) & 0x300;
685 break;
686 case 0x78: /* Input Window Y End Position 0 */
687 s->iy[1] &= 0x300;
688 s->iy[1] |= (value << 0) & 0x0ff;
689 break;
690 case 0x7a: /* Input Window Y End Position 1 */
691 s->iy[1] &= 0x0ff;
692 s->iy[1] |= (value << 8) & 0x300;
693 break;
694 case 0x7c: /* Output Window X Start Position 0 */
695 s->ox[0] &= 0x300;
696 s->ox[0] |= (value << 0) & 0x0ff;
697 break;
698 case 0x7e: /* Output Window X Start Position 1 */
699 s->ox[0] &= 0x0ff;
700 s->ox[0] |= (value << 8) & 0x300;
701 break;
702 case 0x80: /* Output Window Y Start Position 0 */
703 s->oy[0] &= 0x300;
704 s->oy[0] |= (value << 0) & 0x0ff;
705 break;
706 case 0x82: /* Output Window Y Start Position 1 */
707 s->oy[0] &= 0x0ff;
708 s->oy[0] |= (value << 8) & 0x300;
709 break;
710 case 0x84: /* Output Window X End Position 0 */
711 s->ox[1] &= 0x300;
712 s->ox[1] |= (value << 0) & 0x0ff;
713 break;
714 case 0x86: /* Output Window X End Position 1 */
715 s->ox[1] &= 0x0ff;
716 s->ox[1] |= (value << 8) & 0x300;
717 break;
718 case 0x88: /* Output Window Y End Position 0 */
719 s->oy[1] &= 0x300;
720 s->oy[1] |= (value << 0) & 0x0ff;
721 break;
722 case 0x8a: /* Output Window Y End Position 1 */
723 s->oy[1] &= 0x0ff;
724 s->oy[1] |= (value << 8) & 0x300;
725 break;
726
727 case 0x8c: /* Input Data Format */
728 s->iformat = value & 0xf;
729 s->bpp = blizzard_iformat_bpp[s->iformat];
730 if (!s->bpp)
731 fprintf(stderr, "%s: Illegal or unsupported input format %x\n",
732 __FUNCTION__, s->iformat);
733 break;
734 case 0x8e: /* Data Source Select */
735 s->source = value & 7;
736 /* Currently all windows will be "destructive overlays". */
737 if ((!(s->effect & (1 << 3)) && (s->ix[0] != s->ox[0] ||
738 s->iy[0] != s->oy[0] ||
739 s->ix[1] != s->ox[1] ||
740 s->iy[1] != s->oy[1])) ||
741 !((s->ix[1] - s->ix[0]) & (s->iy[1] - s->iy[0]) &
742 (s->ox[1] - s->ox[0]) & (s->oy[1] - s->oy[0]) & 1))
743 fprintf(stderr, "%s: Illegal input/output window positions\n",
744 __FUNCTION__);
745
746 blizzard_transfer_setup(s);
747 break;
748
749 case 0x90: /* Display Memory Data Port */
750 if (!s->data.len && !blizzard_transfer_setup(s))
751 break;
752
753 *s->data.ptr ++ = value;
754 if (-- s->data.len == 0)
755 blizzard_window(s);
756 break;
757
758 case 0xa8: /* Border Color 0 */
759 s->border_r = value;
760 break;
761 case 0xaa: /* Border Color 1 */
762 s->border_g = value;
763 break;
764 case 0xac: /* Border Color 2 */
765 s->border_b = value;
766 break;
767
768 case 0xb4: /* Gamma Correction Enable */
769 s->gamma_config = value & 0x87;
770 break;
771 case 0xb6: /* Gamma Correction Table Index */
772 s->gamma_idx = value;
773 break;
774 case 0xb8: /* Gamma Correction Table Data */
775 s->gamma_lut[s->gamma_idx ++] = value;
776 break;
777
778 case 0xba: /* 3x3 Matrix Enable */
779 s->matrix_ena = value & 1;
780 break;
781 case 0xbc ... 0xde: /* Coefficient Registers */
782 s->matrix_coeff[(reg - 0xbc) >> 1] = value & ((reg & 2) ? 0x80 : 0xff);
783 break;
784 case 0xe0: /* 3x3 Matrix Red Offset */
785 s->matrix_r = value;
786 break;
787 case 0xe2: /* 3x3 Matrix Green Offset */
788 s->matrix_g = value;
789 break;
790 case 0xe4: /* 3x3 Matrix Blue Offset */
791 s->matrix_b = value;
792 break;
793
794 case 0xe6: /* Power-save */
795 s->pm = value & 0x83;
796 if (value & s->mode & 1)
797 fprintf(stderr, "%s: The display must be disabled before entering "
798 "Standby Mode\n", __FUNCTION__);
799 break;
800 case 0xe8: /* Non-display Period Control / Status */
801 s->status = value & 0x1b;
802 break;
803 case 0xea: /* RGB Interface Control */
804 s->rgbgpio_dir = value & 0x8f;
805 break;
806 case 0xec: /* RGB Interface Status */
807 s->rgbgpio = value & 0xcf;
808 break;
809 case 0xee: /* General-purpose IO Pins Configuration */
810 s->gpio_dir = value;
811 break;
812 case 0xf0: /* General-purpose IO Pins Status / Control */
813 s->gpio = value;
814 break;
815 case 0xf2: /* GPIO Positive Edge Interrupt Trigger */
816 s->gpio_edge[0] = value;
817 break;
818 case 0xf4: /* GPIO Negative Edge Interrupt Trigger */
819 s->gpio_edge[1] = value;
820 break;
821 case 0xf6: /* GPIO Interrupt Status */
822 s->gpio_irq &= value;
823 break;
824 case 0xf8: /* GPIO Pull-down Control */
825 s->gpio_pdown = value;
826 break;
827
828 default:
829 fprintf(stderr, "%s: unknown register %02x\n", __FUNCTION__, reg);
830 break;
831 }
832}
833
834uint16_t s1d13745_read(void *opaque, int dc)
835{
836 struct blizzard_s *s = (struct blizzard_s *) opaque;
837 uint16_t value = blizzard_reg_read(s, s->reg);
838
839 if (s->swallow -- > 0)
840 return 0;
841 if (dc)
842 s->reg ++;
843
844 return value;
845}
846
847void s1d13745_write(void *opaque, int dc, uint16_t value)
848{
849 struct blizzard_s *s = (struct blizzard_s *) opaque;
850
851 if (s->swallow -- > 0)
852 return;
853 if (dc) {
854 blizzard_reg_write(s, s->reg, value);
855
856 if (s->reg != 0x90 && s->reg != 0x5a && s->reg != 0xb8)
857 s->reg += 2;
858 } else
859 s->reg = value & 0xff;
860}
861
862void s1d13745_write_block(void *opaque, int dc,
863 void *buf, size_t len, int pitch)
864{
865 struct blizzard_s *s = (struct blizzard_s *) opaque;
866
867 while (len > 0) {
868 if (s->reg == 0x90 && dc &&
869 (s->data.len || blizzard_transfer_setup(s)) &&
870 len >= (s->data.len << 1)) {
871 len -= s->data.len << 1;
872 s->data.len = 0;
873 s->data.data = buf;
874 if (pitch)
875 s->data.pitch = pitch;
876 blizzard_window(s);
877 s->data.data = s->data.buf;
878 continue;
879 }
880
881 s1d13745_write(opaque, dc, *(uint16_t *) buf);
882 len -= 2;
883 buf += 2;
884 }
885
886 return;
887}
888
889static void blizzard_update_display(void *opaque)
890{
891 struct blizzard_s *s = (struct blizzard_s *) opaque;
892 int y, bypp, bypl, bwidth;
893 uint8_t *src, *dst;
894
895 if (!s->enable)
896 return;
897
0e1f5a0c 898 if (s->x != ds_get_width(s->state) || s->y != ds_get_height(s->state)) {
7e7c5e4c 899 s->invalidate = 1;
c60e08d9 900 qemu_console_resize(s->console, s->x, s->y);
7e7c5e4c
AZ		 901 }
902
903 if (s->invalidate) {
904 s->invalidate = 0;
905
906 if (s->blank) {
0e1f5a0c
AL		 907 bypp = (ds_get_bits_per_pixel(s->state) + 7) >> 3;
908 memset(ds_get_data(s->state), 0, bypp * s->x * s->y);
7e7c5e4c
AZ		 909 return;
910 }
911
912 s->mx[0] = 0;
913 s->mx[1] = s->x;
914 s->my[0] = 0;
915 s->my[1] = s->y;
916 }
917
918 if (s->mx[1] <= s->mx[0])
919 return;
920
0e1f5a0c 921 bypp = (ds_get_bits_per_pixel(s->state) + 7) >> 3;
7e7c5e4c
AZ		 922 bypl = bypp * s->x;
923 bwidth = bypp * (s->mx[1] - s->mx[0]);
924 y = s->my[0];
925 src = s->fb + bypl * y + bypp * s->mx[0];
0e1f5a0c 926 dst = ds_get_data(s->state) + bypl * y + bypp * s->mx[0];
7e7c5e4c
AZ		 927 for (; y < s->my[1]; y ++, src += bypl, dst += bypl)
928 memcpy(dst, src, bwidth);
929
930 dpy_update(s->state, s->mx[0], s->my[0],
931 s->mx[1] - s->mx[0], y - s->my[0]);
932
933 s->mx[0] = s->x;
934 s->mx[1] = 0;
935 s->my[0] = s->y;
936 s->my[1] = 0;
937}
938
939static void blizzard_screen_dump(void *opaque, const char *filename) {
940 struct blizzard_s *s = (struct blizzard_s *) opaque;
941
942 blizzard_update_display(opaque);
0e1f5a0c
AL		 943 if (s && ds_get_data(s->state))
944 ppm_save(filename, ds_get_data(s->state), s->x, s->y, ds_get_linesize(s->state));
7e7c5e4c
AZ		 945}
946
947#define DEPTH 8
948#include "blizzard_template.h"
949#define DEPTH 15
950#include "blizzard_template.h"
951#define DEPTH 16
952#include "blizzard_template.h"
953#define DEPTH 24
954#include "blizzard_template.h"
955#define DEPTH 32
956#include "blizzard_template.h"
957
958void *s1d13745_init(qemu_irq gpio_int, DisplayState *ds)
959{
960 struct blizzard_s *s = (struct blizzard_s *) qemu_mallocz(sizeof(*s));
961
962 s->state = ds;
963 s->fb = qemu_malloc(0x180000);
964
0e1f5a0c 965 switch (ds_get_bits_per_pixel(s->state)) {
7e7c5e4c
AZ		 966 case 0:
967 s->line_fn_tab[0] = s->line_fn_tab[1] =
968 qemu_mallocz(sizeof(blizzard_fn_t) * 0x10);
969 break;
970 case 8:
971 s->line_fn_tab[0] = blizzard_draw_fn_8;
972 s->line_fn_tab[1] = blizzard_draw_fn_r_8;
973 break;
974 case 15:
975 s->line_fn_tab[0] = blizzard_draw_fn_15;
976 s->line_fn_tab[1] = blizzard_draw_fn_r_15;
977 break;
978 case 16:
979 s->line_fn_tab[0] = blizzard_draw_fn_16;
980 s->line_fn_tab[1] = blizzard_draw_fn_r_16;
981 break;
982 case 24:
983 s->line_fn_tab[0] = blizzard_draw_fn_24;
984 s->line_fn_tab[1] = blizzard_draw_fn_r_24;
985 break;
986 case 32:
987 s->line_fn_tab[0] = blizzard_draw_fn_32;
988 s->line_fn_tab[1] = blizzard_draw_fn_r_32;
989 break;
990 default:
991 fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
992 exit(1);
993 }
994
995 blizzard_reset(s);
996
c60e08d9
PB		 997 s->console = graphic_console_init(s->state, blizzard_update_display,
998 blizzard_invalidate_display,
999 blizzard_screen_dump, NULL, s);
7e7c5e4c
AZ		 1000
1001 return s;
1002}
Empty description
This page took 0.203776 seconds and 4 git commands to generate.