[qemu.git] / target / m68k / cpu.h

/*
 * m68k virtual CPU header
 *
 *  Copyright (c) 2005-2007 CodeSourcery
 *  Written by Paul Brook
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#ifndef M68K_CPU_H
#define M68K_CPU_H

#define TARGET_LONG_BITS 32

#define CPUArchState struct CPUM68KState

#include "qemu-common.h"
#include "exec/cpu-defs.h"
#include "cpu-qom.h"
#include "fpu/softfloat.h"

#define OS_BYTE     0
#define OS_WORD     1
#define OS_LONG     2
#define OS_SINGLE   3
#define OS_DOUBLE   4
#define OS_EXTENDED 5
#define OS_PACKED   6
#define OS_UNSIZED  7

#define MAX_QREGS 32

#define EXCP_ACCESS         2   /* Access (MMU) error.  */
#define EXCP_ADDRESS        3   /* Address error.  */
#define EXCP_ILLEGAL        4   /* Illegal instruction.  */
#define EXCP_DIV0           5   /* Divide by zero */
#define EXCP_PRIVILEGE      8   /* Privilege violation.  */
#define EXCP_TRACE          9
#define EXCP_LINEA          10  /* Unimplemented line-A (MAC) opcode.  */
#define EXCP_LINEF          11  /* Unimplemented line-F (FPU) opcode.  */
#define EXCP_DEBUGNBP       12  /* Non-breakpoint debug interrupt.  */
#define EXCP_DEBEGBP        13  /* Breakpoint debug interrupt.  */
#define EXCP_FORMAT         14  /* RTE format error.  */
#define EXCP_UNINITIALIZED  15
#define EXCP_TRAP0          32   /* User trap #0.  */
#define EXCP_TRAP15         47   /* User trap #15.  */
#define EXCP_FP_BSUN        48 /* Branch Set on Unordered */
#define EXCP_FP_INEX        49 /* Inexact result */
#define EXCP_FP_DZ          50 /* Divide by Zero */
#define EXCP_FP_UNFL        51 /* Underflow */
#define EXCP_FP_OPERR       52 /* Operand Error */
#define EXCP_FP_OVFL        53 /* Overflow */
#define EXCP_FP_SNAN        54 /* Signaling Not-A-Number */
#define EXCP_FP_UNIMP       55 /* Unimplemented Data type */
#define EXCP_UNSUPPORTED    61

#define EXCP_RTE            0x100
#define EXCP_HALT_INSN      0x101

#define NB_MMU_MODES 2
#define TARGET_INSN_START_EXTRA_WORDS 1

typedef CPU_LDoubleU FPReg;

typedef struct CPUM68KState {
    uint32_t dregs[8];
    uint32_t aregs[8];
    uint32_t pc;
    uint32_t sr;

    /* SSP and USP.  The current_sp is stored in aregs[7], the other here.  */
    int current_sp;
    uint32_t sp[2];

    /* Condition flags.  */
    uint32_t cc_op;
    uint32_t cc_x; /* always 0/1 */
    uint32_t cc_n; /* in bit 31 (i.e. negative) */
    uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */
    uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */
    uint32_t cc_z; /* == 0 or unused */

    FPReg fregs[8];
    FPReg fp_result;
    uint32_t fpcr;
    uint32_t fpsr;
    float_status fp_status;

    uint64_t mactmp;
    /* EMAC Hardware deals with 48-bit values composed of one 32-bit and
       two 8-bit parts.  We store a single 64-bit value and
       rearrange/extend this when changing modes.  */
    uint64_t macc[4];
    uint32_t macsr;
    uint32_t mac_mask;

    /* MMU status.  */
    struct {
        uint32_t ar;
    } mmu;

    /* Control registers.  */
    uint32_t vbr;
    uint32_t mbar;
    uint32_t rambar0;
    uint32_t cacr;

    int pending_vector;
    int pending_level;

    uint32_t qregs[MAX_QREGS];

    /* Fields up to this point are cleared by a CPU reset */
    struct {} end_reset_fields;

    CPU_COMMON

    /* Fields from here on are preserved across CPU reset. */
    uint32_t features;
} CPUM68KState;

/**
 * M68kCPU:
 * @env: #CPUM68KState
 *
 * A Motorola 68k CPU.
 */
struct M68kCPU {
    /*< private >*/
    CPUState parent_obj;
    /*< public >*/

    CPUM68KState env;
};

static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env)
{
    return container_of(env, M68kCPU, env);
}

#define ENV_GET_CPU(e) CPU(m68k_env_get_cpu(e))

#define ENV_OFFSET offsetof(M68kCPU, env)

void m68k_cpu_do_interrupt(CPUState *cpu);
bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);
void m68k_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
                         int flags);
hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);

void m68k_tcg_init(void);
void m68k_cpu_init_gdb(M68kCPU *cpu);
M68kCPU *cpu_m68k_init(const char *cpu_model);
/* you can call this signal handler from your SIGBUS and SIGSEGV
   signal handlers to inform the virtual CPU of exceptions. non zero
   is returned if the signal was handled by the virtual CPU.  */
int cpu_m68k_signal_handler(int host_signum, void *pinfo,
                           void *puc);
uint32_t cpu_m68k_get_ccr(CPUM68KState *env);
void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t);
void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val);


/* Instead of computing the condition codes after each m68k instruction,
 * QEMU just stores one operand (called CC_SRC), the result
 * (called CC_DEST) and the type of operation (called CC_OP). When the
 * condition codes are needed, the condition codes can be calculated
 * using this information. Condition codes are not generated if they
 * are only needed for conditional branches.
 */
typedef enum {
    /* Translator only -- use env->cc_op.  */
    CC_OP_DYNAMIC = -1,

    /* Each flag bit computed into cc_[xcnvz].  */
    CC_OP_FLAGS,

    /* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v.  */
    CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL,
    CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL,

    /* X in cc_x, {N,Z,C,V} via cc_n/cc_v.  */
    CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL,

    /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n.  */
    CC_OP_LOGIC,

    CC_OP_NB
} CCOp;

#define CCF_C 0x01
#define CCF_V 0x02
#define CCF_Z 0x04
#define CCF_N 0x08
#define CCF_X 0x10

#define SR_I_SHIFT 8
#define SR_I  0x0700
#define SR_M  0x1000
#define SR_S  0x2000
#define SR_T  0x8000

#define M68K_SSP    0
#define M68K_USP    1

#define M68K_FPIAR_SHIFT  0
#define M68K_FPIAR        (1 << M68K_FPIAR_SHIFT)
#define M68K_FPSR_SHIFT   1
#define M68K_FPSR         (1 << M68K_FPSR_SHIFT)
#define M68K_FPCR_SHIFT   2
#define M68K_FPCR         (1 << M68K_FPCR_SHIFT)

/* Floating-Point Status Register */

/* Condition Code */
#define FPSR_CC_MASK  0x0f000000
#define FPSR_CC_A     0x01000000 /* Not-A-Number */
#define FPSR_CC_I     0x02000000 /* Infinity */
#define FPSR_CC_Z     0x04000000 /* Zero */
#define FPSR_CC_N     0x08000000 /* Negative */

/* Quotient */

#define FPSR_QT_MASK  0x00ff0000

/* Floating-Point Control Register */
/* Rounding mode */
#define FPCR_RND_MASK   0x0030
#define FPCR_RND_N      0x0000
#define FPCR_RND_Z      0x0010
#define FPCR_RND_M      0x0020
#define FPCR_RND_P      0x0030

/* Rounding precision */
#define FPCR_PREC_MASK  0x00c0
#define FPCR_PREC_X     0x0000
#define FPCR_PREC_S     0x0040
#define FPCR_PREC_D     0x0080
#define FPCR_PREC_U     0x00c0

#define FPCR_EXCP_MASK 0xff00

/* CACR fields are implementation defined, but some bits are common.  */
#define M68K_CACR_EUSP  0x10

#define MACSR_PAV0  0x100
#define MACSR_OMC   0x080
#define MACSR_SU    0x040
#define MACSR_FI    0x020
#define MACSR_RT    0x010
#define MACSR_N     0x008
#define MACSR_Z     0x004
#define MACSR_V     0x002
#define MACSR_EV    0x001

void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector);
void m68k_switch_sp(CPUM68KState *env);

void do_m68k_semihosting(CPUM68KState *env, int nr);

/* There are 4 ColdFire core ISA revisions: A, A+, B and C.
   Each feature covers the subset of instructions common to the
   ISA revisions mentioned.  */

enum m68k_features {
    M68K_FEATURE_M68000,
    M68K_FEATURE_CF_ISA_A,
    M68K_FEATURE_CF_ISA_B, /* (ISA B or C).  */
    M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C).  */
    M68K_FEATURE_BRAL, /* Long unconditional branch.  (ISA A+ or B).  */
    M68K_FEATURE_CF_FPU,
    M68K_FEATURE_CF_MAC,
    M68K_FEATURE_CF_EMAC,
    M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate).  */
    M68K_FEATURE_USP, /* User Stack Pointer.  (ISA A+, B or C).  */
    M68K_FEATURE_EXT_FULL, /* 68020+ full extension word.  */
    M68K_FEATURE_WORD_INDEX, /* word sized address index registers.  */
    M68K_FEATURE_SCALED_INDEX, /* scaled address index registers.  */
    M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */
    M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */
    M68K_FEATURE_BCCL, /* Long conditional branches.  */
    M68K_FEATURE_BITFIELD, /* Bit field insns.  */
    M68K_FEATURE_FPU,
    M68K_FEATURE_CAS,
    M68K_FEATURE_BKPT,
    M68K_FEATURE_RTD,
};

static inline int m68k_feature(CPUM68KState *env, int feature)
{
    return (env->features & (1u << feature)) != 0;
}

void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf);

void register_m68k_insns (CPUM68KState *env);

#ifdef CONFIG_USER_ONLY
/* Coldfire Linux uses 8k pages
 * and m68k linux uses 4k pages
 * use the smaller one
 */
#define TARGET_PAGE_BITS 12
#else
/* Smallest TLB entry size is 1k.  */
#define TARGET_PAGE_BITS 10
#endif

#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32

#define cpu_init(cpu_model) CPU(cpu_m68k_init(cpu_model))

#define cpu_signal_handler cpu_m68k_signal_handler
#define cpu_list m68k_cpu_list

/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch)
{
    return (env->sr & SR_S) == 0 ? 1 : 0;
}

int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
                              int mmu_idx);

#include "exec/cpu-all.h"

static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc,
                                        target_ulong *cs_base, uint32_t *flags)
{
    *pc = env->pc;
    *cs_base = 0;
    *flags = (env->sr & SR_S)                   /* Bit  13 */
            | ((env->macsr >> 4) & 0xf);        /* Bits 0-3 */
}

#endif
Commit	Line	Data
e6e5906b PB	1	/*
e6e5906b PB	2	* m68k virtual CPU header
5fafdf24	3	*
0633879f	4	* Copyright (c) 2005-2007 CodeSourcery
e6e5906b PB	5	* Written by Paul Brook
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
8167ee88	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
e6e5906b	19	*/
07f5a258 MA	20
	21	#ifndef M68K_CPU_H
	22	#define M68K_CPU_H
e6e5906b PB	23
	24	#define TARGET_LONG_BITS 32
	25
9349b4f9	26	#define CPUArchState struct CPUM68KState
c2764719	27
9a78eead	28	#include "qemu-common.h"
022c62cb	29	#include "exec/cpu-defs.h"
a836b8fa	30	#include "cpu-qom.h"
6b4c305c	31	#include "fpu/softfloat.h"
e6e5906b	32
7ef25cdd LV	33	#define OS_BYTE 0
	34	#define OS_WORD 1
	35	#define OS_LONG 2
	36	#define OS_SINGLE 3
	37	#define OS_DOUBLE 4
	38	#define OS_EXTENDED 5
	39	#define OS_PACKED 6
f2224f2c	40	#define OS_UNSIZED 7
7ef25cdd	41
e6e5906b PB	42	#define MAX_QREGS 32
e6e5906b PB	43
e6e5906b PB	44	#define EXCP_ACCESS 2 /* Access (MMU) error. */
	45	#define EXCP_ADDRESS 3 /* Address error. */
	46	#define EXCP_ILLEGAL 4 /* Illegal instruction. */
	47	#define EXCP_DIV0 5 /* Divide by zero */
	48	#define EXCP_PRIVILEGE 8 /* Privilege violation. */
	49	#define EXCP_TRACE 9
	50	#define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */
	51	#define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */
	52	#define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */
	53	#define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */
	54	#define EXCP_FORMAT 14 /* RTE format error. */
	55	#define EXCP_UNINITIALIZED 15
	56	#define EXCP_TRAP0 32 /* User trap #0. */
	57	#define EXCP_TRAP15 47 /* User trap #15. */
f83311e4 LV	58	#define EXCP_FP_BSUN 48 /* Branch Set on Unordered */
	59	#define EXCP_FP_INEX 49 /* Inexact result */
	60	#define EXCP_FP_DZ 50 /* Divide by Zero */
	61	#define EXCP_FP_UNFL 51 /* Underflow */
	62	#define EXCP_FP_OPERR 52 /* Operand Error */
	63	#define EXCP_FP_OVFL 53 /* Overflow */
	64	#define EXCP_FP_SNAN 54 /* Signaling Not-A-Number */
	65	#define EXCP_FP_UNIMP 55 /* Unimplemented Data type */
e6e5906b	66	#define EXCP_UNSUPPORTED 61
e6e5906b	67
0633879f	68	#define EXCP_RTE 0x100
a87295e8	69	#define EXCP_HALT_INSN 0x101
0633879f	70
6ebbf390	71	#define NB_MMU_MODES 2
20a8856e	72	#define TARGET_INSN_START_EXTRA_WORDS 1
6ebbf390	73
f83311e4 LV	74	typedef CPU_LDoubleU FPReg;
f83311e4 LV	75
e6e5906b PB	76	typedef struct CPUM68KState {
	77	uint32_t dregs[8];
	78	uint32_t aregs[8];
	79	uint32_t pc;
	80	uint32_t sr;
	81
20dcee94 PB	82	/* SSP and USP. The current_sp is stored in aregs[7], the other here. */
	83	int current_sp;
	84	uint32_t sp[2];
	85
e6e5906b PB	86	/* Condition flags. */
e6e5906b PB	87	uint32_t cc_op;
620c6cf6 RH	88	uint32_t cc_x; /* always 0/1 */
	89	uint32_t cc_n; /* in bit 31 (i.e. negative) */
	90	uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */
	91	uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */
	92	uint32_t cc_z; /* == 0 or unused */
e6e5906b	93
f83311e4 LV	94	FPReg fregs[8];
f83311e4 LV	95	FPReg fp_result;
e6e5906b PB	96	uint32_t fpcr;
	97	uint32_t fpsr;
	98	float_status fp_status;
	99
acf930aa PB	100	uint64_t mactmp;
	101	/* EMAC Hardware deals with 48-bit values composed of one 32-bit and
	102	two 8-bit parts. We store a single 64-bit value and
	103	rearrange/extend this when changing modes. */
	104	uint64_t macc[4];
	105	uint32_t macsr;
	106	uint32_t mac_mask;
	107
e6e5906b PB	108	/* MMU status. */
	109	struct {
	110	uint32_t ar;
	111	} mmu;
0633879f PB	112
	113	/* Control registers. */
	114	uint32_t vbr;
	115	uint32_t mbar;
	116	uint32_t rambar0;
20dcee94	117	uint32_t cacr;
0633879f	118
0633879f PB	119	int pending_vector;
0633879f PB	120	int pending_level;
e6e5906b PB	121
	122	uint32_t qregs[MAX_QREGS];
	123
1f5c00cf AB	124	/* Fields up to this point are cleared by a CPU reset */
	125	struct {} end_reset_fields;
	126
e6e5906b	127	CPU_COMMON
aaed909a	128
f0c3c505	129	/* Fields from here on are preserved across CPU reset. */
aaed909a	130	uint32_t features;
e6e5906b PB	131	} CPUM68KState;
e6e5906b PB	132
a836b8fa PB	133	/**
	134	* M68kCPU:
	135	* @env: #CPUM68KState
	136	*
	137	* A Motorola 68k CPU.
	138	*/
	139	struct M68kCPU {
	140	/< private >/
	141	CPUState parent_obj;
	142	/< public >/
	143
	144	CPUM68KState env;
	145	};
	146
	147	static inline M68kCPU m68k_env_get_cpu(CPUM68KState env)
	148	{
	149	return container_of(env, M68kCPU, env);
	150	}
	151
	152	#define ENV_GET_CPU(e) CPU(m68k_env_get_cpu(e))
	153
	154	#define ENV_OFFSET offsetof(M68kCPU, env)
	155
	156	void m68k_cpu_do_interrupt(CPUState *cpu);
	157	bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);
	158	void m68k_cpu_dump_state(CPUState cpu, FILE f, fprintf_function cpu_fprintf,
	159	int flags);
	160	hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
	161	int m68k_cpu_gdb_read_register(CPUState cpu, uint8_t buf, int reg);
	162	int m68k_cpu_gdb_write_register(CPUState cpu, uint8_t buf, int reg);
	163
e1f3808e	164	void m68k_tcg_init(void);
6d1bbc62	165	void m68k_cpu_init_gdb(M68kCPU *cpu);
c7937d9f	166	M68kCPU cpu_m68k_init(const char cpu_model);
e6e5906b PB	167	/* you can call this signal handler from your SIGBUS and SIGSEGV
	168	signal handlers to inform the virtual CPU of exceptions. non zero
	169	is returned if the signal was handled by the virtual CPU. */
5fafdf24	170	int cpu_m68k_signal_handler(int host_signum, void *pinfo,
e6e5906b	171	void *puc);
99c51448 RH	172	uint32_t cpu_m68k_get_ccr(CPUM68KState *env);
99c51448 RH	173	void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t);
ba624944	174	void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val);
e6e5906b	175
c3ce5a23 PB	176
	177	/* Instead of computing the condition codes after each m68k instruction,
	178	* QEMU just stores one operand (called CC_SRC), the result
	179	* (called CC_DEST) and the type of operation (called CC_OP). When the
	180	* condition codes are needed, the condition codes can be calculated
	181	* using this information. Condition codes are not generated if they
	182	* are only needed for conditional branches.
	183	*/
9fdb533f	184	typedef enum {
620c6cf6 RH	185	/* Translator only -- use env->cc_op. */
	186	CC_OP_DYNAMIC = -1,
	187
	188	/* Each flag bit computed into cc_[xcnvz]. */
	189	CC_OP_FLAGS,
	190
	191	/* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v. */
db3d7945 LV	192	CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL,
db3d7945 LV	193	CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL,
620c6cf6 RH	194
620c6cf6 RH	195	/* X in cc_x, {N,Z,C,V} via cc_n/cc_v. */
db3d7945	196	CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL,
620c6cf6 RH	197
	198	/* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n. */
	199	CC_OP_LOGIC,
	200
	201	CC_OP_NB
9fdb533f	202	} CCOp;
e6e5906b PB	203
	204	#define CCF_C 0x01
	205	#define CCF_V 0x02
	206	#define CCF_Z 0x04
	207	#define CCF_N 0x08
0633879f PB	208	#define CCF_X 0x10
	209
	210	#define SR_I_SHIFT 8
	211	#define SR_I 0x0700
	212	#define SR_M 0x1000
	213	#define SR_S 0x2000
	214	#define SR_T 0x8000
e6e5906b	215
20dcee94 PB	216	#define M68K_SSP 0
	217	#define M68K_USP 1
	218
ba624944 LV	219	#define M68K_FPIAR_SHIFT 0
	220	#define M68K_FPIAR (1 << M68K_FPIAR_SHIFT)
	221	#define M68K_FPSR_SHIFT 1
	222	#define M68K_FPSR (1 << M68K_FPSR_SHIFT)
	223	#define M68K_FPCR_SHIFT 2
	224	#define M68K_FPCR (1 << M68K_FPCR_SHIFT)
	225
	226	/* Floating-Point Status Register */
	227
	228	/* Condition Code */
	229	#define FPSR_CC_MASK 0x0f000000
	230	#define FPSR_CC_A 0x01000000 /* Not-A-Number */
	231	#define FPSR_CC_I 0x02000000 /* Infinity */
	232	#define FPSR_CC_Z 0x04000000 /* Zero */
	233	#define FPSR_CC_N 0x08000000 /* Negative */
	234
	235	/* Quotient */
	236
	237	#define FPSR_QT_MASK 0x00ff0000
	238
	239	/* Floating-Point Control Register */
	240	/* Rounding mode */
	241	#define FPCR_RND_MASK 0x0030
	242	#define FPCR_RND_N 0x0000
	243	#define FPCR_RND_Z 0x0010
	244	#define FPCR_RND_M 0x0020
	245	#define FPCR_RND_P 0x0030
	246
	247	/* Rounding precision */
	248	#define FPCR_PREC_MASK 0x00c0
	249	#define FPCR_PREC_X 0x0000
	250	#define FPCR_PREC_S 0x0040
	251	#define FPCR_PREC_D 0x0080
	252	#define FPCR_PREC_U 0x00c0
	253
	254	#define FPCR_EXCP_MASK 0xff00
	255
20dcee94 PB	256	/* CACR fields are implementation defined, but some bits are common. */
	257	#define M68K_CACR_EUSP 0x10
	258
acf930aa PB	259	#define MACSR_PAV0 0x100
	260	#define MACSR_OMC 0x080
	261	#define MACSR_SU 0x040
	262	#define MACSR_FI 0x020
	263	#define MACSR_RT 0x010
	264	#define MACSR_N 0x008
	265	#define MACSR_Z 0x004
	266	#define MACSR_V 0x002
	267	#define MACSR_EV 0x001
	268
cb3fb38e	269	void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector);
20dcee94	270	void m68k_switch_sp(CPUM68KState *env);
e6e5906b	271
a87295e8 PB	272	void do_m68k_semihosting(CPUM68KState *env, int nr);
a87295e8 PB	273
d315c888 PB	274	/* There are 4 ColdFire core ISA revisions: A, A+, B and C.
	275	Each feature covers the subset of instructions common to the
	276	ISA revisions mentioned. */
	277
0402f767	278	enum m68k_features {
f076803b	279	M68K_FEATURE_M68000,
0402f767	280	M68K_FEATURE_CF_ISA_A,
d315c888 PB	281	M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */
	282	M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */
	283	M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */
0402f767 PB	284	M68K_FEATURE_CF_FPU,
	285	M68K_FEATURE_CF_MAC,
	286	M68K_FEATURE_CF_EMAC,
d315c888 PB	287	M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */
d315c888 PB	288	M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */
e6dbd3b3	289	M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */
f076803b LV	290	M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */
	291	M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */
	292	M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */
	293	M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */
	294	M68K_FEATURE_BCCL, /* Long conditional branches. */
	295	M68K_FEATURE_BITFIELD, /* Bit field insns. */
	296	M68K_FEATURE_FPU,
	297	M68K_FEATURE_CAS,
	298	M68K_FEATURE_BKPT,
18059c9e	299	M68K_FEATURE_RTD,
0402f767 PB	300	};
	301
	302	static inline int m68k_feature(CPUM68KState *env, int feature)
	303	{
	304	return (env->features & (1u << feature)) != 0;
	305	}
	306
9a78eead	307	void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf);
009a4356	308
0402f767 PB	309	void register_m68k_insns (CPUM68KState *env);
0402f767 PB	310
e6e5906b	311	#ifdef CONFIG_USER_ONLY
2b04e85a LV	312	/* Coldfire Linux uses 8k pages
	313	* and m68k linux uses 4k pages
	314	* use the smaller one
	315	*/
	316	#define TARGET_PAGE_BITS 12
e6e5906b	317	#else
5fafdf24	318	/* Smallest TLB entry size is 1k. */
e6e5906b PB	319	#define TARGET_PAGE_BITS 10
e6e5906b PB	320	#endif
9467d44c	321
52705890 RH	322	#define TARGET_PHYS_ADDR_SPACE_BITS 32
	323	#define TARGET_VIRT_ADDR_SPACE_BITS 32
	324
2994fd96	325	#define cpu_init(cpu_model) CPU(cpu_m68k_init(cpu_model))
c7937d9f	326
9467d44c	327	#define cpu_signal_handler cpu_m68k_signal_handler
009a4356	328	#define cpu_list m68k_cpu_list
9467d44c	329
6ebbf390 JM	330	/* MMU modes definitions */
	331	#define MMU_MODE0_SUFFIX _kernel
	332	#define MMU_MODE1_SUFFIX _user
	333	#define MMU_USER_IDX 1
97ed5ccd	334	static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch)
6ebbf390 JM	335	{
	336	return (env->sr & SR_S) == 0 ? 1 : 0;
	337	}
	338
7510454e	339	int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
97b348e7	340	int mmu_idx);
aaedd1f9	341
022c62cb	342	#include "exec/cpu-all.h"
622ed360	343
2b3e3cfe	344	static inline void cpu_get_tb_cpu_state(CPUM68KState env, target_ulong pc,
89fee74a	345	target_ulong cs_base, uint32_t flags)
6b917547 AL	346	{
	347	*pc = env->pc;
	348	*cs_base = 0;
ba624944	349	flags = (env->sr & SR_S) / Bit 13 */
6b917547 AL	350	\| ((env->macsr >> 4) & 0xf); /* Bits 0-3 */
	351	}
	352
e6e5906b	353	#endif