[qemu.git] / hw / mips_jazz.c

/*
 * QEMU MIPS Jazz support
 *
 * Copyright (c) 2007-2008 Hervé Poussineau
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "hw.h"
#include "mips.h"
#include "pc.h"
#include "isa.h"
#include "fdc.h"
#include "sysemu.h"
#include "audio/audio.h"
#include "boards.h"
#include "net.h"
#include "scsi.h"

#ifdef TARGET_WORDS_BIGENDIAN
#define BIOS_FILENAME "mips_bios.bin"
#else
#define BIOS_FILENAME "mipsel_bios.bin"
#endif

enum jazz_model_e
{
    JAZZ_MAGNUM,
    JAZZ_PICA61,
};

static void main_cpu_reset(void *opaque)
{
    CPUState *env = opaque;
    cpu_reset(env);
}

static uint32_t rtc_readb(void *opaque, target_phys_addr_t addr)
{
    CPUState *env = opaque;
    return cpu_inw(env, 0x71);
}

static void rtc_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    CPUState *env = opaque;
    cpu_outw(env, 0x71, val & 0xff);
}

static CPUReadMemoryFunc *rtc_read[3] = {
    rtc_readb,
    rtc_readb,
    rtc_readb,
};

static CPUWriteMemoryFunc *rtc_write[3] = {
    rtc_writeb,
    rtc_writeb,
    rtc_writeb,
};

static void dma_dummy_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    /* Nothing to do. That is only to ensure that
     * the current DMA acknowledge cycle is completed. */
}

static CPUReadMemoryFunc *dma_dummy_read[3] = {
    NULL,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc *dma_dummy_write[3] = {
    dma_dummy_writeb,
    dma_dummy_writeb,
    dma_dummy_writeb,
};

#ifdef HAS_AUDIO
static void audio_init(qemu_irq *pic)
{
    struct soundhw *c;
    int audio_enabled = 0;

    for (c = soundhw; !audio_enabled && c->name; ++c) {
        audio_enabled = c->enabled;
    }

    if (audio_enabled) {
        AudioState *s;

        s = AUD_init();
        for (c = soundhw; c->name; ++c) {
            if (c->enabled) {
                if (c->isa) {
                    c->init.init_isa(s, pic);
                }
            }
        }
    }
}
#endif

#define MAGNUM_BIOS_SIZE_MAX 0x7e000
#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)

static
void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size,
                     const char *cpu_model,
                     enum jazz_model_e jazz_model)
{
    char buf[1024];
    int bios_size, n;
    CPUState *env;
    qemu_irq *rc4030, *i8259;
    rc4030_dma *dmas;
    void* rc4030_opaque;
    void *scsi_hba;
    int hd;
    int s_rtc, s_dma_dummy;
    NICInfo *nd;
    PITState *pit;
    BlockDriverState *fds[MAX_FD];
    qemu_irq esp_reset;
    ram_addr_t ram_offset;
    ram_addr_t bios_offset;

    /* init CPUs */
    if (cpu_model == NULL) {
#ifdef TARGET_MIPS64
        cpu_model = "R4000";
#else
        /* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
        cpu_model = "24Kf";
#endif
    }
    env = cpu_init(cpu_model);
    if (!env) {
        fprintf(stderr, "Unable to find CPU definition\n");
        exit(1);
    }
    qemu_register_reset(main_cpu_reset, env);

    /* allocate RAM */
    ram_offset = qemu_ram_alloc(ram_size);
    cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);

    bios_offset = qemu_ram_alloc(MAGNUM_BIOS_SIZE);
    cpu_register_physical_memory(0x1fc00000LL,
                                 MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
    cpu_register_physical_memory(0xfff00000LL,
                                 MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);

    /* load the BIOS image. */
    if (bios_name == NULL)
        bios_name = BIOS_FILENAME;
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
    bios_size = load_image_targphys(buf, 0xfff00000LL, MAGNUM_BIOS_SIZE);
    if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) {
        fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
                buf);
        exit(1);
    }

    /* Init CPU internal devices */
    cpu_mips_irq_init_cpu(env);
    cpu_mips_clock_init(env);

    /* Chipset */
    rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas);
    s_dma_dummy = cpu_register_io_memory(0, dma_dummy_read, dma_dummy_write, NULL);
    cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy);

    /* ISA devices */
    i8259 = i8259_init(env->irq[4]);
    DMA_init(0);
    pit = pit_init(0x40, i8259[0]);
    pcspk_init(pit);

    /* ISA IO space at 0x90000000 */
    isa_mmio_init(0x90000000, 0x01000000);
    isa_mem_base = 0x11000000;

    /* Video card */
    switch (jazz_model) {
    case JAZZ_MAGNUM:
        g364fb_mm_init(vga_ram_size, 0x40000000, 0x60000000, 0, rc4030[3]);
        break;
    case JAZZ_PICA61:
        isa_vga_mm_init(vga_ram_size, 0x40000000, 0x60000000, 0);
        break;
    default:
        break;
    }

    /* Network controller */
    for (n = 0; n < nb_nics; n++) {
        nd = &nd_table[n];
        if (!nd->model)
            nd->model = "dp83932";
        if (strcmp(nd->model, "dp83932") == 0) {
            dp83932_init(nd, 0x80001000, 2, rc4030[4],
                         rc4030_opaque, rc4030_dma_memory_rw);
            break;
        } else if (strcmp(nd->model, "?") == 0) {
            fprintf(stderr, "qemu: Supported NICs: dp83932\n");
            exit(1);
        } else {
            fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
            exit(1);
        }
    }

    /* SCSI adapter */
    scsi_hba = esp_init(0x80002000, 0,
                        rc4030_dma_read, rc4030_dma_write, dmas[0],
                        rc4030[5], &esp_reset);
    for (n = 0; n < ESP_MAX_DEVS; n++) {
        hd = drive_get_index(IF_SCSI, 0, n);
        if (hd != -1) {
            esp_scsi_attach(scsi_hba, drives_table[hd].bdrv, n);
        }
    }

    /* Floppy */
    if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
        fprintf(stderr, "qemu: too many floppy drives\n");
        exit(1);
    }
    for (n = 0; n < MAX_FD; n++) {
        int fd = drive_get_index(IF_FLOPPY, 0, n);
        if (fd != -1)
            fds[n] = drives_table[fd].bdrv;
        else
            fds[n] = NULL;
    }
    fdctrl_init(rc4030[1], 0, 1, 0x80003000, fds);

    /* Real time clock */
    rtc_init(0x70, i8259[8], 1980);
    s_rtc = cpu_register_io_memory(0, rtc_read, rtc_write, env);
    cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc);

    /* Keyboard (i8042) */
    i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1);

    /* Serial ports */
    if (serial_hds[0])
        serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1);
    if (serial_hds[1])
        serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1);

    /* Parallel port */
    if (parallel_hds[0])
        parallel_mm_init(0x80008000, 0, rc4030[0], parallel_hds[0]);

    /* Sound card */
    /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
#ifdef HAS_AUDIO
    audio_init(i8259);
#endif

    /* NVRAM: Unprotected at 0x9000, Protected at 0xa000, Read only at 0xb000 */
    ds1225y_init(0x80009000, "nvram");

    /* LED indicator */
    jazz_led_init(0x8000f000);
}

static
void mips_magnum_init (ram_addr_t ram_size, int vga_ram_size,
                       const char *boot_device,
                       const char *kernel_filename, const char *kernel_cmdline,
                       const char *initrd_filename, const char *cpu_model)
{
    mips_jazz_init(ram_size, vga_ram_size, cpu_model, JAZZ_MAGNUM);
}

static
void mips_pica61_init (ram_addr_t ram_size, int vga_ram_size,
                       const char *boot_device,
                       const char *kernel_filename, const char *kernel_cmdline,
                       const char *initrd_filename, const char *cpu_model)
{
    mips_jazz_init(ram_size, vga_ram_size, cpu_model, JAZZ_PICA61);
}

QEMUMachine mips_magnum_machine = {
    .name = "magnum",
    .desc = "MIPS Magnum",
    .init = mips_magnum_init,
    .use_scsi = 1,
};

QEMUMachine mips_pica61_machine = {
    .name = "pica61",
    .desc = "Acer Pica 61",
    .init = mips_pica61_init,
    .use_scsi = 1,
};
Commit	Line	Data
4ce7ff6e AJ	1	/*
	2	* QEMU MIPS Jazz support
	3	*
	4	* Copyright (c) 2007-2008 Hervé Poussineau
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	#include "hw.h"
	26	#include "mips.h"
	27	#include "pc.h"
	28	#include "isa.h"
	29	#include "fdc.h"
	30	#include "sysemu.h"
	31	#include "audio/audio.h"
	32	#include "boards.h"
	33	#include "net.h"
	34	#include "scsi.h"
	35
4ce7ff6e AJ	36	#ifdef TARGET_WORDS_BIGENDIAN
	37	#define BIOS_FILENAME "mips_bios.bin"
	38	#else
	39	#define BIOS_FILENAME "mipsel_bios.bin"
	40	#endif
	41
4ce7ff6e AJ	42	enum jazz_model_e
	43	{
	44	JAZZ_MAGNUM,
c171148c	45	JAZZ_PICA61,
4ce7ff6e AJ	46	};
	47
	48	static void main_cpu_reset(void *opaque)
	49	{
	50	CPUState *env = opaque;
	51	cpu_reset(env);
	52	}
	53
	54	static uint32_t rtc_readb(void *opaque, target_phys_addr_t addr)
	55	{
	56	CPUState *env = opaque;
	57	return cpu_inw(env, 0x71);
	58	}
	59
	60	static void rtc_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
	61	{
	62	CPUState *env = opaque;
	63	cpu_outw(env, 0x71, val & 0xff);
	64	}
	65
	66	static CPUReadMemoryFunc *rtc_read[3] = {
	67	rtc_readb,
	68	rtc_readb,
	69	rtc_readb,
	70	};
	71
	72	static CPUWriteMemoryFunc *rtc_write[3] = {
	73	rtc_writeb,
	74	rtc_writeb,
	75	rtc_writeb,
	76	};
	77
c6945b15 AJ	78	static void dma_dummy_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
	79	{
	80	/* Nothing to do. That is only to ensure that
	81	* the current DMA acknowledge cycle is completed. */
	82	}
	83
	84	static CPUReadMemoryFunc *dma_dummy_read[3] = {
	85	NULL,
	86	NULL,
	87	NULL,
	88	};
	89
	90	static CPUWriteMemoryFunc *dma_dummy_write[3] = {
	91	dma_dummy_writeb,
	92	dma_dummy_writeb,
	93	dma_dummy_writeb,
	94	};
	95
4ce7ff6e AJ	96	#ifdef HAS_AUDIO
	97	static void audio_init(qemu_irq *pic)
	98	{
	99	struct soundhw *c;
	100	int audio_enabled = 0;
	101
	102	for (c = soundhw; !audio_enabled && c->name; ++c) {
	103	audio_enabled = c->enabled;
	104	}
	105
	106	if (audio_enabled) {
	107	AudioState *s;
	108
	109	s = AUD_init();
0d9acba8 PB	110	for (c = soundhw; c->name; ++c) {
	111	if (c->enabled) {
	112	if (c->isa) {
	113	c->init.init_isa(s, pic);
4ce7ff6e AJ	114	}
	115	}
	116	}
	117	}
	118	}
	119	#endif
	120
4ce7ff6e AJ	121	#define MAGNUM_BIOS_SIZE_MAX 0x7e000
	122	#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
	123
	124	static
00f82b8a	125	void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size,
3023f332	126	const char *cpu_model,
4ce7ff6e AJ	127	enum jazz_model_e jazz_model)
	128	{
	129	char buf[1024];
4ce7ff6e AJ	130	int bios_size, n;
	131	CPUState *env;
	132	qemu_irq rc4030, i8259;
c6945b15	133	rc4030_dma *dmas;
68238a9e	134	void* rc4030_opaque;
4ce7ff6e AJ	135	void *scsi_hba;
4ce7ff6e AJ	136	int hd;
c6945b15	137	int s_rtc, s_dma_dummy;
a65f56ee	138	NICInfo *nd;
4ce7ff6e AJ	139	PITState *pit;
	140	BlockDriverState *fds[MAX_FD];
	141	qemu_irq esp_reset;
dcac9679 PB	142	ram_addr_t ram_offset;
dcac9679 PB	143	ram_addr_t bios_offset;
4ce7ff6e AJ	144
	145	/* init CPUs */
	146	if (cpu_model == NULL) {
	147	#ifdef TARGET_MIPS64
	148	cpu_model = "R4000";
	149	#else
	150	/* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
	151	cpu_model = "24Kf";
	152	#endif
	153	}
	154	env = cpu_init(cpu_model);
	155	if (!env) {
	156	fprintf(stderr, "Unable to find CPU definition\n");
	157	exit(1);
	158	}
4ce7ff6e AJ	159	qemu_register_reset(main_cpu_reset, env);
	160
	161	/* allocate RAM */
dcac9679 PB	162	ram_offset = qemu_ram_alloc(ram_size);
	163	cpu_register_physical_memory(0, ram_size, ram_offset \| IO_MEM_RAM);
	164
dcac9679 PB	165	bios_offset = qemu_ram_alloc(MAGNUM_BIOS_SIZE);
	166	cpu_register_physical_memory(0x1fc00000LL,
	167	MAGNUM_BIOS_SIZE, bios_offset \| IO_MEM_ROM);
	168	cpu_register_physical_memory(0xfff00000LL,
	169	MAGNUM_BIOS_SIZE, bios_offset \| IO_MEM_ROM);
4ce7ff6e AJ	170
4ce7ff6e AJ	171	/* load the BIOS image. */
c6945b15 AJ	172	if (bios_name == NULL)
	173	bios_name = BIOS_FILENAME;
	174	snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
dcac9679	175	bios_size = load_image_targphys(buf, 0xfff00000LL, MAGNUM_BIOS_SIZE);
4ce7ff6e AJ	176	if (bios_size < 0 \|\| bios_size > MAGNUM_BIOS_SIZE) {
	177	fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
	178	buf);
	179	exit(1);
	180	}
	181
4ce7ff6e AJ	182	/* Init CPU internal devices */
	183	cpu_mips_irq_init_cpu(env);
	184	cpu_mips_clock_init(env);
	185
	186	/* Chipset */
68238a9e	187	rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas);
c6945b15 AJ	188	s_dma_dummy = cpu_register_io_memory(0, dma_dummy_read, dma_dummy_write, NULL);
c6945b15 AJ	189	cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy);
4ce7ff6e AJ	190
	191	/* ISA devices */
	192	i8259 = i8259_init(env->irq[4]);
c6945b15	193	DMA_init(0);
4ce7ff6e AJ	194	pit = pit_init(0x40, i8259[0]);
	195	pcspk_init(pit);
	196
	197	/* ISA IO space at 0x90000000 */
	198	isa_mmio_init(0x90000000, 0x01000000);
	199	isa_mem_base = 0x11000000;
	200
	201	/* Video card */
	202	switch (jazz_model) {
	203	case JAZZ_MAGNUM:
b584726d	204	g364fb_mm_init(vga_ram_size, 0x40000000, 0x60000000, 0, rc4030[3]);
4ce7ff6e	205	break;
c171148c	206	case JAZZ_PICA61:
b584726d	207	isa_vga_mm_init(vga_ram_size, 0x40000000, 0x60000000, 0);
c171148c	208	break;
4ce7ff6e AJ	209	default:
	210	break;
	211	}
	212
	213	/* Network controller */
a65f56ee AJ	214	for (n = 0; n < nb_nics; n++) {
	215	nd = &nd_table[n];
	216	if (!nd->model)
	217	nd->model = "dp83932";
	218	if (strcmp(nd->model, "dp83932") == 0) {
	219	dp83932_init(nd, 0x80001000, 2, rc4030[4],
	220	rc4030_opaque, rc4030_dma_memory_rw);
	221	break;
	222	} else if (strcmp(nd->model, "?") == 0) {
	223	fprintf(stderr, "qemu: Supported NICs: dp83932\n");
	224	exit(1);
	225	} else {
	226	fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
	227	exit(1);
	228	}
	229	}
4ce7ff6e AJ	230
4ce7ff6e AJ	231	/* SCSI adapter */
5d20fa6b	232	scsi_hba = esp_init(0x80002000, 0,
68238a9e	233	rc4030_dma_read, rc4030_dma_write, dmas[0],
4ce7ff6e AJ	234	rc4030[5], &esp_reset);
	235	for (n = 0; n < ESP_MAX_DEVS; n++) {
	236	hd = drive_get_index(IF_SCSI, 0, n);
	237	if (hd != -1) {
	238	esp_scsi_attach(scsi_hba, drives_table[hd].bdrv, n);
	239	}
	240	}
	241
	242	/* Floppy */
	243	if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
	244	fprintf(stderr, "qemu: too many floppy drives\n");
	245	exit(1);
	246	}
	247	for (n = 0; n < MAX_FD; n++) {
	248	int fd = drive_get_index(IF_FLOPPY, 0, n);
	249	if (fd != -1)
	250	fds[n] = drives_table[fd].bdrv;
	251	else
	252	fds[n] = NULL;
	253	}
	254	fdctrl_init(rc4030[1], 0, 1, 0x80003000, fds);
	255
	256	/* Real time clock */
42fc73a1	257	rtc_init(0x70, i8259[8], 1980);
4ce7ff6e AJ	258	s_rtc = cpu_register_io_memory(0, rtc_read, rtc_write, env);
	259	cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc);
	260
	261	/* Keyboard (i8042) */
4efbe58f	262	i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1);
4ce7ff6e AJ	263
	264	/* Serial ports */
	265	if (serial_hds[0])
b6cd0ea1	266	serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1);
4ce7ff6e	267	if (serial_hds[1])
b6cd0ea1	268	serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1);
4ce7ff6e AJ	269
	270	/* Parallel port */
	271	if (parallel_hds[0])
	272	parallel_mm_init(0x80008000, 0, rc4030[0], parallel_hds[0]);
	273
	274	/* Sound card */
	275	/* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
	276	#ifdef HAS_AUDIO
	277	audio_init(i8259);
	278	#endif
	279
	280	/* NVRAM: Unprotected at 0x9000, Protected at 0xa000, Read only at 0xb000 */
	281	ds1225y_init(0x80009000, "nvram");
	282
	283	/* LED indicator */
3023f332	284	jazz_led_init(0x8000f000);
4ce7ff6e AJ	285	}
	286
	287	static
00f82b8a	288	void mips_magnum_init (ram_addr_t ram_size, int vga_ram_size,
3023f332	289	const char *boot_device,
4ce7ff6e AJ	290	const char kernel_filename, const char kernel_cmdline,
	291	const char initrd_filename, const char cpu_model)
	292	{
3023f332	293	mips_jazz_init(ram_size, vga_ram_size, cpu_model, JAZZ_MAGNUM);
4ce7ff6e AJ	294	}
4ce7ff6e AJ	295
c171148c	296	static
00f82b8a	297	void mips_pica61_init (ram_addr_t ram_size, int vga_ram_size,
3023f332	298	const char *boot_device,
c171148c AJ	299	const char kernel_filename, const char kernel_cmdline,
	300	const char initrd_filename, const char cpu_model)
	301	{
3023f332	302	mips_jazz_init(ram_size, vga_ram_size, cpu_model, JAZZ_PICA61);
c171148c AJ	303	}
c171148c AJ	304
4ce7ff6e	305	QEMUMachine mips_magnum_machine = {
eec2743e TS	306	.name = "magnum",
	307	.desc = "MIPS Magnum",
	308	.init = mips_magnum_init,
c6945b15	309	.use_scsi = 1,
4ce7ff6e	310	};
c171148c AJ	311
c171148c AJ	312	QEMUMachine mips_pica61_machine = {
eec2743e TS	313	.name = "pica61",
	314	.desc = "Acer Pica 61",
	315	.init = mips_pica61_init,
c6945b15	316	.use_scsi = 1,
c171148c	317	};