[qemu.git] / hw / i8259.c

/*
 * QEMU 8259 interrupt controller emulation
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "pc.h"
#include "isa.h"
#include "monitor.h"
#include "qemu-timer.h"

/* debug PIC */
//#define DEBUG_PIC

#ifdef DEBUG_PIC
#define DPRINTF(fmt, ...)                                       \
    do { printf("pic: " fmt , ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...)
#endif

//#define DEBUG_IRQ_LATENCY
//#define DEBUG_IRQ_COUNT

typedef struct PicState {
    uint8_t last_irr; /* edge detection */
    uint8_t irr; /* interrupt request register */
    uint8_t imr; /* interrupt mask register */
    uint8_t isr; /* interrupt service register */
    uint8_t priority_add; /* highest irq priority */
    uint8_t irq_base;
    uint8_t read_reg_select;
    uint8_t poll;
    uint8_t special_mask;
    uint8_t init_state;
    uint8_t auto_eoi;
    uint8_t rotate_on_auto_eoi;
    uint8_t special_fully_nested_mode;
    uint8_t init4; /* true if 4 byte init */
    uint8_t single_mode; /* true if slave pic is not initialized */
    uint8_t elcr; /* PIIX edge/trigger selection*/
    uint8_t elcr_mask;
    PicState2 *pics_state;
    MemoryRegion base_io;
    MemoryRegion elcr_io;
} PicState;

struct PicState2 {
    /* 0 is master pic, 1 is slave pic */
    /* XXX: better separation between the two pics */
    PicState pics[2];
    qemu_irq parent_irq;
    void *irq_request_opaque;
};

#if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
static int irq_level[16];
#endif
#ifdef DEBUG_IRQ_COUNT
static uint64_t irq_count[16];
#endif
PicState2 *isa_pic;

/* set irq level. If an edge is detected, then the IRR is set to 1 */
static inline void pic_set_irq1(PicState *s, int irq, int level)
{
    int mask;
    mask = 1 << irq;
    if (s->elcr & mask) {
        /* level triggered */
        if (level) {
            s->irr |= mask;
            s->last_irr |= mask;
        } else {
            s->irr &= ~mask;
            s->last_irr &= ~mask;
        }
    } else {
        /* edge triggered */
        if (level) {
            if ((s->last_irr & mask) == 0)
                s->irr |= mask;
            s->last_irr |= mask;
        } else {
            s->last_irr &= ~mask;
        }
    }
}

/* return the highest priority found in mask (highest = smallest
   number). Return 8 if no irq */
static inline int get_priority(PicState *s, int mask)
{
    int priority;
    if (mask == 0)
        return 8;
    priority = 0;
    while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
        priority++;
    return priority;
}

/* return the pic wanted interrupt. return -1 if none */
static int pic_get_irq(PicState *s)
{
    int mask, cur_priority, priority;

    mask = s->irr & ~s->imr;
    priority = get_priority(s, mask);
    if (priority == 8)
        return -1;
    /* compute current priority. If special fully nested mode on the
       master, the IRQ coming from the slave is not taken into account
       for the priority computation. */
    mask = s->isr;
    if (s->special_mask)
        mask &= ~s->imr;
    if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
        mask &= ~(1 << 2);
    cur_priority = get_priority(s, mask);
    if (priority < cur_priority) {
        /* higher priority found: an irq should be generated */
        return (priority + s->priority_add) & 7;
    } else {
        return -1;
    }
}

/* raise irq to CPU if necessary. must be called every time the active
   irq may change */
/* XXX: should not export it, but it is needed for an APIC kludge */
void pic_update_irq(PicState2 *s)
{
    int irq2, irq;

    /* first look at slave pic */
    irq2 = pic_get_irq(&s->pics[1]);
    if (irq2 >= 0) {
        /* if irq request by slave pic, signal master PIC */
        pic_set_irq1(&s->pics[0], 2, 1);
        pic_set_irq1(&s->pics[0], 2, 0);
    }
    /* look at requested irq */
    irq = pic_get_irq(&s->pics[0]);
    if (irq >= 0) {
#if defined(DEBUG_PIC)
        {
            int i;
            for(i = 0; i < 2; i++) {
                printf("pic%d: imr=%x irr=%x padd=%d\n",
                       i, s->pics[i].imr, s->pics[i].irr,
                       s->pics[i].priority_add);

            }
        }
        printf("pic: cpu_interrupt\n");
#endif
        qemu_irq_raise(s->parent_irq);
    }

/* all targets should do this rather than acking the IRQ in the cpu */
#if defined(TARGET_MIPS) || defined(TARGET_PPC) || defined(TARGET_ALPHA)
    else {
        qemu_irq_lower(s->parent_irq);
    }
#endif
}

#ifdef DEBUG_IRQ_LATENCY
int64_t irq_time[16];
#endif

static void i8259_set_irq(void *opaque, int irq, int level)
{
    PicState2 *s = opaque;

#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
    if (level != irq_level[irq]) {
        DPRINTF("i8259_set_irq: irq=%d level=%d\n", irq, level);
        irq_level[irq] = level;
#ifdef DEBUG_IRQ_COUNT
	if (level == 1)
	    irq_count[irq]++;
#endif
    }
#endif
#ifdef DEBUG_IRQ_LATENCY
    if (level) {
        irq_time[irq] = qemu_get_clock_ns(vm_clock);
    }
#endif
    pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
    pic_update_irq(s);
}

/* acknowledge interrupt 'irq' */
static inline void pic_intack(PicState *s, int irq)
{
    if (s->auto_eoi) {
        if (s->rotate_on_auto_eoi)
            s->priority_add = (irq + 1) & 7;
    } else {
        s->isr |= (1 << irq);
    }
    /* We don't clear a level sensitive interrupt here */
    if (!(s->elcr & (1 << irq)))
        s->irr &= ~(1 << irq);
}

int pic_read_irq(PicState2 *s)
{
    int irq, irq2, intno;

    irq = pic_get_irq(&s->pics[0]);
    if (irq >= 0) {
        pic_intack(&s->pics[0], irq);
        if (irq == 2) {
            irq2 = pic_get_irq(&s->pics[1]);
            if (irq2 >= 0) {
                pic_intack(&s->pics[1], irq2);
            } else {
                /* spurious IRQ on slave controller */
                irq2 = 7;
            }
            intno = s->pics[1].irq_base + irq2;
#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_LATENCY)
            irq = irq2 + 8;
#endif
        } else {
            intno = s->pics[0].irq_base + irq;
        }
    } else {
        /* spurious IRQ on host controller */
        irq = 7;
        intno = s->pics[0].irq_base + irq;
    }
    pic_update_irq(s);

#ifdef DEBUG_IRQ_LATENCY
    printf("IRQ%d latency=%0.3fus\n",
           irq,
           (double)(qemu_get_clock_ns(vm_clock) -
                    irq_time[irq]) * 1000000.0 / get_ticks_per_sec());
#endif
    DPRINTF("pic_interrupt: irq=%d\n", irq);
    return intno;
}

static void pic_reset(void *opaque)
{
    PicState *s = opaque;

    s->last_irr = 0;
    s->irr = 0;
    s->imr = 0;
    s->isr = 0;
    s->priority_add = 0;
    s->irq_base = 0;
    s->read_reg_select = 0;
    s->poll = 0;
    s->special_mask = 0;
    s->init_state = 0;
    s->auto_eoi = 0;
    s->rotate_on_auto_eoi = 0;
    s->special_fully_nested_mode = 0;
    s->init4 = 0;
    s->single_mode = 0;
    /* Note: ELCR is not reset */
}

static void pic_ioport_write(void *opaque, target_phys_addr_t addr64,
                             uint64_t val64, unsigned size)
{
    PicState *s = opaque;
    uint32_t addr = addr64;
    uint32_t val = val64;
    int priority, cmd, irq;

    DPRINTF("write: addr=0x%02x val=0x%02x\n", addr, val);
    if (addr == 0) {
        if (val & 0x10) {
            /* init */
            pic_reset(s);
            /* deassert a pending interrupt */
            qemu_irq_lower(s->pics_state->parent_irq);
            s->init_state = 1;
            s->init4 = val & 1;
            s->single_mode = val & 2;
            if (val & 0x08)
                hw_error("level sensitive irq not supported");
        } else if (val & 0x08) {
            if (val & 0x04)
                s->poll = 1;
            if (val & 0x02)
                s->read_reg_select = val & 1;
            if (val & 0x40)
                s->special_mask = (val >> 5) & 1;
        } else {
            cmd = val >> 5;
            switch(cmd) {
            case 0:
            case 4:
                s->rotate_on_auto_eoi = cmd >> 2;
                break;
            case 1: /* end of interrupt */
            case 5:
                priority = get_priority(s, s->isr);
                if (priority != 8) {
                    irq = (priority + s->priority_add) & 7;
                    s->isr &= ~(1 << irq);
                    if (cmd == 5)
                        s->priority_add = (irq + 1) & 7;
                    pic_update_irq(s->pics_state);
                }
                break;
            case 3:
                irq = val & 7;
                s->isr &= ~(1 << irq);
                pic_update_irq(s->pics_state);
                break;
            case 6:
                s->priority_add = (val + 1) & 7;
                pic_update_irq(s->pics_state);
                break;
            case 7:
                irq = val & 7;
                s->isr &= ~(1 << irq);
                s->priority_add = (irq + 1) & 7;
                pic_update_irq(s->pics_state);
                break;
            default:
                /* no operation */
                break;
            }
        }
    } else {
        switch(s->init_state) {
        case 0:
            /* normal mode */
            s->imr = val;
            pic_update_irq(s->pics_state);
            break;
        case 1:
            s->irq_base = val & 0xf8;
            s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2;
            break;
        case 2:
            if (s->init4) {
                s->init_state = 3;
            } else {
                s->init_state = 0;
            }
            break;
        case 3:
            s->special_fully_nested_mode = (val >> 4) & 1;
            s->auto_eoi = (val >> 1) & 1;
            s->init_state = 0;
            break;
        }
    }
}

static uint32_t pic_poll_read(PicState *s)
{
    int ret;

    ret = pic_get_irq(s);
    if (ret >= 0) {
        bool slave = (s == &isa_pic->pics[1]);

        if (slave) {
            s->pics_state->pics[0].isr &= ~(1 << 2);
            s->pics_state->pics[0].irr &= ~(1 << 2);
        }
        s->irr &= ~(1 << ret);
        s->isr &= ~(1 << ret);
        if (slave || ret != 2)
            pic_update_irq(s->pics_state);
    } else {
        ret = 0x07;
        pic_update_irq(s->pics_state);
    }

    return ret;
}

static uint64_t pic_ioport_read(void *opaque, target_phys_addr_t addr1,
                                unsigned size)
{
    PicState *s = opaque;
    unsigned int addr = addr1;
    int ret;

    if (s->poll) {
        ret = pic_poll_read(s);
        s->poll = 0;
    } else {
        if (addr == 0) {
            if (s->read_reg_select)
                ret = s->isr;
            else
                ret = s->irr;
        } else {
            ret = s->imr;
        }
    }
    DPRINTF("read: addr=0x%02x val=0x%02x\n", addr, ret);
    return ret;
}

/* memory mapped interrupt status */
/* XXX: may be the same than pic_read_irq() */
uint32_t pic_intack_read(PicState2 *s)
{
    int ret;

    ret = pic_poll_read(&s->pics[0]);
    if (ret == 2)
        ret = pic_poll_read(&s->pics[1]) + 8;
    /* Prepare for ISR read */
    s->pics[0].read_reg_select = 1;

    return ret;
}

static void elcr_ioport_write(void *opaque, target_phys_addr_t addr,
                              uint64_t val, unsigned size)
{
    PicState *s = opaque;
    s->elcr = val & s->elcr_mask;
}

static uint64_t elcr_ioport_read(void *opaque, target_phys_addr_t addr,
                                 unsigned size)
{
    PicState *s = opaque;
    return s->elcr;
}

static const VMStateDescription vmstate_pic = {
    .name = "i8259",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_UINT8(last_irr, PicState),
        VMSTATE_UINT8(irr, PicState),
        VMSTATE_UINT8(imr, PicState),
        VMSTATE_UINT8(isr, PicState),
        VMSTATE_UINT8(priority_add, PicState),
        VMSTATE_UINT8(irq_base, PicState),
        VMSTATE_UINT8(read_reg_select, PicState),
        VMSTATE_UINT8(poll, PicState),
        VMSTATE_UINT8(special_mask, PicState),
        VMSTATE_UINT8(init_state, PicState),
        VMSTATE_UINT8(auto_eoi, PicState),
        VMSTATE_UINT8(rotate_on_auto_eoi, PicState),
        VMSTATE_UINT8(special_fully_nested_mode, PicState),
        VMSTATE_UINT8(init4, PicState),
        VMSTATE_UINT8(single_mode, PicState),
        VMSTATE_UINT8(elcr, PicState),
        VMSTATE_END_OF_LIST()
    }
};

static const MemoryRegionOps pic_base_ioport_ops = {
    .read = pic_ioport_read,
    .write = pic_ioport_write,
    .impl = {
        .min_access_size = 1,
        .max_access_size = 1,
    },
};

static const MemoryRegionOps pic_elcr_ioport_ops = {
    .read = elcr_ioport_read,
    .write = elcr_ioport_write,
    .impl = {
        .min_access_size = 1,
        .max_access_size = 1,
    },
};

/* XXX: add generic master/slave system */
static void pic_init1(int io_addr, int elcr_addr, PicState *s)
{
    memory_region_init_io(&s->base_io, &pic_base_ioport_ops, s, "pic", 2);
    memory_region_init_io(&s->elcr_io, &pic_elcr_ioport_ops, s, "elcr", 1);

    isa_register_ioport(NULL, &s->base_io, io_addr);
    if (elcr_addr >= 0) {
        isa_register_ioport(NULL, &s->elcr_io, elcr_addr);
    }

    vmstate_register(NULL, io_addr, &vmstate_pic, s);
    qemu_register_reset(pic_reset, s);
}

void pic_info(Monitor *mon)
{
    int i;
    PicState *s;

    if (!isa_pic)
        return;

    for(i=0;i<2;i++) {
        s = &isa_pic->pics[i];
        monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
                       "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
                       i, s->irr, s->imr, s->isr, s->priority_add,
                       s->irq_base, s->read_reg_select, s->elcr,
                       s->special_fully_nested_mode);
    }
}

void irq_info(Monitor *mon)
{
#ifndef DEBUG_IRQ_COUNT
    monitor_printf(mon, "irq statistic code not compiled.\n");
#else
    int i;
    int64_t count;

    monitor_printf(mon, "IRQ statistics:\n");
    for (i = 0; i < 16; i++) {
        count = irq_count[i];
        if (count > 0)
            monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
    }
#endif
}

qemu_irq *i8259_init(qemu_irq parent_irq)
{
    PicState2 *s;

    s = g_malloc0(sizeof(PicState2));
    pic_init1(0x20, 0x4d0, &s->pics[0]);
    pic_init1(0xa0, 0x4d1, &s->pics[1]);
    s->pics[0].elcr_mask = 0xf8;
    s->pics[1].elcr_mask = 0xde;
    s->parent_irq = parent_irq;
    s->pics[0].pics_state = s;
    s->pics[1].pics_state = s;
    isa_pic = s;
    return qemu_allocate_irqs(i8259_set_irq, s, 16);
}
Commit	Line	Data
80cabfad FB	1	/*
80cabfad FB	2	* QEMU 8259 interrupt controller emulation
5fafdf24	3	*
80cabfad	4	* Copyright (c) 2003-2004 Fabrice Bellard
5fafdf24	5	*
80cabfad FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
	25	#include "pc.h"
	26	#include "isa.h"
376253ec	27	#include "monitor.h"
0bf9e31a	28	#include "qemu-timer.h"
80cabfad FB	29
	30	/* debug PIC */
	31	//#define DEBUG_PIC
	32
8ac02ff8 BS	33	#ifdef DEBUG_PIC
	34	#define DPRINTF(fmt, ...) \
	35	do { printf("pic: " fmt , ## __VA_ARGS__); } while (0)
	36	#else
	37	#define DPRINTF(fmt, ...)
	38	#endif
	39
b41a2cd1	40	//#define DEBUG_IRQ_LATENCY
4a0fb71e	41	//#define DEBUG_IRQ_COUNT
b41a2cd1	42
80cabfad FB	43	typedef struct PicState {
	44	uint8_t last_irr; /* edge detection */
	45	uint8_t irr; /* interrupt request register */
	46	uint8_t imr; /* interrupt mask register */
	47	uint8_t isr; /* interrupt service register */
	48	uint8_t priority_add; /* highest irq priority */
	49	uint8_t irq_base;
	50	uint8_t read_reg_select;
	51	uint8_t poll;
	52	uint8_t special_mask;
	53	uint8_t init_state;
	54	uint8_t auto_eoi;
	55	uint8_t rotate_on_auto_eoi;
	56	uint8_t special_fully_nested_mode;
	57	uint8_t init4; /* true if 4 byte init */
2053152b	58	uint8_t single_mode; /* true if slave pic is not initialized */
660de336 FB	59	uint8_t elcr; /* PIIX edge/trigger selection*/
660de336 FB	60	uint8_t elcr_mask;
3de388f6	61	PicState2 *pics_state;
098d314a RH	62	MemoryRegion base_io;
098d314a RH	63	MemoryRegion elcr_io;
80cabfad FB	64	} PicState;
80cabfad FB	65
3de388f6 FB	66	struct PicState2 {
	67	/* 0 is master pic, 1 is slave pic */
	68	/* XXX: better separation between the two pics */
	69	PicState pics[2];
d537cf6c	70	qemu_irq parent_irq;
3de388f6 FB	71	void *irq_request_opaque;
3de388f6 FB	72	};
80cabfad	73
4a0fb71e FB	74	#if defined(DEBUG_PIC) \|\| defined (DEBUG_IRQ_COUNT)
	75	static int irq_level[16];
	76	#endif
	77	#ifdef DEBUG_IRQ_COUNT
	78	static uint64_t irq_count[16];
	79	#endif
fbe3288d	80	PicState2 *isa_pic;
4a0fb71e	81
80cabfad FB	82	/* set irq level. If an edge is detected, then the IRR is set to 1 */
	83	static inline void pic_set_irq1(PicState *s, int irq, int level)
	84	{
	85	int mask;
	86	mask = 1 << irq;
660de336 FB	87	if (s->elcr & mask) {
	88	/* level triggered */
	89	if (level) {
80cabfad	90	s->irr \|= mask;
660de336 FB	91	s->last_irr \|= mask;
	92	} else {
	93	s->irr &= ~mask;
	94	s->last_irr &= ~mask;
	95	}
80cabfad	96	} else {
660de336 FB	97	/* edge triggered */
	98	if (level) {
	99	if ((s->last_irr & mask) == 0)
	100	s->irr \|= mask;
	101	s->last_irr \|= mask;
	102	} else {
	103	s->last_irr &= ~mask;
	104	}
80cabfad FB	105	}
	106	}
	107
	108	/* return the highest priority found in mask (highest = smallest
	109	number). Return 8 if no irq */
	110	static inline int get_priority(PicState *s, int mask)
	111	{
	112	int priority;
	113	if (mask == 0)
	114	return 8;
	115	priority = 0;
	116	while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
	117	priority++;
	118	return priority;
	119	}
	120
	121	/* return the pic wanted interrupt. return -1 if none */
	122	static int pic_get_irq(PicState *s)
	123	{
	124	int mask, cur_priority, priority;
	125
	126	mask = s->irr & ~s->imr;
	127	priority = get_priority(s, mask);
	128	if (priority == 8)
	129	return -1;
	130	/* compute current priority. If special fully nested mode on the
	131	master, the IRQ coming from the slave is not taken into account
	132	for the priority computation. */
	133	mask = s->isr;
84678711 AZ	134	if (s->special_mask)
84678711 AZ	135	mask &= ~s->imr;
3de388f6	136	if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
80cabfad FB	137	mask &= ~(1 << 2);
	138	cur_priority = get_priority(s, mask);
	139	if (priority < cur_priority) {
	140	/* higher priority found: an irq should be generated */
	141	return (priority + s->priority_add) & 7;
	142	} else {
	143	return -1;
	144	}
	145	}
	146
	147	/* raise irq to CPU if necessary. must be called every time the active
	148	irq may change */
3de388f6 FB	149	/* XXX: should not export it, but it is needed for an APIC kludge */
3de388f6 FB	150	void pic_update_irq(PicState2 *s)
80cabfad FB	151	{
	152	int irq2, irq;
	153
	154	/* first look at slave pic */
3de388f6	155	irq2 = pic_get_irq(&s->pics[1]);
80cabfad FB	156	if (irq2 >= 0) {
80cabfad FB	157	/* if irq request by slave pic, signal master PIC */
3de388f6 FB	158	pic_set_irq1(&s->pics[0], 2, 1);
3de388f6 FB	159	pic_set_irq1(&s->pics[0], 2, 0);
80cabfad FB	160	}
80cabfad FB	161	/* look at requested irq */
3de388f6	162	irq = pic_get_irq(&s->pics[0]);
80cabfad	163	if (irq >= 0) {
80cabfad FB	164	#if defined(DEBUG_PIC)
	165	{
	166	int i;
	167	for(i = 0; i < 2; i++) {
5fafdf24 TS	168	printf("pic%d: imr=%x irr=%x padd=%d\n",
5fafdf24 TS	169	i, s->pics[i].imr, s->pics[i].irr,
3de388f6	170	s->pics[i].priority_add);
3b46e624	171
80cabfad FB	172	}
80cabfad FB	173	}
2444ca41	174	printf("pic: cpu_interrupt\n");
80cabfad	175	#endif
d537cf6c	176	qemu_irq_raise(s->parent_irq);
80cabfad	177	}
4de9b249 TS	178
4de9b249 TS	179	/* all targets should do this rather than acking the IRQ in the cpu */
29463b24	180	#if defined(TARGET_MIPS) \|\| defined(TARGET_PPC) \|\| defined(TARGET_ALPHA)
4de9b249	181	else {
d537cf6c	182	qemu_irq_lower(s->parent_irq);
4de9b249 TS	183	}
4de9b249 TS	184	#endif
80cabfad FB	185	}
	186
	187	#ifdef DEBUG_IRQ_LATENCY
	188	int64_t irq_time[16];
80cabfad	189	#endif
80cabfad	190
9596ebb7	191	static void i8259_set_irq(void *opaque, int irq, int level)
80cabfad	192	{
3de388f6 FB	193	PicState2 *s = opaque;
3de388f6 FB	194
4a0fb71e	195	#if defined(DEBUG_PIC) \|\| defined(DEBUG_IRQ_COUNT)
80cabfad	196	if (level != irq_level[irq]) {
8ac02ff8	197	DPRINTF("i8259_set_irq: irq=%d level=%d\n", irq, level);
80cabfad	198	irq_level[irq] = level;
4a0fb71e FB	199	#ifdef DEBUG_IRQ_COUNT
	200	if (level == 1)
	201	irq_count[irq]++;
	202	#endif
80cabfad FB	203	}
	204	#endif
	205	#ifdef DEBUG_IRQ_LATENCY
	206	if (level) {
74475455	207	irq_time[irq] = qemu_get_clock_ns(vm_clock);
80cabfad FB	208	}
80cabfad FB	209	#endif
3de388f6 FB	210	pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
3de388f6 FB	211	pic_update_irq(s);
80cabfad FB	212	}
	213
	214	/* acknowledge interrupt 'irq' */
	215	static inline void pic_intack(PicState *s, int irq)
	216	{
	217	if (s->auto_eoi) {
	218	if (s->rotate_on_auto_eoi)
	219	s->priority_add = (irq + 1) & 7;
	220	} else {
	221	s->isr \|= (1 << irq);
	222	}
0ecf89aa FB	223	/* We don't clear a level sensitive interrupt here */
	224	if (!(s->elcr & (1 << irq)))
	225	s->irr &= ~(1 << irq);
80cabfad FB	226	}
80cabfad FB	227
3de388f6	228	int pic_read_irq(PicState2 *s)
80cabfad FB	229	{
	230	int irq, irq2, intno;
	231
3de388f6	232	irq = pic_get_irq(&s->pics[0]);
15aeac38	233	if (irq >= 0) {
3de388f6	234	pic_intack(&s->pics[0], irq);
15aeac38	235	if (irq == 2) {
3de388f6	236	irq2 = pic_get_irq(&s->pics[1]);
15aeac38	237	if (irq2 >= 0) {
3de388f6	238	pic_intack(&s->pics[1], irq2);
15aeac38 FB	239	} else {
	240	/* spurious IRQ on slave controller */
	241	irq2 = 7;
	242	}
3de388f6	243	intno = s->pics[1].irq_base + irq2;
7f5b7d3e	244	#if defined(DEBUG_PIC) \|\| defined(DEBUG_IRQ_LATENCY)
15aeac38	245	irq = irq2 + 8;
7f5b7d3e	246	#endif
15aeac38	247	} else {
3de388f6	248	intno = s->pics[0].irq_base + irq;
15aeac38 FB	249	}
	250	} else {
	251	/* spurious IRQ on host controller */
	252	irq = 7;
3de388f6	253	intno = s->pics[0].irq_base + irq;
15aeac38	254	}
3de388f6	255	pic_update_irq(s);
3b46e624	256
80cabfad	257	#ifdef DEBUG_IRQ_LATENCY
5fafdf24 TS	258	printf("IRQ%d latency=%0.3fus\n",
5fafdf24 TS	259	irq,
74475455	260	(double)(qemu_get_clock_ns(vm_clock) -
6ee093c9	261	irq_time[irq]) * 1000000.0 / get_ticks_per_sec());
80cabfad	262	#endif
8ac02ff8	263	DPRINTF("pic_interrupt: irq=%d\n", irq);
80cabfad FB	264	return intno;
	265	}
	266
d7d02e3c FB	267	static void pic_reset(void *opaque)
	268	{
	269	PicState *s = opaque;
d7d02e3c	270
3de388f6 FB	271	s->last_irr = 0;
	272	s->irr = 0;
	273	s->imr = 0;
	274	s->isr = 0;
	275	s->priority_add = 0;
	276	s->irq_base = 0;
	277	s->read_reg_select = 0;
	278	s->poll = 0;
	279	s->special_mask = 0;
	280	s->init_state = 0;
	281	s->auto_eoi = 0;
	282	s->rotate_on_auto_eoi = 0;
	283	s->special_fully_nested_mode = 0;
	284	s->init4 = 0;
2053152b	285	s->single_mode = 0;
4dbe19e1	286	/* Note: ELCR is not reset */
d7d02e3c FB	287	}
d7d02e3c FB	288
098d314a RH	289	static void pic_ioport_write(void *opaque, target_phys_addr_t addr64,
098d314a RH	290	uint64_t val64, unsigned size)
80cabfad	291	{
b41a2cd1	292	PicState *s = opaque;
098d314a RH	293	uint32_t addr = addr64;
098d314a RH	294	uint32_t val = val64;
d7d02e3c	295	int priority, cmd, irq;
80cabfad	296
8ac02ff8	297	DPRINTF("write: addr=0x%02x val=0x%02x\n", addr, val);
80cabfad FB	298	if (addr == 0) {
	299	if (val & 0x10) {
	300	/* init */
d7d02e3c	301	pic_reset(s);
b54ad049	302	/* deassert a pending interrupt */
d537cf6c	303	qemu_irq_lower(s->pics_state->parent_irq);
80cabfad FB	304	s->init_state = 1;
80cabfad FB	305	s->init4 = val & 1;
2053152b	306	s->single_mode = val & 2;
80cabfad FB	307	if (val & 0x08)
	308	hw_error("level sensitive irq not supported");
	309	} else if (val & 0x08) {
	310	if (val & 0x04)
	311	s->poll = 1;
	312	if (val & 0x02)
	313	s->read_reg_select = val & 1;
	314	if (val & 0x40)
	315	s->special_mask = (val >> 5) & 1;
	316	} else {
	317	cmd = val >> 5;
	318	switch(cmd) {
	319	case 0:
	320	case 4:
	321	s->rotate_on_auto_eoi = cmd >> 2;
	322	break;
	323	case 1: /* end of interrupt */
	324	case 5:
	325	priority = get_priority(s, s->isr);
	326	if (priority != 8) {
	327	irq = (priority + s->priority_add) & 7;
	328	s->isr &= ~(1 << irq);
	329	if (cmd == 5)
	330	s->priority_add = (irq + 1) & 7;
3de388f6	331	pic_update_irq(s->pics_state);
80cabfad FB	332	}
	333	break;
	334	case 3:
	335	irq = val & 7;
	336	s->isr &= ~(1 << irq);
3de388f6	337	pic_update_irq(s->pics_state);
80cabfad FB	338	break;
	339	case 6:
	340	s->priority_add = (val + 1) & 7;
3de388f6	341	pic_update_irq(s->pics_state);
80cabfad FB	342	break;
	343	case 7:
	344	irq = val & 7;
	345	s->isr &= ~(1 << irq);
	346	s->priority_add = (irq + 1) & 7;
3de388f6	347	pic_update_irq(s->pics_state);
80cabfad FB	348	break;
	349	default:
	350	/* no operation */
	351	break;
	352	}
	353	}
	354	} else {
	355	switch(s->init_state) {
	356	case 0:
	357	/* normal mode */
	358	s->imr = val;
3de388f6	359	pic_update_irq(s->pics_state);
80cabfad FB	360	break;
	361	case 1:
	362	s->irq_base = val & 0xf8;
2bb081f7	363	s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2;
80cabfad FB	364	break;
	365	case 2:
	366	if (s->init4) {
	367	s->init_state = 3;
	368	} else {
	369	s->init_state = 0;
	370	}
	371	break;
	372	case 3:
	373	s->special_fully_nested_mode = (val >> 4) & 1;
	374	s->auto_eoi = (val >> 1) & 1;
	375	s->init_state = 0;
	376	break;
	377	}
	378	}
	379	}
	380
098d314a	381	static uint32_t pic_poll_read(PicState *s)
80cabfad FB	382	{
	383	int ret;
	384
	385	ret = pic_get_irq(s);
	386	if (ret >= 0) {
098d314a RH	387	bool slave = (s == &isa_pic->pics[1]);
	388
	389	if (slave) {
3de388f6 FB	390	s->pics_state->pics[0].isr &= ~(1 << 2);
3de388f6 FB	391	s->pics_state->pics[0].irr &= ~(1 << 2);
80cabfad FB	392	}
	393	s->irr &= ~(1 << ret);
	394	s->isr &= ~(1 << ret);
098d314a	395	if (slave \|\| ret != 2)
3de388f6	396	pic_update_irq(s->pics_state);
80cabfad FB	397	} else {
80cabfad FB	398	ret = 0x07;
3de388f6	399	pic_update_irq(s->pics_state);
80cabfad FB	400	}
	401
	402	return ret;
	403	}
	404
098d314a RH	405	static uint64_t pic_ioport_read(void *opaque, target_phys_addr_t addr1,
098d314a RH	406	unsigned size)
80cabfad	407	{
b41a2cd1	408	PicState *s = opaque;
098d314a	409	unsigned int addr = addr1;
80cabfad FB	410	int ret;
80cabfad FB	411
80cabfad	412	if (s->poll) {
098d314a	413	ret = pic_poll_read(s);
80cabfad FB	414	s->poll = 0;
	415	} else {
	416	if (addr == 0) {
	417	if (s->read_reg_select)
	418	ret = s->isr;
	419	else
	420	ret = s->irr;
	421	} else {
	422	ret = s->imr;
	423	}
	424	}
098d314a	425	DPRINTF("read: addr=0x%02x val=0x%02x\n", addr, ret);
80cabfad FB	426	return ret;
	427	}
	428
	429	/* memory mapped interrupt status */
3de388f6 FB	430	/* XXX: may be the same than pic_read_irq() */
3de388f6 FB	431	uint32_t pic_intack_read(PicState2 *s)
80cabfad FB	432	{
	433	int ret;
	434
098d314a	435	ret = pic_poll_read(&s->pics[0]);
80cabfad	436	if (ret == 2)
098d314a	437	ret = pic_poll_read(&s->pics[1]) + 8;
80cabfad	438	/* Prepare for ISR read */
3de388f6	439	s->pics[0].read_reg_select = 1;
3b46e624	440
80cabfad FB	441	return ret;
	442	}
	443
098d314a RH	444	static void elcr_ioport_write(void *opaque, target_phys_addr_t addr,
098d314a RH	445	uint64_t val, unsigned size)
660de336 FB	446	{
	447	PicState *s = opaque;
	448	s->elcr = val & s->elcr_mask;
	449	}
	450
098d314a RH	451	static uint64_t elcr_ioport_read(void *opaque, target_phys_addr_t addr,
098d314a RH	452	unsigned size)
660de336 FB	453	{
	454	PicState *s = opaque;
	455	return s->elcr;
	456	}
	457
77eea838 JQ	458	static const VMStateDescription vmstate_pic = {
	459	.name = "i8259",
	460	.version_id = 1,
	461	.minimum_version_id = 1,
	462	.minimum_version_id_old = 1,
	463	.fields = (VMStateField []) {
	464	VMSTATE_UINT8(last_irr, PicState),
	465	VMSTATE_UINT8(irr, PicState),
	466	VMSTATE_UINT8(imr, PicState),
	467	VMSTATE_UINT8(isr, PicState),
	468	VMSTATE_UINT8(priority_add, PicState),
	469	VMSTATE_UINT8(irq_base, PicState),
	470	VMSTATE_UINT8(read_reg_select, PicState),
	471	VMSTATE_UINT8(poll, PicState),
	472	VMSTATE_UINT8(special_mask, PicState),
	473	VMSTATE_UINT8(init_state, PicState),
	474	VMSTATE_UINT8(auto_eoi, PicState),
	475	VMSTATE_UINT8(rotate_on_auto_eoi, PicState),
	476	VMSTATE_UINT8(special_fully_nested_mode, PicState),
	477	VMSTATE_UINT8(init4, PicState),
	478	VMSTATE_UINT8(single_mode, PicState),
	479	VMSTATE_UINT8(elcr, PicState),
	480	VMSTATE_END_OF_LIST()
	481	}
	482	};
b0a21b53	483
098d314a RH	484	static const MemoryRegionOps pic_base_ioport_ops = {
	485	.read = pic_ioport_read,
	486	.write = pic_ioport_write,
	487	.impl = {
	488	.min_access_size = 1,
	489	.max_access_size = 1,
	490	},
	491	};
	492
	493	static const MemoryRegionOps pic_elcr_ioport_ops = {
	494	.read = elcr_ioport_read,
	495	.write = elcr_ioport_write,
	496	.impl = {
	497	.min_access_size = 1,
	498	.max_access_size = 1,
	499	},
	500	};
	501
b0a21b53	502	/* XXX: add generic master/slave system */
660de336	503	static void pic_init1(int io_addr, int elcr_addr, PicState *s)
b0a21b53	504	{
098d314a RH	505	memory_region_init_io(&s->base_io, &pic_base_ioport_ops, s, "pic", 2);
	506	memory_region_init_io(&s->elcr_io, &pic_elcr_ioport_ops, s, "elcr", 1);
	507
	508	isa_register_ioport(NULL, &s->base_io, io_addr);
660de336	509	if (elcr_addr >= 0) {
098d314a	510	isa_register_ioport(NULL, &s->elcr_io, elcr_addr);
660de336	511	}
098d314a	512
0be71e32	513	vmstate_register(NULL, io_addr, &vmstate_pic, s);
a08d4367	514	qemu_register_reset(pic_reset, s);
b0a21b53 FB	515	}
b0a21b53 FB	516
376253ec	517	void pic_info(Monitor *mon)
ba91cd80 FB	518	{
	519	int i;
	520	PicState *s;
3b46e624	521
3de388f6 FB	522	if (!isa_pic)
3de388f6 FB	523	return;
ba91cd80 FB	524
ba91cd80 FB	525	for(i=0;i<2;i++) {
3de388f6	526	s = &isa_pic->pics[i];
376253ec AL	527	monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
	528	"irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
	529	i, s->irr, s->imr, s->isr, s->priority_add,
	530	s->irq_base, s->read_reg_select, s->elcr,
	531	s->special_fully_nested_mode);
ba91cd80 FB	532	}
	533	}
	534
376253ec	535	void irq_info(Monitor *mon)
4a0fb71e FB	536	{
4a0fb71e FB	537	#ifndef DEBUG_IRQ_COUNT
376253ec	538	monitor_printf(mon, "irq statistic code not compiled.\n");
4a0fb71e FB	539	#else
	540	int i;
	541	int64_t count;
	542
376253ec	543	monitor_printf(mon, "IRQ statistics:\n");
4a0fb71e FB	544	for (i = 0; i < 16; i++) {
	545	count = irq_count[i];
	546	if (count > 0)
376253ec	547	monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
4a0fb71e FB	548	}
	549	#endif
	550	}
ba91cd80	551
d537cf6c	552	qemu_irq *i8259_init(qemu_irq parent_irq)
80cabfad	553	{
3de388f6	554	PicState2 *s;
d537cf6c	555
7267c094	556	s = g_malloc0(sizeof(PicState2));
3de388f6 FB	557	pic_init1(0x20, 0x4d0, &s->pics[0]);
	558	pic_init1(0xa0, 0x4d1, &s->pics[1]);
	559	s->pics[0].elcr_mask = 0xf8;
	560	s->pics[1].elcr_mask = 0xde;
d537cf6c	561	s->parent_irq = parent_irq;
3de388f6 FB	562	s->pics[0].pics_state = s;
3de388f6 FB	563	s->pics[1].pics_state = s;
d537cf6c PB	564	isa_pic = s;
d537cf6c PB	565	return qemu_allocate_irqs(i8259_set_irq, s, 16);
80cabfad	566	}