[qemu.git] / hw / ssi / imx_spi.c

/*
 * IMX SPI Controller
 *
 * Copyright (c) 2016 Jean-Christophe Dubois <[email protected]>
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 *
 */

#include "qemu/osdep.h"
#include "hw/ssi/imx_spi.h"
#include "sysemu/sysemu.h"
#include "qemu/log.h"

#ifndef DEBUG_IMX_SPI
#define DEBUG_IMX_SPI 0
#endif

#define DPRINTF(fmt, args...) \
    do { \
        if (DEBUG_IMX_SPI) { \
            fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SPI, \
                                             __func__, ##args); \
        } \
    } while (0)

static const char *imx_spi_reg_name(uint32_t reg)
{
    static char unknown[20];

    switch (reg) {
    case ECSPI_RXDATA:
        return  "ECSPI_RXDATA";
    case ECSPI_TXDATA:
        return  "ECSPI_TXDATA";
    case ECSPI_CONREG:
        return  "ECSPI_CONREG";
    case ECSPI_CONFIGREG:
        return  "ECSPI_CONFIGREG";
    case ECSPI_INTREG:
        return  "ECSPI_INTREG";
    case ECSPI_DMAREG:
        return  "ECSPI_DMAREG";
    case ECSPI_STATREG:
        return  "ECSPI_STATREG";
    case ECSPI_PERIODREG:
        return  "ECSPI_PERIODREG";
    case ECSPI_TESTREG:
        return  "ECSPI_TESTREG";
    case ECSPI_MSGDATA:
        return  "ECSPI_MSGDATA";
    default:
        sprintf(unknown, "%d ?", reg);
        return unknown;
    }
}

static const VMStateDescription vmstate_imx_spi = {
    .name = TYPE_IMX_SPI,
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_FIFO32(tx_fifo, IMXSPIState),
        VMSTATE_FIFO32(rx_fifo, IMXSPIState),
        VMSTATE_INT16(burst_length, IMXSPIState),
        VMSTATE_UINT32_ARRAY(regs, IMXSPIState, ECSPI_MAX),
        VMSTATE_END_OF_LIST()
    },
};

static void imx_spi_txfifo_reset(IMXSPIState *s)
{
    fifo32_reset(&s->tx_fifo);
    s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TE;
    s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TF;
}

static void imx_spi_rxfifo_reset(IMXSPIState *s)
{
    fifo32_reset(&s->rx_fifo);
    s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RR;
    s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RF;
    s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RO;
}

static void imx_spi_update_irq(IMXSPIState *s)
{
    int level;

    if (fifo32_is_empty(&s->rx_fifo)) {
        s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RR;
    } else {
        s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RR;
    }

    if (fifo32_is_full(&s->rx_fifo)) {
        s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RF;
    } else {
        s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RF;
    }

    if (fifo32_is_empty(&s->tx_fifo)) {
        s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TE;
    } else {
        s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TE;
    }

    if (fifo32_is_full(&s->tx_fifo)) {
        s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TF;
    } else {
        s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TF;
    }

    level = s->regs[ECSPI_STATREG] & s->regs[ECSPI_INTREG] ? 1 : 0;

    qemu_set_irq(s->irq, level);

    DPRINTF("IRQ level is %d\n", level);
}

static uint8_t imx_spi_selected_channel(IMXSPIState *s)
{
    return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_CHANNEL_SELECT);
}

static uint32_t imx_spi_burst_length(IMXSPIState *s)
{
    return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1;
}

static bool imx_spi_is_enabled(IMXSPIState *s)
{
    return s->regs[ECSPI_CONREG] & ECSPI_CONREG_EN;
}

static bool imx_spi_channel_is_master(IMXSPIState *s)
{
    uint8_t mode = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_CHANNEL_MODE);

    return (mode & (1 << imx_spi_selected_channel(s))) ? true : false;
}

static bool imx_spi_is_multiple_master_burst(IMXSPIState *s)
{
    uint8_t wave = EXTRACT(s->regs[ECSPI_CONFIGREG], ECSPI_CONFIGREG_SS_CTL);

    return imx_spi_channel_is_master(s) &&
           !(s->regs[ECSPI_CONREG] & ECSPI_CONREG_SMC) &&
           ((wave & (1 << imx_spi_selected_channel(s))) ? true : false);
}

static void imx_spi_flush_txfifo(IMXSPIState *s)
{
    uint32_t tx;
    uint32_t rx;

    DPRINTF("Begin: TX Fifo Size = %d, RX Fifo Size = %d\n",
            fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo));

    while (!fifo32_is_empty(&s->tx_fifo)) {
        int tx_burst = 0;
        int index = 0;

        if (s->burst_length <= 0) {
            s->burst_length = imx_spi_burst_length(s);

            DPRINTF("Burst length = %d\n", s->burst_length);

            if (imx_spi_is_multiple_master_burst(s)) {
                s->regs[ECSPI_CONREG] |= ECSPI_CONREG_XCH;
            }
        }

        tx = fifo32_pop(&s->tx_fifo);

        DPRINTF("data tx:0x%08x\n", tx);

        tx_burst = MIN(s->burst_length, 32);

        rx = 0;

        while (tx_burst) {
            uint8_t byte = tx & 0xff;

            DPRINTF("writing 0x%02x\n", (uint32_t)byte);

            /* We need to write one byte at a time */
            byte = ssi_transfer(s->bus, byte);

            DPRINTF("0x%02x read\n", (uint32_t)byte);

            tx = tx >> 8;
            rx |= (byte << (index * 8));

            /* Remove 8 bits from the actual burst */
            tx_burst -= 8;
            s->burst_length -= 8;
            index++;
        }

        DPRINTF("data rx:0x%08x\n", rx);

        if (fifo32_is_full(&s->rx_fifo)) {
            s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RO;
        } else {
            fifo32_push(&s->rx_fifo, (uint8_t)rx);
        }

        if (s->burst_length <= 0) {
            s->regs[ECSPI_CONREG] &= ~ECSPI_CONREG_XCH;

            if (!imx_spi_is_multiple_master_burst(s)) {
                s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TC;
                break;
            }
        }
    }

    if (fifo32_is_empty(&s->tx_fifo)) {
        s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TC;
    }

    /* TODO: We should also use TDR and RDR bits */

    DPRINTF("End: TX Fifo Size = %d, RX Fifo Size = %d\n",
            fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo));
}

static void imx_spi_reset(DeviceState *dev)
{
    IMXSPIState *s = IMX_SPI(dev);

    DPRINTF("\n");

    memset(s->regs, 0, sizeof(s->regs));

    s->regs[ECSPI_STATREG] = 0x00000003;

    imx_spi_rxfifo_reset(s);
    imx_spi_txfifo_reset(s);

    imx_spi_update_irq(s);

    s->burst_length = 0;
}

static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size)
{
    uint32_t value = 0;
    IMXSPIState *s = opaque;
    uint32_t index = offset >> 2;

    if (index >=  ECSPI_MAX) {
        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
                      HWADDR_PRIx "\n", TYPE_IMX_SPI, __func__, offset);
        return 0;
    }

    switch (index) {
    case ECSPI_RXDATA:
        if (!imx_spi_is_enabled(s)) {
            value = 0;
        } else if (fifo32_is_empty(&s->rx_fifo)) {
            /* value is undefined */
            value = 0xdeadbeef;
        } else {
            /* read from the RX FIFO */
            value = fifo32_pop(&s->rx_fifo);
        }

        break;
    case ECSPI_TXDATA:
        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from TX FIFO\n",
                      TYPE_IMX_SPI, __func__);

        /* Reading from TXDATA gives 0 */

        break;
    case ECSPI_MSGDATA:
        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from MSG FIFO\n",
                      TYPE_IMX_SPI, __func__);

        /* Reading from MSGDATA gives 0 */

        break;
    default:
        value = s->regs[index];
        break;
    }

    DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx_spi_reg_name(index), value);

    imx_spi_update_irq(s);

    return (uint64_t)value;
}

static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
                           unsigned size)
{
    IMXSPIState *s = opaque;
    uint32_t index = offset >> 2;
    uint32_t change_mask;

    if (index >=  ECSPI_MAX) {
        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
                      HWADDR_PRIx "\n", TYPE_IMX_SPI, __func__, offset);
        return;
    }

    DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_spi_reg_name(index),
            (uint32_t)value);

    change_mask = s->regs[index] ^ value;

    switch (index) {
    case ECSPI_RXDATA:
        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to write to RX FIFO\n",
                      TYPE_IMX_SPI, __func__);
        break;
    case ECSPI_TXDATA:
        if (!imx_spi_is_enabled(s)) {
            /* Ignore writes if device is disabled */
            break;
        } else if (fifo32_is_full(&s->tx_fifo)) {
            /* Ignore writes if queue is full */
            break;
        }

        fifo32_push(&s->tx_fifo, (uint32_t)value);

        if (imx_spi_channel_is_master(s) &&
            (s->regs[ECSPI_CONREG] & ECSPI_CONREG_SMC)) {
            /*
             * Start emitting if current channel is master and SMC bit is
             * set.
             */
            imx_spi_flush_txfifo(s);
        }

        break;
    case ECSPI_STATREG:
        /* the RO and TC bits are write-one-to-clear */
        value &= ECSPI_STATREG_RO | ECSPI_STATREG_TC;
        s->regs[ECSPI_STATREG] &= ~value;

        break;
    case ECSPI_CONREG:
        s->regs[ECSPI_CONREG] = value;

        if (!imx_spi_is_enabled(s)) {
            /* device is disabled, so this is a reset */
            imx_spi_reset(DEVICE(s));
            return;
        }

        if (imx_spi_channel_is_master(s)) {
            int i;

            /* We are in master mode */

            for (i = 0; i < 4; i++) {
                qemu_set_irq(s->cs_lines[i],
                             i == imx_spi_selected_channel(s) ? 0 : 1);
            }

            if ((value & change_mask & ECSPI_CONREG_SMC) &&
                !fifo32_is_empty(&s->tx_fifo)) {
                /* SMC bit is set and TX FIFO has some slots filled in */
                imx_spi_flush_txfifo(s);
            } else if ((value & change_mask & ECSPI_CONREG_XCH) &&
                !(value & ECSPI_CONREG_SMC)) {
                /* This is a request to start emitting */
                imx_spi_flush_txfifo(s);
            }
        }

        break;
    case ECSPI_MSGDATA:
        /* it is not clear from the spec what MSGDATA is for */
        /* Anyway it is not used by Linux driver */
        /* So for now we just ignore it */
        qemu_log_mask(LOG_UNIMP,
                      "[%s]%s: Trying to write to MSGDATA, ignoring\n",
                      TYPE_IMX_SPI, __func__);
        break;
    default:
        s->regs[index] = value;

        break;
    }

    imx_spi_update_irq(s);
}

static const struct MemoryRegionOps imx_spi_ops = {
    .read = imx_spi_read,
    .write = imx_spi_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        /*
         * Our device would not work correctly if the guest was doing
         * unaligned access. This might not be a limitation on the real
         * device but in practice there is no reason for a guest to access
         * this device unaligned.
         */
        .min_access_size = 4,
        .max_access_size = 4,
        .unaligned = false,
    },
};

static void imx_spi_realize(DeviceState *dev, Error **errp)
{
    IMXSPIState *s = IMX_SPI(dev);
    int i;

    s->bus = ssi_create_bus(dev, "spi");

    memory_region_init_io(&s->iomem, OBJECT(dev), &imx_spi_ops, s,
                          TYPE_IMX_SPI, 0x1000);
    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
    sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);

    ssi_auto_connect_slaves(dev, s->cs_lines, s->bus);

    for (i = 0; i < 4; ++i) {
        sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]);
    }

    s->burst_length = 0;

    fifo32_create(&s->tx_fifo, ECSPI_FIFO_SIZE);
    fifo32_create(&s->rx_fifo, ECSPI_FIFO_SIZE);
}

static void imx_spi_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = imx_spi_realize;
    dc->vmsd = &vmstate_imx_spi;
    dc->reset = imx_spi_reset;
    dc->desc = "i.MX SPI Controller";
}

static const TypeInfo imx_spi_info = {
    .name          = TYPE_IMX_SPI,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(IMXSPIState),
    .class_init    = imx_spi_class_init,
};

static void imx_spi_register_types(void)
{
    type_register_static(&imx_spi_info);
}

type_init(imx_spi_register_types)
Commit	Line	Data
c906a3a0 JCD	1	/*
	2	* IMX SPI Controller
	3	*
	4	* Copyright (c) 2016 Jean-Christophe Dubois <[email protected]>
	5	*
	6	* This work is licensed under the terms of the GNU GPL, version 2 or later.
	7	* See the COPYING file in the top-level directory.
	8	*
	9	*/
	10
	11	#include "qemu/osdep.h"
	12	#include "hw/ssi/imx_spi.h"
	13	#include "sysemu/sysemu.h"
03dd024f	14	#include "qemu/log.h"
c906a3a0 JCD	15
	16	#ifndef DEBUG_IMX_SPI
	17	#define DEBUG_IMX_SPI 0
	18	#endif
	19
	20	#define DPRINTF(fmt, args...) \
	21	do { \
	22	if (DEBUG_IMX_SPI) { \
	23	fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SPI, \
	24	__func__, ##args); \
	25	} \
	26	} while (0)
	27
d675765a	28	static const char *imx_spi_reg_name(uint32_t reg)
c906a3a0 JCD	29	{
	30	static char unknown[20];
	31
	32	switch (reg) {
	33	case ECSPI_RXDATA:
	34	return "ECSPI_RXDATA";
	35	case ECSPI_TXDATA:
	36	return "ECSPI_TXDATA";
	37	case ECSPI_CONREG:
	38	return "ECSPI_CONREG";
	39	case ECSPI_CONFIGREG:
	40	return "ECSPI_CONFIGREG";
	41	case ECSPI_INTREG:
	42	return "ECSPI_INTREG";
	43	case ECSPI_DMAREG:
	44	return "ECSPI_DMAREG";
	45	case ECSPI_STATREG:
	46	return "ECSPI_STATREG";
	47	case ECSPI_PERIODREG:
	48	return "ECSPI_PERIODREG";
	49	case ECSPI_TESTREG:
	50	return "ECSPI_TESTREG";
	51	case ECSPI_MSGDATA:
	52	return "ECSPI_MSGDATA";
	53	default:
	54	sprintf(unknown, "%d ?", reg);
	55	return unknown;
	56	}
	57	}
	58
	59	static const VMStateDescription vmstate_imx_spi = {
	60	.name = TYPE_IMX_SPI,
	61	.version_id = 1,
	62	.minimum_version_id = 1,
	63	.fields = (VMStateField[]) {
	64	VMSTATE_FIFO32(tx_fifo, IMXSPIState),
	65	VMSTATE_FIFO32(rx_fifo, IMXSPIState),
	66	VMSTATE_INT16(burst_length, IMXSPIState),
	67	VMSTATE_UINT32_ARRAY(regs, IMXSPIState, ECSPI_MAX),
	68	VMSTATE_END_OF_LIST()
	69	},
	70	};
	71
	72	static void imx_spi_txfifo_reset(IMXSPIState *s)
	73	{
	74	fifo32_reset(&s->tx_fifo);
	75	s->regs[ECSPI_STATREG] \|= ECSPI_STATREG_TE;
	76	s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TF;
	77	}
	78
	79	static void imx_spi_rxfifo_reset(IMXSPIState *s)
	80	{
	81	fifo32_reset(&s->rx_fifo);
	82	s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RR;
	83	s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RF;
	84	s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RO;
	85	}
	86
	87	static void imx_spi_update_irq(IMXSPIState *s)
	88	{
	89	int level;
	90
	91	if (fifo32_is_empty(&s->rx_fifo)) {
	92	s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RR;
93	} else {
94	s->regs[ECSPI_STATREG] \|= ECSPI_STATREG_RR;
95	}
96
97	if (fifo32_is_full(&s->rx_fifo)) {
98	s->regs[ECSPI_STATREG] \|= ECSPI_STATREG_RF;
99	} else {
100	s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RF;
101	}
102
103	if (fifo32_is_empty(&s->tx_fifo)) {
104	s->regs[ECSPI_STATREG] \|= ECSPI_STATREG_TE;
105	} else {
106	s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TE;
107	}
108
109	if (fifo32_is_full(&s->tx_fifo)) {
110	s->regs[ECSPI_STATREG] \|= ECSPI_STATREG_TF;
111	} else {
112	s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TF;
113	}
114
115	level = s->regs[ECSPI_STATREG] & s->regs[ECSPI_INTREG] ? 1 : 0;
116
117	qemu_set_irq(s->irq, level);
118
119	DPRINTF("IRQ level is %d\n", level);
120	}
121
122	static uint8_t imx_spi_selected_channel(IMXSPIState *s)
123	{
124	return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_CHANNEL_SELECT);
125	}
126
127	static uint32_t imx_spi_burst_length(IMXSPIState *s)
128	{
129	return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1;
130	}
131
132	static bool imx_spi_is_enabled(IMXSPIState *s)
133	{
134	return s->regs[ECSPI_CONREG] & ECSPI_CONREG_EN;
135	}
136
137	static bool imx_spi_channel_is_master(IMXSPIState *s)
138	{
139	uint8_t mode = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_CHANNEL_MODE);
140
141	return (mode & (1 << imx_spi_selected_channel(s))) ? true : false;
142	}
143
144	static bool imx_spi_is_multiple_master_burst(IMXSPIState *s)
145	{
146	uint8_t wave = EXTRACT(s->regs[ECSPI_CONFIGREG], ECSPI_CONFIGREG_SS_CTL);
147
148	return imx_spi_channel_is_master(s) &&
149	!(s->regs[ECSPI_CONREG] & ECSPI_CONREG_SMC) &&
150	((wave & (1 << imx_spi_selected_channel(s))) ? true : false);
151	}
152
153	static void imx_spi_flush_txfifo(IMXSPIState *s)
154	{
155	uint32_t tx;
156	uint32_t rx;
157
158	DPRINTF("Begin: TX Fifo Size = %d, RX Fifo Size = %d\n",
159	fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo));
160
161	while (!fifo32_is_empty(&s->tx_fifo)) {
162	int tx_burst = 0;
163	int index = 0;
164
165	if (s->burst_length <= 0) {
166	s->burst_length = imx_spi_burst_length(s);
167
168	DPRINTF("Burst length = %d\n", s->burst_length);
169
170	if (imx_spi_is_multiple_master_burst(s)) {
171	s->regs[ECSPI_CONREG] \|= ECSPI_CONREG_XCH;
172	}
173	}
174
175	tx = fifo32_pop(&s->tx_fifo);
176
177	DPRINTF("data tx:0x%08x\n", tx);
178
179	tx_burst = MIN(s->burst_length, 32);
180
181	rx = 0;
182
183	while (tx_burst) {
184	uint8_t byte = tx & 0xff;
185
186	DPRINTF("writing 0x%02x\n", (uint32_t)byte);
187
188	/* We need to write one byte at a time */
189	byte = ssi_transfer(s->bus, byte);
190
191	DPRINTF("0x%02x read\n", (uint32_t)byte);
192
193	tx = tx >> 8;
194	rx \|= (byte << (index * 8));
195
196	/* Remove 8 bits from the actual burst */
197	tx_burst -= 8;
198	s->burst_length -= 8;
199	index++;
200	}
201
202	DPRINTF("data rx:0x%08x\n", rx);
203
204	if (fifo32_is_full(&s->rx_fifo)) {
205	s->regs[ECSPI_STATREG] \|= ECSPI_STATREG_RO;
206	} else {
207	fifo32_push(&s->rx_fifo, (uint8_t)rx);
208	}
209
210	if (s->burst_length <= 0) {
211	s->regs[ECSPI_CONREG] &= ~ECSPI_CONREG_XCH;
212
213	if (!imx_spi_is_multiple_master_burst(s)) {
214	s->regs[ECSPI_STATREG] \|= ECSPI_STATREG_TC;
215	break;
216	}
217	}
218	}
219
220	if (fifo32_is_empty(&s->tx_fifo)) {
221	s->regs[ECSPI_STATREG] \|= ECSPI_STATREG_TC;
222	}
223
224	/* TODO: We should also use TDR and RDR bits */
225
226	DPRINTF("End: TX Fifo Size = %d, RX Fifo Size = %d\n",
227	fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo));
228	}
229
230	static void imx_spi_reset(DeviceState *dev)
231	{
232	IMXSPIState *s = IMX_SPI(dev);
233
234	DPRINTF("\n");
235
236	memset(s->regs, 0, sizeof(s->regs));
237
238	s->regs[ECSPI_STATREG] = 0x00000003;
239
240	imx_spi_rxfifo_reset(s);
241	imx_spi_txfifo_reset(s);
242
243	imx_spi_update_irq(s);
244
245	s->burst_length = 0;
246	}
247
248	static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size)
249	{
250	uint32_t value = 0;
251	IMXSPIState *s = opaque;
252	uint32_t index = offset >> 2;
253
254	if (index >= ECSPI_MAX) {
255	qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
256	HWADDR_PRIx "\n", TYPE_IMX_SPI, __func__, offset);
257	return 0;
258	}
259
260	switch (index) {
261	case ECSPI_RXDATA:
262	if (!imx_spi_is_enabled(s)) {
263	value = 0;
264	} else if (fifo32_is_empty(&s->rx_fifo)) {
265	/* value is undefined */
266	value = 0xdeadbeef;
267	} else {
268	/* read from the RX FIFO */
269	value = fifo32_pop(&s->rx_fifo);
270	}
271
272	break;
273	case ECSPI_TXDATA:
274	qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from TX FIFO\n",
275	TYPE_IMX_SPI, __func__);
276
277	/* Reading from TXDATA gives 0 */
278
279	break;
280	case ECSPI_MSGDATA:
281	qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from MSG FIFO\n",
282	TYPE_IMX_SPI, __func__);
283
284	/* Reading from MSGDATA gives 0 */
285
286	break;
287	default:
288	value = s->regs[index];
289	break;
290	}
291
292	DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx_spi_reg_name(index), value);
293
294	imx_spi_update_irq(s);
295
296	return (uint64_t)value;
297	}
298
299	static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
300	unsigned size)
301	{
302	IMXSPIState *s = opaque;
303	uint32_t index = offset >> 2;
304	uint32_t change_mask;
305
306	if (index >= ECSPI_MAX) {
307	qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
308	HWADDR_PRIx "\n", TYPE_IMX_SPI, __func__, offset);
309	return;
310	}
311
312	DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_spi_reg_name(index),
313	(uint32_t)value);
314
315	change_mask = s->regs[index] ^ value;
316
317	switch (index) {
318	case ECSPI_RXDATA:
319	qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to write to RX FIFO\n",
320	TYPE_IMX_SPI, __func__);
321	break;
322	case ECSPI_TXDATA:
c906a3a0 JCD	323	if (!imx_spi_is_enabled(s)) {
	324	/* Ignore writes if device is disabled */
	325	break;
	326	} else if (fifo32_is_full(&s->tx_fifo)) {
	327	/* Ignore writes if queue is full */
	328	break;
	329	}
	330
	331	fifo32_push(&s->tx_fifo, (uint32_t)value);
	332
	333	if (imx_spi_channel_is_master(s) &&
	334	(s->regs[ECSPI_CONREG] & ECSPI_CONREG_SMC)) {
	335	/*
	336	* Start emitting if current channel is master and SMC bit is
	337	* set.
	338	*/
	339	imx_spi_flush_txfifo(s);
	340	}
	341
	342	break;
	343	case ECSPI_STATREG:
	344	/* the RO and TC bits are write-one-to-clear */
	345	value &= ECSPI_STATREG_RO \| ECSPI_STATREG_TC;
	346	s->regs[ECSPI_STATREG] &= ~value;
	347
	348	break;
	349	case ECSPI_CONREG:
	350	s->regs[ECSPI_CONREG] = value;
	351
	352	if (!imx_spi_is_enabled(s)) {
	353	/* device is disabled, so this is a reset */
	354	imx_spi_reset(DEVICE(s));
	355	return;
	356	}
	357
	358	if (imx_spi_channel_is_master(s)) {
	359	int i;
	360
	361	/* We are in master mode */
	362
	363	for (i = 0; i < 4; i++) {
	364	qemu_set_irq(s->cs_lines[i],
	365	i == imx_spi_selected_channel(s) ? 0 : 1);
	366	}
	367
	368	if ((value & change_mask & ECSPI_CONREG_SMC) &&
	369	!fifo32_is_empty(&s->tx_fifo)) {
	370	/* SMC bit is set and TX FIFO has some slots filled in */
	371	imx_spi_flush_txfifo(s);
	372	} else if ((value & change_mask & ECSPI_CONREG_XCH) &&
	373	!(value & ECSPI_CONREG_SMC)) {
	374	/* This is a request to start emitting */
	375	imx_spi_flush_txfifo(s);
	376	}
	377	}
	378
	379	break;
556899fc JCD	380	case ECSPI_MSGDATA:
	381	/* it is not clear from the spec what MSGDATA is for */
	382	/* Anyway it is not used by Linux driver */
	383	/* So for now we just ignore it */
	384	qemu_log_mask(LOG_UNIMP,
	385	"[%s]%s: Trying to write to MSGDATA, ignoring\n",
	386	TYPE_IMX_SPI, __func__);
	387	break;
c906a3a0 JCD	388	default:
	389	s->regs[index] = value;
	390
	391	break;
	392	}
	393
	394	imx_spi_update_irq(s);
	395	}
	396
	397	static const struct MemoryRegionOps imx_spi_ops = {
	398	.read = imx_spi_read,
	399	.write = imx_spi_write,
	400	.endianness = DEVICE_NATIVE_ENDIAN,
	401	.valid = {
	402	/*
	403	* Our device would not work correctly if the guest was doing
	404	* unaligned access. This might not be a limitation on the real
	405	* device but in practice there is no reason for a guest to access
	406	* this device unaligned.
	407	*/
	408	.min_access_size = 4,
	409	.max_access_size = 4,
	410	.unaligned = false,
	411	},
	412	};
	413
	414	static void imx_spi_realize(DeviceState dev, Error *errp)
	415	{
	416	IMXSPIState *s = IMX_SPI(dev);
	417	int i;
	418
	419	s->bus = ssi_create_bus(dev, "spi");
	420
	421	memory_region_init_io(&s->iomem, OBJECT(dev), &imx_spi_ops, s,
	422	TYPE_IMX_SPI, 0x1000);
	423	sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
	424	sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
	425
	426	ssi_auto_connect_slaves(dev, s->cs_lines, s->bus);
	427
	428	for (i = 0; i < 4; ++i) {
	429	sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]);
	430	}
	431
	432	s->burst_length = 0;
	433
	434	fifo32_create(&s->tx_fifo, ECSPI_FIFO_SIZE);
	435	fifo32_create(&s->rx_fifo, ECSPI_FIFO_SIZE);
	436	}
	437
	438	static void imx_spi_class_init(ObjectClass klass, void data)
	439	{
	440	DeviceClass *dc = DEVICE_CLASS(klass);
	441
	442	dc->realize = imx_spi_realize;
	443	dc->vmsd = &vmstate_imx_spi;
	444	dc->reset = imx_spi_reset;
	445	dc->desc = "i.MX SPI Controller";
	446	}
	447
	448	static const TypeInfo imx_spi_info = {
	449	.name = TYPE_IMX_SPI,
	450	.parent = TYPE_SYS_BUS_DEVICE,
	451	.instance_size = sizeof(IMXSPIState),
452	.class_init = imx_spi_class_init,
453	};
454
455	static void imx_spi_register_types(void)
456	{
457	type_register_static(&imx_spi_info);
458	}
459
460	type_init(imx_spi_register_types)