[qemu.git] / hw / intc / s390_flic.c

/*
 * QEMU S390x floating interrupt controller (flic)
 *
 * Copyright 2014 IBM Corp.
 * Author(s): Jens Freimann <[email protected]>
 *            Cornelia Huck <[email protected]>
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or (at
 * your option) any later version. See the COPYING file in the top-level
 * directory.
 */

#include "qemu/osdep.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "hw/sysbus.h"
#include "hw/s390x/ioinst.h"
#include "hw/s390x/s390_flic.h"
#include "hw/s390x/css.h"
#include "trace.h"
#include "cpu.h"
#include "hw/qdev.h"
#include "qapi/error.h"
#include "hw/s390x/s390-virtio-ccw.h"

S390FLICStateClass *s390_get_flic_class(S390FLICState *fs)
{
    static S390FLICStateClass *class;

    if (!class) {
        /* we only have one flic device, so this is fine to cache */
        class = S390_FLIC_COMMON_GET_CLASS(fs);
    }
    return class;
}

QEMUS390FLICState *s390_get_qemu_flic(S390FLICState *fs)
{
    static QEMUS390FLICState *flic;

    if (!flic) {
        /* we only have one flic device, so this is fine to cache */
        flic = QEMU_S390_FLIC(fs);
    }
    return flic;
}

S390FLICState *s390_get_flic(void)
{
    static S390FLICState *fs;

    if (!fs) {
        fs = S390_FLIC_COMMON(object_resolve_path_type("",
                                                       TYPE_S390_FLIC_COMMON,
                                                       NULL));
    }
    return fs;
}

void s390_flic_init(void)
{
    DeviceState *dev;

    if (kvm_enabled()) {
        dev = qdev_create(NULL, TYPE_KVM_S390_FLIC);
        object_property_add_child(qdev_get_machine(), TYPE_KVM_S390_FLIC,
                                  OBJECT(dev), NULL);
    } else {
        dev = qdev_create(NULL, TYPE_QEMU_S390_FLIC);
        object_property_add_child(qdev_get_machine(), TYPE_QEMU_S390_FLIC,
                                  OBJECT(dev), NULL);
    }
    qdev_init_nofail(dev);
}

static int qemu_s390_register_io_adapter(S390FLICState *fs, uint32_t id,
                                         uint8_t isc, bool swap,
                                         bool is_maskable, uint8_t flags)
{
    /* nothing to do */
    return 0;
}

static int qemu_s390_io_adapter_map(S390FLICState *fs, uint32_t id,
                                    uint64_t map_addr, bool do_map)
{
    /* nothing to do */
    return 0;
}

static int qemu_s390_add_adapter_routes(S390FLICState *fs,
                                        AdapterRoutes *routes)
{
    return -ENOSYS;
}

static void qemu_s390_release_adapter_routes(S390FLICState *fs,
                                             AdapterRoutes *routes)
{
}

static int qemu_s390_clear_io_flic(S390FLICState *fs, uint16_t subchannel_id,
                           uint16_t subchannel_nr)
{
    QEMUS390FLICState *flic  = s390_get_qemu_flic(fs);
    QEMUS390FlicIO *cur, *next;
    uint8_t isc;

    g_assert(qemu_mutex_iothread_locked());
    if (!(flic->pending & FLIC_PENDING_IO)) {
        return 0;
    }

    /* check all iscs */
    for (isc = 0; isc < 8; isc++) {
        if (QLIST_EMPTY(&flic->io[isc])) {
            continue;
        }

        /* search and delete any matching one */
        QLIST_FOREACH_SAFE(cur, &flic->io[isc], next, next) {
            if (cur->id == subchannel_id && cur->nr == subchannel_nr) {
                QLIST_REMOVE(cur, next);
                g_free(cur);
            }
        }

        /* update our indicator bit */
        if (QLIST_EMPTY(&flic->io[isc])) {
            flic->pending &= ~ISC_TO_PENDING_IO(isc);
        }
    }
    return 0;
}

static int qemu_s390_modify_ais_mode(S390FLICState *fs, uint8_t isc,
                                     uint16_t mode)
{
    QEMUS390FLICState *flic  = s390_get_qemu_flic(fs);

    switch (mode) {
    case SIC_IRQ_MODE_ALL:
        flic->simm &= ~AIS_MODE_MASK(isc);
        flic->nimm &= ~AIS_MODE_MASK(isc);
        break;
    case SIC_IRQ_MODE_SINGLE:
        flic->simm |= AIS_MODE_MASK(isc);
        flic->nimm &= ~AIS_MODE_MASK(isc);
        break;
    default:
        return -EINVAL;
    }

    return 0;
}

static int qemu_s390_inject_airq(S390FLICState *fs, uint8_t type,
                                 uint8_t isc, uint8_t flags)
{
    QEMUS390FLICState *flic = s390_get_qemu_flic(fs);
    S390FLICStateClass *fsc = s390_get_flic_class(fs);
    bool flag = flags & S390_ADAPTER_SUPPRESSIBLE;
    uint32_t io_int_word = (isc << 27) | IO_INT_WORD_AI;

    if (flag && (flic->nimm & AIS_MODE_MASK(isc))) {
        trace_qemu_s390_airq_suppressed(type, isc);
        return 0;
    }

    fsc->inject_io(fs, 0, 0, 0, io_int_word);

    if (flag && (flic->simm & AIS_MODE_MASK(isc))) {
        flic->nimm |= AIS_MODE_MASK(isc);
        trace_qemu_s390_suppress_airq(isc, "Single-Interruption Mode",
                                      "NO-Interruptions Mode");
    }

    return 0;
}

static void qemu_s390_flic_notify(uint32_t type)
{
    CPUState *cs;

    /*
     * We have to make all CPUs see CPU_INTERRUPT_HARD, so they might
     * consider it. We will kick all running CPUs and only relevant
     * sleeping ones.
     */
    CPU_FOREACH(cs) {
        S390CPU *cpu = S390_CPU(cs);

        cs->interrupt_request |= CPU_INTERRUPT_HARD;

        /* ignore CPUs that are not sleeping */
        if (s390_cpu_get_state(cpu) != S390_CPU_STATE_OPERATING &&
            s390_cpu_get_state(cpu) != S390_CPU_STATE_LOAD) {
            continue;
        }

        /* we always kick running CPUs for now, this is tricky */
        if (cs->halted) {
            /* don't check for subclasses, CPUs double check when waking up */
            if (type & FLIC_PENDING_SERVICE) {
                if (!(cpu->env.psw.mask & PSW_MASK_EXT)) {
                    continue;
                }
            } else if (type & FLIC_PENDING_IO) {
                if (!(cpu->env.psw.mask & PSW_MASK_IO)) {
                    continue;
                }
            } else if (type & FLIC_PENDING_MCHK_CR) {
                if (!(cpu->env.psw.mask & PSW_MASK_MCHECK)) {
                    continue;
                }
            }
        }
        cpu_interrupt(cs, CPU_INTERRUPT_HARD);
    }
}

uint32_t qemu_s390_flic_dequeue_service(QEMUS390FLICState *flic)
{
    uint32_t tmp;

    g_assert(qemu_mutex_iothread_locked());
    g_assert(flic->pending & FLIC_PENDING_SERVICE);
    tmp = flic->service_param;
    flic->service_param = 0;
    flic->pending &= ~FLIC_PENDING_SERVICE;

    return tmp;
}

/* caller has to free the returned object */
QEMUS390FlicIO *qemu_s390_flic_dequeue_io(QEMUS390FLICState *flic, uint64_t cr6)
{
    QEMUS390FlicIO *io;
    uint8_t isc;

    g_assert(qemu_mutex_iothread_locked());
    if (!(flic->pending & CR6_TO_PENDING_IO(cr6))) {
        return NULL;
    }

    for (isc = 0; isc < 8; isc++) {
        if (QLIST_EMPTY(&flic->io[isc]) || !(cr6 & ISC_TO_ISC_BITS(isc))) {
            continue;
        }
        io = QLIST_FIRST(&flic->io[isc]);
        QLIST_REMOVE(io, next);

        /* update our indicator bit */
        if (QLIST_EMPTY(&flic->io[isc])) {
            flic->pending &= ~ISC_TO_PENDING_IO(isc);
        }
        return io;
    }

    return NULL;
}

void qemu_s390_flic_dequeue_crw_mchk(QEMUS390FLICState *flic)
{
    g_assert(qemu_mutex_iothread_locked());
    g_assert(flic->pending & FLIC_PENDING_MCHK_CR);
    flic->pending &= ~FLIC_PENDING_MCHK_CR;
}

static void qemu_s390_inject_service(S390FLICState *fs, uint32_t parm)
{
    QEMUS390FLICState *flic = s390_get_qemu_flic(fs);

    g_assert(qemu_mutex_iothread_locked());
    /* multiplexing is good enough for sclp - kvm does it internally as well */
    flic->service_param |= parm;
    flic->pending |= FLIC_PENDING_SERVICE;

    qemu_s390_flic_notify(FLIC_PENDING_SERVICE);
}

static void qemu_s390_inject_io(S390FLICState *fs, uint16_t subchannel_id,
                                uint16_t subchannel_nr, uint32_t io_int_parm,
                                uint32_t io_int_word)
{
    const uint8_t isc = IO_INT_WORD_ISC(io_int_word);
    QEMUS390FLICState *flic = s390_get_qemu_flic(fs);
    QEMUS390FlicIO *io;

    g_assert(qemu_mutex_iothread_locked());
    io = g_new0(QEMUS390FlicIO, 1);
    io->id = subchannel_id;
    io->nr = subchannel_nr;
    io->parm = io_int_parm;
    io->word = io_int_word;

    QLIST_INSERT_HEAD(&flic->io[isc], io, next);
    flic->pending |= ISC_TO_PENDING_IO(isc);

    qemu_s390_flic_notify(ISC_TO_PENDING_IO(isc));
}

static void qemu_s390_inject_crw_mchk(S390FLICState *fs)
{
    QEMUS390FLICState *flic = s390_get_qemu_flic(fs);

    g_assert(qemu_mutex_iothread_locked());
    flic->pending |= FLIC_PENDING_MCHK_CR;

    qemu_s390_flic_notify(FLIC_PENDING_MCHK_CR);
}

bool qemu_s390_flic_has_service(QEMUS390FLICState *flic)
{
    /* called without lock via cc->has_work, will be validated under lock */
    return !!(flic->pending & FLIC_PENDING_SERVICE);
}

bool qemu_s390_flic_has_io(QEMUS390FLICState *flic, uint64_t cr6)
{
    /* called without lock via cc->has_work, will be validated under lock */
    return !!(flic->pending & CR6_TO_PENDING_IO(cr6));
}

bool qemu_s390_flic_has_crw_mchk(QEMUS390FLICState *flic)
{
    /* called without lock via cc->has_work, will be validated under lock */
    return !!(flic->pending & FLIC_PENDING_MCHK_CR);
}

bool qemu_s390_flic_has_any(QEMUS390FLICState *flic)
{
    g_assert(qemu_mutex_iothread_locked());
    return !!flic->pending;
}

static void qemu_s390_flic_reset(DeviceState *dev)
{
    QEMUS390FLICState *flic = QEMU_S390_FLIC(dev);
    QEMUS390FlicIO *cur, *next;
    int isc;

    g_assert(qemu_mutex_iothread_locked());
    flic->simm = 0;
    flic->nimm = 0;
    flic->pending = 0;

    /* remove all pending io interrupts */
    for (isc = 0; isc < 8; isc++) {
        QLIST_FOREACH_SAFE(cur, &flic->io[isc], next, next) {
            QLIST_REMOVE(cur, next);
            g_free(cur);
        }
    }
}

bool ais_needed(void *opaque)
{
    S390FLICState *s = opaque;

    return s->ais_supported;
}

static const VMStateDescription qemu_s390_flic_vmstate = {
    .name = "qemu-s390-flic",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = ais_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINT8(simm, QEMUS390FLICState),
        VMSTATE_UINT8(nimm, QEMUS390FLICState),
        VMSTATE_END_OF_LIST()
    }
};

static void qemu_s390_flic_instance_init(Object *obj)
{
    QEMUS390FLICState *flic = QEMU_S390_FLIC(obj);
    int isc;

    for (isc = 0; isc < 8; isc++) {
        QLIST_INIT(&flic->io[isc]);
    }
}

static void qemu_s390_flic_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);
    S390FLICStateClass *fsc = S390_FLIC_COMMON_CLASS(oc);

    dc->reset = qemu_s390_flic_reset;
    dc->vmsd = &qemu_s390_flic_vmstate;
    fsc->register_io_adapter = qemu_s390_register_io_adapter;
    fsc->io_adapter_map = qemu_s390_io_adapter_map;
    fsc->add_adapter_routes = qemu_s390_add_adapter_routes;
    fsc->release_adapter_routes = qemu_s390_release_adapter_routes;
    fsc->clear_io_irq = qemu_s390_clear_io_flic;
    fsc->modify_ais_mode = qemu_s390_modify_ais_mode;
    fsc->inject_airq = qemu_s390_inject_airq;
    fsc->inject_service = qemu_s390_inject_service;
    fsc->inject_io = qemu_s390_inject_io;
    fsc->inject_crw_mchk = qemu_s390_inject_crw_mchk;
}

static Property s390_flic_common_properties[] = {
    DEFINE_PROP_UINT32("adapter_routes_max_batch", S390FLICState,
                       adapter_routes_max_batch, ADAPTER_ROUTES_MAX_GSI),
    DEFINE_PROP_END_OF_LIST(),
};

static void s390_flic_common_realize(DeviceState *dev, Error **errp)
{
    S390FLICState *fs = S390_FLIC_COMMON(dev);
    uint32_t max_batch = fs->adapter_routes_max_batch;

    if (max_batch > ADAPTER_ROUTES_MAX_GSI) {
        error_setg(errp, "flic property adapter_routes_max_batch too big"
                   " (%d > %d)", max_batch, ADAPTER_ROUTES_MAX_GSI);
        return;
    }

    fs->ais_supported = s390_has_feat(S390_FEAT_ADAPTER_INT_SUPPRESSION);
}

static void s390_flic_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->props = s390_flic_common_properties;
    dc->realize = s390_flic_common_realize;
}

static const TypeInfo qemu_s390_flic_info = {
    .name          = TYPE_QEMU_S390_FLIC,
    .parent        = TYPE_S390_FLIC_COMMON,
    .instance_size = sizeof(QEMUS390FLICState),
    .instance_init = qemu_s390_flic_instance_init,
    .class_init    = qemu_s390_flic_class_init,
};


static const TypeInfo s390_flic_common_info = {
    .name          = TYPE_S390_FLIC_COMMON,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(S390FLICState),
    .class_init    = s390_flic_class_init,
    .class_size    = sizeof(S390FLICStateClass),
};

static void qemu_s390_flic_register_types(void)
{
    type_register_static(&s390_flic_common_info);
    type_register_static(&qemu_s390_flic_info);
}

type_init(qemu_s390_flic_register_types)

static bool adapter_info_so_needed(void *opaque)
{
    return css_migration_enabled();
}

const VMStateDescription vmstate_adapter_info_so = {
    .name = "s390_adapter_info/summary_offset",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = adapter_info_so_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(summary_offset, AdapterInfo),
        VMSTATE_END_OF_LIST()
    }
};

const VMStateDescription vmstate_adapter_info = {
    .name = "s390_adapter_info",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64(ind_offset, AdapterInfo),
        /*
         * We do not have to migrate neither the id nor the addresses.
         * The id is set by css_register_io_adapter and the addresses
         * are set based on the IndAddr objects after those get mapped.
         */
        VMSTATE_END_OF_LIST()
    },
    .subsections = (const VMStateDescription * []) {
        &vmstate_adapter_info_so,
        NULL
    }
};

const VMStateDescription vmstate_adapter_routes = {

    .name = "s390_adapter_routes",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_STRUCT(adapter, AdapterRoutes, 1, vmstate_adapter_info,
                       AdapterInfo),
        VMSTATE_END_OF_LIST()
    }
};
Commit	Line	Data
3a553fc6	1	/*
7b35d0c4	2	* QEMU S390x floating interrupt controller (flic)
3a553fc6 JF	3	*
	4	* Copyright 2014 IBM Corp.
	5	* Author(s): Jens Freimann <[email protected]>
7b35d0c4	6	* Cornelia Huck <[email protected]>
3a553fc6 JF	7	*
	8	* This work is licensed under the terms of the GNU GPL, version 2 or (at
	9	* your option) any later version. See the COPYING file in the top-level
	10	* directory.
	11	*/
	12
90191d07	13	#include "qemu/osdep.h"
3a553fc6	14	#include "qemu/error-report.h"
0b8fa32f	15	#include "qemu/module.h"
3a553fc6	16	#include "hw/sysbus.h"
1622ffd5	17	#include "hw/s390x/ioinst.h"
3a553fc6	18	#include "hw/s390x/s390_flic.h"
1622ffd5	19	#include "hw/s390x/css.h"
3a553fc6	20	#include "trace.h"
1622ffd5	21	#include "cpu.h"
e61cc6b5 HP	22	#include "hw/qdev.h"
e61cc6b5 HP	23	#include "qapi/error.h"
517ff12c	24	#include "hw/s390x/s390-virtio-ccw.h"
3a553fc6	25
6762808f DH	26	S390FLICStateClass s390_get_flic_class(S390FLICState fs)
	27	{
	28	static S390FLICStateClass *class;
	29
	30	if (!class) {
	31	/* we only have one flic device, so this is fine to cache */
	32	class = S390_FLIC_COMMON_GET_CLASS(fs);
	33	}
	34	return class;
	35	}
	36
f68ecdd4 DH	37	QEMUS390FLICState s390_get_qemu_flic(S390FLICState fs)
	38	{
	39	static QEMUS390FLICState *flic;
	40
	41	if (!flic) {
	42	/* we only have one flic device, so this is fine to cache */
	43	flic = QEMU_S390_FLIC(fs);
	44	}
	45	return flic;
	46	}
	47
7b35d0c4	48	S390FLICState *s390_get_flic(void)
819bd309	49	{
bc66d6cb	50	static S390FLICState *fs;
819bd309	51
7b35d0c4	52	if (!fs) {
b03d9970 DH	53	fs = S390_FLIC_COMMON(object_resolve_path_type("",
	54	TYPE_S390_FLIC_COMMON,
	55	NULL));
819bd309	56	}
7b35d0c4	57	return fs;
819bd309 DD	58	}
819bd309 DD	59
7b35d0c4	60	void s390_flic_init(void)
3a553fc6	61	{
7b35d0c4	62	DeviceState *dev;
3a553fc6	63
e2ac12f0 DH	64	if (kvm_enabled()) {
	65	dev = qdev_create(NULL, TYPE_KVM_S390_FLIC);
	66	object_property_add_child(qdev_get_machine(), TYPE_KVM_S390_FLIC,
	67	OBJECT(dev), NULL);
	68	} else {
7b35d0c4 CH	69	dev = qdev_create(NULL, TYPE_QEMU_S390_FLIC);
	70	object_property_add_child(qdev_get_machine(), TYPE_QEMU_S390_FLIC,
	71	OBJECT(dev), NULL);
3a553fc6	72	}
ae4a2bd7	73	qdev_init_nofail(dev);
3a553fc6 JF	74	}
3a553fc6 JF	75
03cf077a CH	76	static int qemu_s390_register_io_adapter(S390FLICState *fs, uint32_t id,
03cf077a CH	77	uint8_t isc, bool swap,
1497c160	78	bool is_maskable, uint8_t flags)
03cf077a CH	79	{
	80	/* nothing to do */
	81	return 0;
	82	}
	83
d426d9fb CH	84	static int qemu_s390_io_adapter_map(S390FLICState *fs, uint32_t id,
	85	uint64_t map_addr, bool do_map)
	86	{
	87	/* nothing to do */
	88	return 0;
	89	}
	90
	91	static int qemu_s390_add_adapter_routes(S390FLICState *fs,
	92	AdapterRoutes *routes)
	93	{
	94	return -ENOSYS;
	95	}
	96
	97	static void qemu_s390_release_adapter_routes(S390FLICState *fs,
	98	AdapterRoutes *routes)
	99	{
	100	}
	101
9eccb862 HP	102	static int qemu_s390_clear_io_flic(S390FLICState *fs, uint16_t subchannel_id,
	103	uint16_t subchannel_nr)
	104	{
f68ecdd4	105	QEMUS390FLICState *flic = s390_get_qemu_flic(fs);
6e0d8175 DH	106	QEMUS390FlicIO cur, next;
	107	uint8_t isc;
	108
	109	g_assert(qemu_mutex_iothread_locked());
	110	if (!(flic->pending & FLIC_PENDING_IO)) {
	111	return 0;
	112	}
	113
	114	/* check all iscs */
	115	for (isc = 0; isc < 8; isc++) {
	116	if (QLIST_EMPTY(&flic->io[isc])) {
	117	continue;
	118	}
	119
	120	/* search and delete any matching one */
	121	QLIST_FOREACH_SAFE(cur, &flic->io[isc], next, next) {
	122	if (cur->id == subchannel_id && cur->nr == subchannel_nr) {
	123	QLIST_REMOVE(cur, next);
	124	g_free(cur);
	125	}
	126	}
	127
	128	/* update our indicator bit */
	129	if (QLIST_EMPTY(&flic->io[isc])) {
	130	flic->pending &= ~ISC_TO_PENDING_IO(isc);
	131	}
	132	}
	133	return 0;
9eccb862 HP	134	}
9eccb862 HP	135
6c1dd652 FL	136	static int qemu_s390_modify_ais_mode(S390FLICState *fs, uint8_t isc,
	137	uint16_t mode)
	138	{
f68ecdd4	139	QEMUS390FLICState *flic = s390_get_qemu_flic(fs);
6c1dd652 FL	140
	141	switch (mode) {
	142	case SIC_IRQ_MODE_ALL:
	143	flic->simm &= ~AIS_MODE_MASK(isc);
	144	flic->nimm &= ~AIS_MODE_MASK(isc);
	145	break;
	146	case SIC_IRQ_MODE_SINGLE:
	147	flic->simm \|= AIS_MODE_MASK(isc);
	148	flic->nimm &= ~AIS_MODE_MASK(isc);
	149	break;
	150	default:
	151	return -EINVAL;
	152	}
	153
	154	return 0;
	155	}
	156
1622ffd5 YMZ	157	static int qemu_s390_inject_airq(S390FLICState *fs, uint8_t type,
	158	uint8_t isc, uint8_t flags)
	159	{
f68ecdd4	160	QEMUS390FLICState *flic = s390_get_qemu_flic(fs);
6762808f	161	S390FLICStateClass *fsc = s390_get_flic_class(fs);
1622ffd5 YMZ	162	bool flag = flags & S390_ADAPTER_SUPPRESSIBLE;
	163	uint32_t io_int_word = (isc << 27) \| IO_INT_WORD_AI;
	164
	165	if (flag && (flic->nimm & AIS_MODE_MASK(isc))) {
	166	trace_qemu_s390_airq_suppressed(type, isc);
	167	return 0;
	168	}
	169
d8d7942d	170	fsc->inject_io(fs, 0, 0, 0, io_int_word);
1622ffd5 YMZ	171
	172	if (flag && (flic->simm & AIS_MODE_MASK(isc))) {
	173	flic->nimm \|= AIS_MODE_MASK(isc);
	174	trace_qemu_s390_suppress_airq(isc, "Single-Interruption Mode",
	175	"NO-Interruptions Mode");
	176	}
	177
	178	return 0;
	179	}
	180
b194e447 DH	181	static void qemu_s390_flic_notify(uint32_t type)
	182	{
	183	CPUState *cs;
	184
	185	/*
	186	* We have to make all CPUs see CPU_INTERRUPT_HARD, so they might
631b5966 DH	187	* consider it. We will kick all running CPUs and only relevant
631b5966 DH	188	* sleeping ones.
b194e447 DH	189	*/
b194e447 DH	190	CPU_FOREACH(cs) {
631b5966 DH	191	S390CPU *cpu = S390_CPU(cs);
	192
	193	cs->interrupt_request \|= CPU_INTERRUPT_HARD;
	194
	195	/* ignore CPUs that are not sleeping */
9d0306df VM	196	if (s390_cpu_get_state(cpu) != S390_CPU_STATE_OPERATING &&
9d0306df VM	197	s390_cpu_get_state(cpu) != S390_CPU_STATE_LOAD) {
631b5966 DH	198	continue;
	199	}
	200
	201	/* we always kick running CPUs for now, this is tricky */
	202	if (cs->halted) {
	203	/* don't check for subclasses, CPUs double check when waking up */
	204	if (type & FLIC_PENDING_SERVICE) {
	205	if (!(cpu->env.psw.mask & PSW_MASK_EXT)) {
	206	continue;
	207	}
	208	} else if (type & FLIC_PENDING_IO) {
	209	if (!(cpu->env.psw.mask & PSW_MASK_IO)) {
	210	continue;
	211	}
	212	} else if (type & FLIC_PENDING_MCHK_CR) {
	213	if (!(cpu->env.psw.mask & PSW_MASK_MCHECK)) {
	214	continue;
	215	}
	216	}
	217	}
b194e447 DH	218	cpu_interrupt(cs, CPU_INTERRUPT_HARD);
	219	}
	220	}
	221
	222	uint32_t qemu_s390_flic_dequeue_service(QEMUS390FLICState *flic)
	223	{
	224	uint32_t tmp;
	225
	226	g_assert(qemu_mutex_iothread_locked());
	227	g_assert(flic->pending & FLIC_PENDING_SERVICE);
	228	tmp = flic->service_param;
	229	flic->service_param = 0;
	230	flic->pending &= ~FLIC_PENDING_SERVICE;
	231
	232	return tmp;
	233	}
	234
	235	/* caller has to free the returned object */
	236	QEMUS390FlicIO qemu_s390_flic_dequeue_io(QEMUS390FLICState flic, uint64_t cr6)
	237	{
	238	QEMUS390FlicIO *io;
	239	uint8_t isc;
	240
	241	g_assert(qemu_mutex_iothread_locked());
	242	if (!(flic->pending & CR6_TO_PENDING_IO(cr6))) {
	243	return NULL;
	244	}
	245
	246	for (isc = 0; isc < 8; isc++) {
	247	if (QLIST_EMPTY(&flic->io[isc]) \|\| !(cr6 & ISC_TO_ISC_BITS(isc))) {
	248	continue;
	249	}
	250	io = QLIST_FIRST(&flic->io[isc]);
	251	QLIST_REMOVE(io, next);
	252
	253	/* update our indicator bit */
	254	if (QLIST_EMPTY(&flic->io[isc])) {
	255	flic->pending &= ~ISC_TO_PENDING_IO(isc);
	256	}
	257	return io;
	258	}
	259
	260	return NULL;
	261	}
	262
	263	void qemu_s390_flic_dequeue_crw_mchk(QEMUS390FLICState *flic)
	264	{
	265	g_assert(qemu_mutex_iothread_locked());
	266	g_assert(flic->pending & FLIC_PENDING_MCHK_CR);
	267	flic->pending &= ~FLIC_PENDING_MCHK_CR;
	268	}
	269
e6505d53 DH	270	static void qemu_s390_inject_service(S390FLICState *fs, uint32_t parm)
e6505d53 DH	271	{
f68ecdd4	272	QEMUS390FLICState *flic = s390_get_qemu_flic(fs);
e6505d53	273
b194e447 DH	274	g_assert(qemu_mutex_iothread_locked());
	275	/* multiplexing is good enough for sclp - kvm does it internally as well */
	276	flic->service_param \|= parm;
	277	flic->pending \|= FLIC_PENDING_SERVICE;
e6505d53	278
b194e447	279	qemu_s390_flic_notify(FLIC_PENDING_SERVICE);
e6505d53 DH	280	}
	281
	282	static void qemu_s390_inject_io(S390FLICState *fs, uint16_t subchannel_id,
	283	uint16_t subchannel_nr, uint32_t io_int_parm,
	284	uint32_t io_int_word)
	285	{
b194e447	286	const uint8_t isc = IO_INT_WORD_ISC(io_int_word);
f68ecdd4	287	QEMUS390FLICState *flic = s390_get_qemu_flic(fs);
b194e447	288	QEMUS390FlicIO *io;
e6505d53	289
b194e447 DH	290	g_assert(qemu_mutex_iothread_locked());
	291	io = g_new0(QEMUS390FlicIO, 1);
	292	io->id = subchannel_id;
	293	io->nr = subchannel_nr;
	294	io->parm = io_int_parm;
	295	io->word = io_int_word;
	296
	297	QLIST_INSERT_HEAD(&flic->io[isc], io, next);
	298	flic->pending \|= ISC_TO_PENDING_IO(isc);
	299
	300	qemu_s390_flic_notify(ISC_TO_PENDING_IO(isc));
e6505d53 DH	301	}
	302
	303	static void qemu_s390_inject_crw_mchk(S390FLICState *fs)
	304	{
f68ecdd4	305	QEMUS390FLICState *flic = s390_get_qemu_flic(fs);
b194e447 DH	306
	307	g_assert(qemu_mutex_iothread_locked());
	308	flic->pending \|= FLIC_PENDING_MCHK_CR;
	309
	310	qemu_s390_flic_notify(FLIC_PENDING_MCHK_CR);
	311	}
	312
	313	bool qemu_s390_flic_has_service(QEMUS390FLICState *flic)
	314	{
	315	/* called without lock via cc->has_work, will be validated under lock */
	316	return !!(flic->pending & FLIC_PENDING_SERVICE);
	317	}
	318
	319	bool qemu_s390_flic_has_io(QEMUS390FLICState *flic, uint64_t cr6)
	320	{
	321	/* called without lock via cc->has_work, will be validated under lock */
	322	return !!(flic->pending & CR6_TO_PENDING_IO(cr6));
	323	}
	324
	325	bool qemu_s390_flic_has_crw_mchk(QEMUS390FLICState *flic)
	326	{
	327	/* called without lock via cc->has_work, will be validated under lock */
	328	return !!(flic->pending & FLIC_PENDING_MCHK_CR);
	329	}
e6505d53	330
b194e447 DH	331	bool qemu_s390_flic_has_any(QEMUS390FLICState *flic)
	332	{
	333	g_assert(qemu_mutex_iothread_locked());
	334	return !!flic->pending;
e6505d53 DH	335	}
e6505d53 DH	336
6c1dd652 FL	337	static void qemu_s390_flic_reset(DeviceState *dev)
	338	{
	339	QEMUS390FLICState *flic = QEMU_S390_FLIC(dev);
b194e447 DH	340	QEMUS390FlicIO cur, next;
b194e447 DH	341	int isc;
6c1dd652	342
b194e447	343	g_assert(qemu_mutex_iothread_locked());
6c1dd652 FL	344	flic->simm = 0;
6c1dd652 FL	345	flic->nimm = 0;
b194e447 DH	346	flic->pending = 0;
	347
	348	/* remove all pending io interrupts */
	349	for (isc = 0; isc < 8; isc++) {
	350	QLIST_FOREACH_SAFE(cur, &flic->io[isc], next, next) {
	351	QLIST_REMOVE(cur, next);
	352	g_free(cur);
	353	}
	354	}
6c1dd652 FL	355	}
6c1dd652 FL	356
e7be8d49 YMZ	357	bool ais_needed(void *opaque)
	358	{
	359	S390FLICState *s = opaque;
	360
	361	return s->ais_supported;
	362	}
	363
	364	static const VMStateDescription qemu_s390_flic_vmstate = {
	365	.name = "qemu-s390-flic",
	366	.version_id = 1,
	367	.minimum_version_id = 1,
	368	.needed = ais_needed,
	369	.fields = (VMStateField[]) {
	370	VMSTATE_UINT8(simm, QEMUS390FLICState),
	371	VMSTATE_UINT8(nimm, QEMUS390FLICState),
	372	VMSTATE_END_OF_LIST()
	373	}
	374	};
	375
b194e447 DH	376	static void qemu_s390_flic_instance_init(Object *obj)
	377	{
	378	QEMUS390FLICState *flic = QEMU_S390_FLIC(obj);
	379	int isc;
	380
	381	for (isc = 0; isc < 8; isc++) {
	382	QLIST_INIT(&flic->io[isc]);
	383	}
	384	}
	385
03cf077a CH	386	static void qemu_s390_flic_class_init(ObjectClass oc, void data)
03cf077a CH	387	{
6c1dd652	388	DeviceClass *dc = DEVICE_CLASS(oc);
03cf077a CH	389	S390FLICStateClass *fsc = S390_FLIC_COMMON_CLASS(oc);
03cf077a CH	390
6c1dd652	391	dc->reset = qemu_s390_flic_reset;
e7be8d49	392	dc->vmsd = &qemu_s390_flic_vmstate;
03cf077a	393	fsc->register_io_adapter = qemu_s390_register_io_adapter;
d426d9fb CH	394	fsc->io_adapter_map = qemu_s390_io_adapter_map;
	395	fsc->add_adapter_routes = qemu_s390_add_adapter_routes;
	396	fsc->release_adapter_routes = qemu_s390_release_adapter_routes;
9eccb862	397	fsc->clear_io_irq = qemu_s390_clear_io_flic;
6c1dd652	398	fsc->modify_ais_mode = qemu_s390_modify_ais_mode;
1622ffd5	399	fsc->inject_airq = qemu_s390_inject_airq;
e6505d53 DH	400	fsc->inject_service = qemu_s390_inject_service;
	401	fsc->inject_io = qemu_s390_inject_io;
	402	fsc->inject_crw_mchk = qemu_s390_inject_crw_mchk;
03cf077a CH	403	}
03cf077a CH	404
e61cc6b5 HP	405	static Property s390_flic_common_properties[] = {
	406	DEFINE_PROP_UINT32("adapter_routes_max_batch", S390FLICState,
	407	adapter_routes_max_batch, ADAPTER_ROUTES_MAX_GSI),
	408	DEFINE_PROP_END_OF_LIST(),
	409	};
	410
	411	static void s390_flic_common_realize(DeviceState dev, Error *errp)
	412	{
6c1dd652 FL	413	S390FLICState *fs = S390_FLIC_COMMON(dev);
6c1dd652 FL	414	uint32_t max_batch = fs->adapter_routes_max_batch;
e61cc6b5 HP	415
e61cc6b5 HP	416	if (max_batch > ADAPTER_ROUTES_MAX_GSI) {
5cbab1bf HP	417	error_setg(errp, "flic property adapter_routes_max_batch too big"
5cbab1bf HP	418	" (%d > %d)", max_batch, ADAPTER_ROUTES_MAX_GSI);
3b00f702	419	return;
e61cc6b5	420	}
6c1dd652	421
3b00f702	422	fs->ais_supported = s390_has_feat(S390_FEAT_ADAPTER_INT_SUPPRESSION);
e61cc6b5 HP	423	}
	424
	425	static void s390_flic_class_init(ObjectClass oc, void data)
	426	{
	427	DeviceClass *dc = DEVICE_CLASS(oc);
	428
	429	dc->props = s390_flic_common_properties;
	430	dc->realize = s390_flic_common_realize;
	431	}
	432
7b35d0c4 CH	433	static const TypeInfo qemu_s390_flic_info = {
	434	.name = TYPE_QEMU_S390_FLIC,
	435	.parent = TYPE_S390_FLIC_COMMON,
	436	.instance_size = sizeof(QEMUS390FLICState),
b194e447	437	.instance_init = qemu_s390_flic_instance_init,
03cf077a	438	.class_init = qemu_s390_flic_class_init,
7b35d0c4	439	};
3a553fc6	440
e61cc6b5	441
7b35d0c4 CH	442	static const TypeInfo s390_flic_common_info = {
7b35d0c4 CH	443	.name = TYPE_S390_FLIC_COMMON,
3a553fc6	444	.parent = TYPE_SYS_BUS_DEVICE,
7b35d0c4	445	.instance_size = sizeof(S390FLICState),
e61cc6b5	446	.class_init = s390_flic_class_init,
7b35d0c4	447	.class_size = sizeof(S390FLICStateClass),
3a553fc6 JF	448	};
3a553fc6 JF	449
7b35d0c4	450	static void qemu_s390_flic_register_types(void)
3a553fc6	451	{
7b35d0c4 CH	452	type_register_static(&s390_flic_common_info);
7b35d0c4 CH	453	type_register_static(&qemu_s390_flic_info);
3a553fc6 JF	454	}
3a553fc6 JF	455
7b35d0c4	456	type_init(qemu_s390_flic_register_types)
517ff12c	457
457af626 HP	458	static bool adapter_info_so_needed(void *opaque)
	459	{
	460	return css_migration_enabled();
	461	}
	462
	463	const VMStateDescription vmstate_adapter_info_so = {
	464	.name = "s390_adapter_info/summary_offset",
	465	.version_id = 1,
	466	.minimum_version_id = 1,
	467	.needed = adapter_info_so_needed,
	468	.fields = (VMStateField[]) {
	469	VMSTATE_UINT32(summary_offset, AdapterInfo),
	470	VMSTATE_END_OF_LIST()
	471	}
	472	};
	473
517ff12c HP	474	const VMStateDescription vmstate_adapter_info = {
	475	.name = "s390_adapter_info",
	476	.version_id = 1,
	477	.minimum_version_id = 1,
	478	.fields = (VMStateField[]) {
	479	VMSTATE_UINT64(ind_offset, AdapterInfo),
	480	/*
	481	* We do not have to migrate neither the id nor the addresses.
	482	* The id is set by css_register_io_adapter and the addresses
	483	* are set based on the IndAddr objects after those get mapped.
	484	*/
	485	VMSTATE_END_OF_LIST()
	486	},
457af626 HP	487	.subsections = (const VMStateDescription * []) {
	488	&vmstate_adapter_info_so,
	489	NULL
	490	}
517ff12c HP	491	};
	492
	493	const VMStateDescription vmstate_adapter_routes = {
	494
	495	.name = "s390_adapter_routes",
	496	.version_id = 1,
	497	.minimum_version_id = 1,
	498	.fields = (VMStateField[]) {
	499	VMSTATE_STRUCT(adapter, AdapterRoutes, 1, vmstate_adapter_info,
	500	AdapterInfo),
	501	VMSTATE_END_OF_LIST()
	502	}
	503	};