[qemu.git] / softmmu_header.h

/*
 *  Software MMU support
 * 
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#if DATA_SIZE == 8
#define SUFFIX q
#define USUFFIX q
#define DATA_TYPE uint64_t
#elif DATA_SIZE == 4
#define SUFFIX l
#define USUFFIX l
#define DATA_TYPE uint32_t
#elif DATA_SIZE == 2
#define SUFFIX w
#define USUFFIX uw
#define DATA_TYPE uint16_t
#define DATA_STYPE int16_t
#elif DATA_SIZE == 1
#define SUFFIX b
#define USUFFIX ub
#define DATA_TYPE uint8_t
#define DATA_STYPE int8_t
#else
#error unsupported data size
#endif

#if ACCESS_TYPE == 0

#define CPU_MEM_INDEX 0
#define MMUSUFFIX _mmu

#elif ACCESS_TYPE == 1

#define CPU_MEM_INDEX 1
#define MMUSUFFIX _mmu

#elif ACCESS_TYPE == 2

#ifdef TARGET_I386
#define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
#elif defined (TARGET_PPC)
#define CPU_MEM_INDEX (msr_pr)
#elif defined (TARGET_MIPS)
#define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
#elif defined (TARGET_SPARC)
#define CPU_MEM_INDEX ((env->psrs) == 0)
#elif defined (TARGET_ARM)
#define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
#else
#error unsupported CPU
#endif
#define MMUSUFFIX _mmu

#elif ACCESS_TYPE == 3

#ifdef TARGET_I386
#define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
#elif defined (TARGET_PPC)
#define CPU_MEM_INDEX (msr_pr)
#elif defined (TARGET_MIPS)
#define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
#elif defined (TARGET_SPARC)
#define CPU_MEM_INDEX ((env->psrs) == 0)
#elif defined (TARGET_ARM)
#define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
#else
#error unsupported CPU
#endif
#define MMUSUFFIX _cmmu

#else
#error invalid ACCESS_TYPE
#endif

#if DATA_SIZE == 8
#define RES_TYPE uint64_t
#else
#define RES_TYPE int
#endif

#if ACCESS_TYPE == 3
#define ADDR_READ addr_code
#else
#define ADDR_READ addr_read
#endif

DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                         int is_user);
void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int is_user);

#if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
    (ACCESS_TYPE <= 1) && defined(ASM_SOFTMMU)

#define CPU_TLB_ENTRY_BITS 4

static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
{
    int res;

    asm volatile ("movl %1, %%edx\n"
                  "movl %1, %%eax\n"
                  "shrl %3, %%edx\n"
                  "andl %4, %%eax\n"
                  "andl %2, %%edx\n"
                  "leal %5(%%edx, %%ebp), %%edx\n"
                  "cmpl (%%edx), %%eax\n"
                  "movl %1, %%eax\n"
                  "je 1f\n"
                  "pushl %6\n"
                  "call %7\n"
                  "popl %%edx\n"
                  "movl %%eax, %0\n"
                  "jmp 2f\n"
                  "1:\n"
                  "addl 12(%%edx), %%eax\n"
#if DATA_SIZE == 1
                  "movzbl (%%eax), %0\n"
#elif DATA_SIZE == 2
                  "movzwl (%%eax), %0\n"
#elif DATA_SIZE == 4
                  "movl (%%eax), %0\n"
#else
#error unsupported size
#endif
                  "2:\n"
                  : "=r" (res)
                  : "r" (ptr), 
                  "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS), 
                  "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS), 
                  "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
                  "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_read)),
                  "i" (CPU_MEM_INDEX),
                  "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
                  : "%eax", "%ecx", "%edx", "memory", "cc");
    return res;
}

#if DATA_SIZE <= 2
static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
{
    int res;

    asm volatile ("movl %1, %%edx\n"
                  "movl %1, %%eax\n"
                  "shrl %3, %%edx\n"
                  "andl %4, %%eax\n"
                  "andl %2, %%edx\n"
                  "leal %5(%%edx, %%ebp), %%edx\n"
                  "cmpl (%%edx), %%eax\n"
                  "movl %1, %%eax\n"
                  "je 1f\n"
                  "pushl %6\n"
                  "call %7\n"
                  "popl %%edx\n"
#if DATA_SIZE == 1
                  "movsbl %%al, %0\n"
#elif DATA_SIZE == 2
                  "movswl %%ax, %0\n"
#else
#error unsupported size
#endif
                  "jmp 2f\n"
                  "1:\n"
                  "addl 12(%%edx), %%eax\n"
#if DATA_SIZE == 1
                  "movsbl (%%eax), %0\n"
#elif DATA_SIZE == 2
                  "movswl (%%eax), %0\n"
#else
#error unsupported size
#endif
                  "2:\n"
                  : "=r" (res)
                  : "r" (ptr), 
                  "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS), 
                  "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS), 
                  "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
                  "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_read)),
                  "i" (CPU_MEM_INDEX),
                  "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
                  : "%eax", "%ecx", "%edx", "memory", "cc");
    return res;
}
#endif

static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
{
    asm volatile ("movl %0, %%edx\n"
                  "movl %0, %%eax\n"
                  "shrl %3, %%edx\n"
                  "andl %4, %%eax\n"
                  "andl %2, %%edx\n"
                  "leal %5(%%edx, %%ebp), %%edx\n"
                  "cmpl (%%edx), %%eax\n"
                  "movl %0, %%eax\n"
                  "je 1f\n"
#if DATA_SIZE == 1
                  "movzbl %b1, %%edx\n"
#elif DATA_SIZE == 2
                  "movzwl %w1, %%edx\n"
#elif DATA_SIZE == 4
                  "movl %1, %%edx\n"
#else
#error unsupported size
#endif
                  "pushl %6\n"
                  "call %7\n"
                  "popl %%eax\n"
                  "jmp 2f\n"
                  "1:\n"
                  "addl 8(%%edx), %%eax\n"
#if DATA_SIZE == 1
                  "movb %b1, (%%eax)\n"
#elif DATA_SIZE == 2
                  "movw %w1, (%%eax)\n"
#elif DATA_SIZE == 4
                  "movl %1, (%%eax)\n"
#else
#error unsupported size
#endif
                  "2:\n"
                  : 
                  : "r" (ptr), 
/* NOTE: 'q' would be needed as constraint, but we could not use it
   with T1 ! */
                  "r" (v), 
                  "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS), 
                  "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS), 
                  "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
                  "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_write)),
                  "i" (CPU_MEM_INDEX),
                  "m" (*(uint8_t *)&glue(glue(__st, SUFFIX), MMUSUFFIX))
                  : "%eax", "%ecx", "%edx", "memory", "cc");
}

#else

/* generic load/store macros */

static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
{
    int index;
    RES_TYPE res;
    target_ulong addr;
    unsigned long physaddr;
    int is_user;

    addr = ptr;
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    is_user = CPU_MEM_INDEX;
    if (__builtin_expect(env->tlb_table[is_user][index].ADDR_READ != 
                         (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
        res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
    } else {
        physaddr = addr + env->tlb_table[is_user][index].addend;
        res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
    }
    return res;
}

#if DATA_SIZE <= 2
static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
{
    int res, index;
    target_ulong addr;
    unsigned long physaddr;
    int is_user;

    addr = ptr;
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    is_user = CPU_MEM_INDEX;
    if (__builtin_expect(env->tlb_table[is_user][index].ADDR_READ != 
                         (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
        res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
    } else {
        physaddr = addr + env->tlb_table[is_user][index].addend;
        res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
    }
    return res;
}
#endif

#if ACCESS_TYPE != 3

/* generic store macro */

static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
{
    int index;
    target_ulong addr;
    unsigned long physaddr;
    int is_user;

    addr = ptr;
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    is_user = CPU_MEM_INDEX;
    if (__builtin_expect(env->tlb_table[is_user][index].addr_write != 
                         (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
        glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, is_user);
    } else {
        physaddr = addr + env->tlb_table[is_user][index].addend;
        glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
    }
}

#endif /* ACCESS_TYPE != 3 */

#endif /* !asm */

#if ACCESS_TYPE != 3

#if DATA_SIZE == 8
static inline float64 glue(ldfq, MEMSUFFIX)(target_ulong ptr)
{
    union {
        float64 d;
        uint64_t i;
    } u;
    u.i = glue(ldq, MEMSUFFIX)(ptr);
    return u.d;
}

static inline void glue(stfq, MEMSUFFIX)(target_ulong ptr, float64 v)
{
    union {
        float64 d;
        uint64_t i;
    } u;
    u.d = v;
    glue(stq, MEMSUFFIX)(ptr, u.i);
}
#endif /* DATA_SIZE == 8 */

#if DATA_SIZE == 4
static inline float32 glue(ldfl, MEMSUFFIX)(target_ulong ptr)
{
    union {
        float32 f;
        uint32_t i;
    } u;
    u.i = glue(ldl, MEMSUFFIX)(ptr);
    return u.f;
}

static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float32 v)
{
    union {
        float32 f;
        uint32_t i;
    } u;
    u.f = v;
    glue(stl, MEMSUFFIX)(ptr, u.i);
}
#endif /* DATA_SIZE == 4 */

#endif /* ACCESS_TYPE != 3 */

#undef RES_TYPE
#undef DATA_TYPE
#undef DATA_STYPE
#undef SUFFIX
#undef USUFFIX
#undef DATA_SIZE
#undef CPU_MEM_INDEX
#undef MMUSUFFIX
#undef ADDR_READ
Commit	Line	Data
b92e5a22 FB	1	/*
	2	* Software MMU support
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#if DATA_SIZE == 8
	21	#define SUFFIX q
61382a50	22	#define USUFFIX q
b92e5a22 FB	23	#define DATA_TYPE uint64_t
	24	#elif DATA_SIZE == 4
	25	#define SUFFIX l
61382a50	26	#define USUFFIX l
b92e5a22 FB	27	#define DATA_TYPE uint32_t
	28	#elif DATA_SIZE == 2
	29	#define SUFFIX w
61382a50	30	#define USUFFIX uw
b92e5a22 FB	31	#define DATA_TYPE uint16_t
	32	#define DATA_STYPE int16_t
	33	#elif DATA_SIZE == 1
	34	#define SUFFIX b
61382a50	35	#define USUFFIX ub
b92e5a22 FB	36	#define DATA_TYPE uint8_t
	37	#define DATA_STYPE int8_t
	38	#else
	39	#error unsupported data size
	40	#endif
	41
61382a50 FB	42	#if ACCESS_TYPE == 0
	43
	44	#define CPU_MEM_INDEX 0
	45	#define MMUSUFFIX _mmu
	46
	47	#elif ACCESS_TYPE == 1
	48
	49	#define CPU_MEM_INDEX 1
	50	#define MMUSUFFIX _mmu
	51
	52	#elif ACCESS_TYPE == 2
	53
2d603d22	54	#ifdef TARGET_I386
61382a50	55	#define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
2d603d22 FB	56	#elif defined (TARGET_PPC)
2d603d22 FB	57	#define CPU_MEM_INDEX (msr_pr)
6af0bf9c FB	58	#elif defined (TARGET_MIPS)
6af0bf9c FB	59	#define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
e95c8d51 FB	60	#elif defined (TARGET_SPARC)
e95c8d51 FB	61	#define CPU_MEM_INDEX ((env->psrs) == 0)
b5ff1b31 FB	62	#elif defined (TARGET_ARM)
	63	#define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
	64	#else
	65	#error unsupported CPU
2d603d22	66	#endif
61382a50 FB	67	#define MMUSUFFIX _mmu
	68
	69	#elif ACCESS_TYPE == 3
	70
2d603d22	71	#ifdef TARGET_I386
61382a50	72	#define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
2d603d22 FB	73	#elif defined (TARGET_PPC)
2d603d22 FB	74	#define CPU_MEM_INDEX (msr_pr)
6af0bf9c FB	75	#elif defined (TARGET_MIPS)
6af0bf9c FB	76	#define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
e95c8d51 FB	77	#elif defined (TARGET_SPARC)
e95c8d51 FB	78	#define CPU_MEM_INDEX ((env->psrs) == 0)
b5ff1b31 FB	79	#elif defined (TARGET_ARM)
	80	#define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
	81	#else
	82	#error unsupported CPU
2d603d22	83	#endif
61382a50 FB	84	#define MMUSUFFIX _cmmu
61382a50 FB	85
b92e5a22	86	#else
61382a50	87	#error invalid ACCESS_TYPE
b92e5a22 FB	88	#endif
	89
	90	#if DATA_SIZE == 8
	91	#define RES_TYPE uint64_t
	92	#else
	93	#define RES_TYPE int
	94	#endif
	95
84b7b8e7 FB	96	#if ACCESS_TYPE == 3
	97	#define ADDR_READ addr_code
	98	#else
	99	#define ADDR_READ addr_read
	100	#endif
b92e5a22	101
c27004ec	102	DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
61382a50	103	int is_user);
c27004ec	104	void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int is_user);
b92e5a22	105
c27004ec FB	106	#if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
c27004ec FB	107	(ACCESS_TYPE <= 1) && defined(ASM_SOFTMMU)
e16c53fa	108
84b7b8e7 FB	109	#define CPU_TLB_ENTRY_BITS 4
84b7b8e7 FB	110
c27004ec	111	static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
e16c53fa FB	112	{
	113	int res;
	114
	115	asm volatile ("movl %1, %%edx\n"
	116	"movl %1, %%eax\n"
	117	"shrl %3, %%edx\n"
	118	"andl %4, %%eax\n"
	119	"andl %2, %%edx\n"
	120	"leal %5(%%edx, %%ebp), %%edx\n"
	121	"cmpl (%%edx), %%eax\n"
	122	"movl %1, %%eax\n"
	123	"je 1f\n"
	124	"pushl %6\n"
	125	"call %7\n"
	126	"popl %%edx\n"
	127	"movl %%eax, %0\n"
	128	"jmp 2f\n"
	129	"1:\n"
84b7b8e7	130	"addl 12(%%edx), %%eax\n"
e16c53fa FB	131	#if DATA_SIZE == 1
	132	"movzbl (%%eax), %0\n"
	133	#elif DATA_SIZE == 2
	134	"movzwl (%%eax), %0\n"
	135	#elif DATA_SIZE == 4
	136	"movl (%%eax), %0\n"
	137	#else
	138	#error unsupported size
	139	#endif
	140	"2:\n"
	141	: "=r" (res)
	142	: "r" (ptr),
84b7b8e7 FB	143	"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
84b7b8e7 FB	144	"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
e16c53fa	145	"i" (TARGET_PAGE_MASK \| (DATA_SIZE - 1)),
84b7b8e7	146	"m" ((uint32_t )offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_read)),
e16c53fa FB	147	"i" (CPU_MEM_INDEX),
	148	"m" ((uint8_t )&glue(glue(__ld, SUFFIX), MMUSUFFIX))
	149	: "%eax", "%ecx", "%edx", "memory", "cc");
	150	return res;
	151	}
	152
	153	#if DATA_SIZE <= 2
c27004ec	154	static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
e16c53fa FB	155	{
	156	int res;
	157
	158	asm volatile ("movl %1, %%edx\n"
	159	"movl %1, %%eax\n"
	160	"shrl %3, %%edx\n"
	161	"andl %4, %%eax\n"
	162	"andl %2, %%edx\n"
	163	"leal %5(%%edx, %%ebp), %%edx\n"
	164	"cmpl (%%edx), %%eax\n"
	165	"movl %1, %%eax\n"
	166	"je 1f\n"
	167	"pushl %6\n"
	168	"call %7\n"
	169	"popl %%edx\n"
	170	#if DATA_SIZE == 1
	171	"movsbl %%al, %0\n"
	172	#elif DATA_SIZE == 2
	173	"movswl %%ax, %0\n"
	174	#else
	175	#error unsupported size
	176	#endif
	177	"jmp 2f\n"
	178	"1:\n"
84b7b8e7	179	"addl 12(%%edx), %%eax\n"
e16c53fa FB	180	#if DATA_SIZE == 1
	181	"movsbl (%%eax), %0\n"
	182	#elif DATA_SIZE == 2
	183	"movswl (%%eax), %0\n"
	184	#else
	185	#error unsupported size
	186	#endif
	187	"2:\n"
	188	: "=r" (res)
	189	: "r" (ptr),
84b7b8e7 FB	190	"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
84b7b8e7 FB	191	"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
e16c53fa	192	"i" (TARGET_PAGE_MASK \| (DATA_SIZE - 1)),
84b7b8e7	193	"m" ((uint32_t )offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_read)),
e16c53fa FB	194	"i" (CPU_MEM_INDEX),
	195	"m" ((uint8_t )&glue(glue(__ld, SUFFIX), MMUSUFFIX))
	196	: "%eax", "%ecx", "%edx", "memory", "cc");
	197	return res;
	198	}
	199	#endif
	200
c27004ec	201	static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
e16c53fa FB	202	{
	203	asm volatile ("movl %0, %%edx\n"
	204	"movl %0, %%eax\n"
	205	"shrl %3, %%edx\n"
	206	"andl %4, %%eax\n"
	207	"andl %2, %%edx\n"
	208	"leal %5(%%edx, %%ebp), %%edx\n"
	209	"cmpl (%%edx), %%eax\n"
	210	"movl %0, %%eax\n"
	211	"je 1f\n"
	212	#if DATA_SIZE == 1
	213	"movzbl %b1, %%edx\n"
	214	#elif DATA_SIZE == 2
	215	"movzwl %w1, %%edx\n"
	216	#elif DATA_SIZE == 4
	217	"movl %1, %%edx\n"
	218	#else
	219	#error unsupported size
	220	#endif
	221	"pushl %6\n"
	222	"call %7\n"
	223	"popl %%eax\n"
	224	"jmp 2f\n"
	225	"1:\n"
84b7b8e7	226	"addl 8(%%edx), %%eax\n"
e16c53fa FB	227	#if DATA_SIZE == 1
	228	"movb %b1, (%%eax)\n"
	229	#elif DATA_SIZE == 2
	230	"movw %w1, (%%eax)\n"
	231	#elif DATA_SIZE == 4
	232	"movl %1, (%%eax)\n"
	233	#else
	234	#error unsupported size
	235	#endif
	236	"2:\n"
	237	:
	238	: "r" (ptr),
	239	/* NOTE: 'q' would be needed as constraint, but we could not use it
	240	with T1 ! */
	241	"r" (v),
84b7b8e7 FB	242	"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
84b7b8e7 FB	243	"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
e16c53fa	244	"i" (TARGET_PAGE_MASK \| (DATA_SIZE - 1)),
84b7b8e7	245	"m" ((uint32_t )offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_write)),
e16c53fa FB	246	"i" (CPU_MEM_INDEX),
	247	"m" ((uint8_t )&glue(glue(__st, SUFFIX), MMUSUFFIX))
	248	: "%eax", "%ecx", "%edx", "memory", "cc");
	249	}
	250
	251	#else
	252
	253	/* generic load/store macros */
	254
c27004ec	255	static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
b92e5a22 FB	256	{
	257	int index;
	258	RES_TYPE res;
c27004ec FB	259	target_ulong addr;
c27004ec FB	260	unsigned long physaddr;
61382a50 FB	261	int is_user;
61382a50 FB	262
c27004ec	263	addr = ptr;
b92e5a22	264	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
61382a50	265	is_user = CPU_MEM_INDEX;
84b7b8e7	266	if (__builtin_expect(env->tlb_table[is_user][index].ADDR_READ !=
b92e5a22	267	(addr & (TARGET_PAGE_MASK \| (DATA_SIZE - 1))), 0)) {
61382a50	268	res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
b92e5a22	269	} else {
84b7b8e7	270	physaddr = addr + env->tlb_table[is_user][index].addend;
61382a50	271	res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
b92e5a22 FB	272	}
	273	return res;
	274	}
	275
	276	#if DATA_SIZE <= 2
c27004ec	277	static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
b92e5a22 FB	278	{
b92e5a22 FB	279	int res, index;
c27004ec FB	280	target_ulong addr;
c27004ec FB	281	unsigned long physaddr;
61382a50 FB	282	int is_user;
61382a50 FB	283
c27004ec	284	addr = ptr;
b92e5a22	285	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
61382a50	286	is_user = CPU_MEM_INDEX;
84b7b8e7	287	if (__builtin_expect(env->tlb_table[is_user][index].ADDR_READ !=
b92e5a22	288	(addr & (TARGET_PAGE_MASK \| (DATA_SIZE - 1))), 0)) {
61382a50	289	res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
b92e5a22	290	} else {
84b7b8e7	291	physaddr = addr + env->tlb_table[is_user][index].addend;
b92e5a22 FB	292	res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
	293	}
	294	return res;
	295	}
	296	#endif
	297
84b7b8e7 FB	298	#if ACCESS_TYPE != 3
84b7b8e7 FB	299
e16c53fa FB	300	/* generic store macro */
e16c53fa FB	301
c27004ec	302	static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
b92e5a22 FB	303	{
b92e5a22 FB	304	int index;
c27004ec FB	305	target_ulong addr;
c27004ec FB	306	unsigned long physaddr;
61382a50 FB	307	int is_user;
61382a50 FB	308
c27004ec	309	addr = ptr;
b92e5a22	310	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
61382a50	311	is_user = CPU_MEM_INDEX;
84b7b8e7	312	if (__builtin_expect(env->tlb_table[is_user][index].addr_write !=
b92e5a22	313	(addr & (TARGET_PAGE_MASK \| (DATA_SIZE - 1))), 0)) {
61382a50	314	glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, is_user);
b92e5a22	315	} else {
84b7b8e7	316	physaddr = addr + env->tlb_table[is_user][index].addend;
b92e5a22 FB	317	glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
	318	}
	319	}
	320
84b7b8e7 FB	321	#endif /* ACCESS_TYPE != 3 */
	322
	323	#endif /* !asm */
	324
	325	#if ACCESS_TYPE != 3
e16c53fa	326
2d603d22	327	#if DATA_SIZE == 8
3f87bf69	328	static inline float64 glue(ldfq, MEMSUFFIX)(target_ulong ptr)
2d603d22 FB	329	{
2d603d22 FB	330	union {
3f87bf69	331	float64 d;
2d603d22 FB	332	uint64_t i;
	333	} u;
	334	u.i = glue(ldq, MEMSUFFIX)(ptr);
	335	return u.d;
	336	}
	337
3f87bf69	338	static inline void glue(stfq, MEMSUFFIX)(target_ulong ptr, float64 v)
2d603d22 FB	339	{
2d603d22 FB	340	union {
3f87bf69	341	float64 d;
2d603d22 FB	342	uint64_t i;
	343	} u;
	344	u.d = v;
	345	glue(stq, MEMSUFFIX)(ptr, u.i);
	346	}
	347	#endif /* DATA_SIZE == 8 */
	348
	349	#if DATA_SIZE == 4
3f87bf69	350	static inline float32 glue(ldfl, MEMSUFFIX)(target_ulong ptr)
2d603d22 FB	351	{
2d603d22 FB	352	union {
3f87bf69	353	float32 f;
2d603d22 FB	354	uint32_t i;
	355	} u;
	356	u.i = glue(ldl, MEMSUFFIX)(ptr);
	357	return u.f;
	358	}
	359
3f87bf69	360	static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float32 v)
2d603d22 FB	361	{
2d603d22 FB	362	union {
3f87bf69	363	float32 f;
2d603d22 FB	364	uint32_t i;
	365	} u;
	366	u.f = v;
	367	glue(stl, MEMSUFFIX)(ptr, u.i);
	368	}
	369	#endif /* DATA_SIZE == 4 */
	370
84b7b8e7 FB	371	#endif /* ACCESS_TYPE != 3 */
84b7b8e7 FB	372
b92e5a22 FB	373	#undef RES_TYPE
	374	#undef DATA_TYPE
	375	#undef DATA_STYPE
	376	#undef SUFFIX
61382a50	377	#undef USUFFIX
b92e5a22	378	#undef DATA_SIZE
61382a50 FB	379	#undef CPU_MEM_INDEX
61382a50 FB	380	#undef MMUSUFFIX
84b7b8e7	381	#undef ADDR_READ