[qemu.git] / hw / intc / openpic_kvm.c

/*
 * KVM in-kernel OpenPIC
 *
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include <sys/ioctl.h>
#include "exec/address-spaces.h"
#include "hw/hw.h"
#include "hw/ppc/openpic.h"
#include "hw/pci/msi.h"
#include "hw/sysbus.h"
#include "sysemu/kvm.h"
#include "qemu/log.h"

#define GCR_RESET        0x80000000

#define KVM_OPENPIC(obj) \
    OBJECT_CHECK(KVMOpenPICState, (obj), TYPE_KVM_OPENPIC)

typedef struct KVMOpenPICState {
    /*< private >*/
    SysBusDevice parent_obj;
    /*< public >*/

    MemoryRegion mem;
    MemoryListener mem_listener;
    uint32_t fd;
    uint32_t model;
} KVMOpenPICState;

static void kvm_openpic_set_irq(void *opaque, int n_IRQ, int level)
{
    kvm_set_irq(kvm_state, n_IRQ, level);
}

static void kvm_openpic_write(void *opaque, hwaddr addr, uint64_t val,
                              unsigned size)
{
    KVMOpenPICState *opp = opaque;
    struct kvm_device_attr attr;
    uint32_t val32 = val;
    int ret;

    attr.group = KVM_DEV_MPIC_GRP_REGISTER;
    attr.attr = addr;
    attr.addr = (uint64_t)(unsigned long)&val32;

    ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr);
    if (ret < 0) {
        qemu_log_mask(LOG_UNIMP, "%s: %s %" PRIx64 "\n", __func__,
                      strerror(errno), attr.attr);
    }
}

static void kvm_openpic_reset(DeviceState *d)
{
    KVMOpenPICState *opp = KVM_OPENPIC(d);

    /* Trigger the GCR.RESET bit to reset the PIC */
    kvm_openpic_write(opp, 0x1020, GCR_RESET, sizeof(uint32_t));
}

static uint64_t kvm_openpic_read(void *opaque, hwaddr addr, unsigned size)
{
    KVMOpenPICState *opp = opaque;
    struct kvm_device_attr attr;
    uint32_t val = 0xdeadbeef;
    int ret;

    attr.group = KVM_DEV_MPIC_GRP_REGISTER;
    attr.attr = addr;
    attr.addr = (uint64_t)(unsigned long)&val;

    ret = ioctl(opp->fd, KVM_GET_DEVICE_ATTR, &attr);
    if (ret < 0) {
        qemu_log_mask(LOG_UNIMP, "%s: %s %" PRIx64 "\n", __func__,
                      strerror(errno), attr.attr);
        return 0;
    }

    return val;
}

static const MemoryRegionOps kvm_openpic_mem_ops = {
    .write = kvm_openpic_write,
    .read  = kvm_openpic_read,
    .endianness = DEVICE_BIG_ENDIAN,
    .impl = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

static void kvm_openpic_region_add(MemoryListener *listener,
                                   MemoryRegionSection *section)
{
    KVMOpenPICState *opp = container_of(listener, KVMOpenPICState,
                                        mem_listener);
    struct kvm_device_attr attr;
    uint64_t reg_base;
    int ret;

    if (section->address_space != &address_space_memory) {
        abort();
    }

    /* Ignore events on regions that are not us */
    if (section->mr != &opp->mem) {
        return;
    }

    reg_base = section->offset_within_address_space;

    attr.group = KVM_DEV_MPIC_GRP_MISC;
    attr.attr = KVM_DEV_MPIC_BASE_ADDR;
    attr.addr = (uint64_t)(unsigned long)&reg_base;

    ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr);
    if (ret < 0) {
        fprintf(stderr, "%s: %s %" PRIx64 "\n", __func__,
                strerror(errno), reg_base);
    }
}

static void kvm_openpic_region_del(MemoryListener *listener,
                                   MemoryRegionSection *section)
{
    KVMOpenPICState *opp = container_of(listener, KVMOpenPICState,
                                        mem_listener);
    struct kvm_device_attr attr;
    uint64_t reg_base = 0;
    int ret;

    /* Ignore events on regions that are not us */
    if (section->mr != &opp->mem) {
        return;
    }

    attr.group = KVM_DEV_MPIC_GRP_MISC;
    attr.attr = KVM_DEV_MPIC_BASE_ADDR;
    attr.addr = (uint64_t)(unsigned long)&reg_base;

    ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr);
    if (ret < 0) {
        fprintf(stderr, "%s: %s %" PRIx64 "\n", __func__,
                strerror(errno), reg_base);
    }
}

static void kvm_openpic_init(Object *obj)
{
    KVMOpenPICState *opp = KVM_OPENPIC(obj);

    memory_region_init_io(&opp->mem, OBJECT(opp), &kvm_openpic_mem_ops, opp,
                          "kvm-openpic", 0x40000);
}

static void kvm_openpic_realize(DeviceState *dev, Error **errp)
{
    SysBusDevice *d = SYS_BUS_DEVICE(dev);
    KVMOpenPICState *opp = KVM_OPENPIC(dev);
    KVMState *s = kvm_state;
    int kvm_openpic_model;
    struct kvm_create_device cd = {0};
    int ret, i;

    if (!kvm_check_extension(s, KVM_CAP_DEVICE_CTRL)) {
        error_setg(errp, "Kernel is lacking Device Control API");
        return;
    }

    switch (opp->model) {
    case OPENPIC_MODEL_FSL_MPIC_20:
        kvm_openpic_model = KVM_DEV_TYPE_FSL_MPIC_20;
        break;

    case OPENPIC_MODEL_FSL_MPIC_42:
        kvm_openpic_model = KVM_DEV_TYPE_FSL_MPIC_42;
        break;

    default:
        error_setg(errp, "Unsupported OpenPIC model %" PRIu32, opp->model);
        return;
    }

    cd.type = kvm_openpic_model;
    ret = kvm_vm_ioctl(s, KVM_CREATE_DEVICE, &cd);
    if (ret < 0) {
        error_setg(errp, "Can't create device %d: %s",
                   cd.type, strerror(errno));
        return;
    }
    opp->fd = cd.fd;

    sysbus_init_mmio(d, &opp->mem);
    qdev_init_gpio_in(dev, kvm_openpic_set_irq, OPENPIC_MAX_IRQ);

    opp->mem_listener.region_add = kvm_openpic_region_add;
    opp->mem_listener.region_del = kvm_openpic_region_del;
    memory_listener_register(&opp->mem_listener, &address_space_memory);

    /* indicate pic capabilities */
    msi_supported = true;
    kvm_kernel_irqchip = true;
    kvm_async_interrupts_allowed = true;

    /* set up irq routing */
    kvm_init_irq_routing(kvm_state);
    for (i = 0; i < 256; ++i) {
        kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
    }

    kvm_irqfds_allowed = true;
    kvm_msi_via_irqfd_allowed = true;
    kvm_gsi_routing_allowed = true;

    kvm_irqchip_commit_routes(s);
}

int kvm_openpic_connect_vcpu(DeviceState *d, CPUState *cs)
{
    KVMOpenPICState *opp = KVM_OPENPIC(d);

    return kvm_vcpu_enable_cap(cs, KVM_CAP_IRQ_MPIC, 0, opp->fd,
                               kvm_arch_vcpu_id(cs));
}

static Property kvm_openpic_properties[] = {
    DEFINE_PROP_UINT32("model", KVMOpenPICState, model,
                       OPENPIC_MODEL_FSL_MPIC_20),
    DEFINE_PROP_END_OF_LIST(),
};

static void kvm_openpic_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->realize = kvm_openpic_realize;
    dc->props = kvm_openpic_properties;
    dc->reset = kvm_openpic_reset;
}

static const TypeInfo kvm_openpic_info = {
    .name          = TYPE_KVM_OPENPIC,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(KVMOpenPICState),
    .instance_init = kvm_openpic_init,
    .class_init    = kvm_openpic_class_init,
};

static void kvm_openpic_register_types(void)
{
    type_register_static(&kvm_openpic_info);
}

type_init(kvm_openpic_register_types)
Commit	Line	Data
d85937e6 SW	1	/*
	2	* KVM in-kernel OpenPIC
	3	*
	4	* Copyright 2013 Freescale Semiconductor, Inc.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	#include <sys/ioctl.h>
	26	#include "exec/address-spaces.h"
	27	#include "hw/hw.h"
	28	#include "hw/ppc/openpic.h"
	29	#include "hw/pci/msi.h"
	30	#include "hw/sysbus.h"
	31	#include "sysemu/kvm.h"
	32	#include "qemu/log.h"
	33
af354f19 AG	34	#define GCR_RESET 0x80000000
af354f19 AG	35
dd49c038 AF	36	#define KVM_OPENPIC(obj) \
	37	OBJECT_CHECK(KVMOpenPICState, (obj), TYPE_KVM_OPENPIC)
	38
d85937e6	39	typedef struct KVMOpenPICState {
dd49c038 AF	40	/< private >/
	41	SysBusDevice parent_obj;
	42	/< public >/
	43
d85937e6 SW	44	MemoryRegion mem;
	45	MemoryListener mem_listener;
	46	uint32_t fd;
	47	uint32_t model;
	48	} KVMOpenPICState;
	49
	50	static void kvm_openpic_set_irq(void *opaque, int n_IRQ, int level)
	51	{
	52	kvm_set_irq(kvm_state, n_IRQ, level);
	53	}
	54
d85937e6 SW	55	static void kvm_openpic_write(void *opaque, hwaddr addr, uint64_t val,
	56	unsigned size)
	57	{
	58	KVMOpenPICState *opp = opaque;
	59	struct kvm_device_attr attr;
	60	uint32_t val32 = val;
	61	int ret;
	62
	63	attr.group = KVM_DEV_MPIC_GRP_REGISTER;
	64	attr.attr = addr;
	65	attr.addr = (uint64_t)(unsigned long)&val32;
	66
	67	ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr);
	68	if (ret < 0) {
	69	qemu_log_mask(LOG_UNIMP, "%s: %s %" PRIx64 "\n", __func__,
	70	strerror(errno), attr.attr);
	71	}
	72	}
	73
af354f19 AG	74	static void kvm_openpic_reset(DeviceState *d)
	75	{
	76	KVMOpenPICState *opp = KVM_OPENPIC(d);
	77
	78	/* Trigger the GCR.RESET bit to reset the PIC */
	79	kvm_openpic_write(opp, 0x1020, GCR_RESET, sizeof(uint32_t));
	80	}
	81
d85937e6 SW	82	static uint64_t kvm_openpic_read(void *opaque, hwaddr addr, unsigned size)
	83	{
	84	KVMOpenPICState *opp = opaque;
	85	struct kvm_device_attr attr;
	86	uint32_t val = 0xdeadbeef;
	87	int ret;
	88
	89	attr.group = KVM_DEV_MPIC_GRP_REGISTER;
	90	attr.attr = addr;
	91	attr.addr = (uint64_t)(unsigned long)&val;
	92
	93	ret = ioctl(opp->fd, KVM_GET_DEVICE_ATTR, &attr);
	94	if (ret < 0) {
	95	qemu_log_mask(LOG_UNIMP, "%s: %s %" PRIx64 "\n", __func__,
	96	strerror(errno), attr.attr);
	97	return 0;
	98	}
	99
	100	return val;
	101	}
	102
	103	static const MemoryRegionOps kvm_openpic_mem_ops = {
	104	.write = kvm_openpic_write,
	105	.read = kvm_openpic_read,
	106	.endianness = DEVICE_BIG_ENDIAN,
	107	.impl = {
	108	.min_access_size = 4,
	109	.max_access_size = 4,
	110	},
	111	};
	112
	113	static void kvm_openpic_region_add(MemoryListener *listener,
	114	MemoryRegionSection *section)
	115	{
	116	KVMOpenPICState *opp = container_of(listener, KVMOpenPICState,
	117	mem_listener);
	118	struct kvm_device_attr attr;
	119	uint64_t reg_base;
	120	int ret;
	121
	122	if (section->address_space != &address_space_memory) {
	123	abort();
	124	}
	125
87d8354d AG	126	/* Ignore events on regions that are not us */
	127	if (section->mr != &opp->mem) {
	128	return;
	129	}
	130
d85937e6 SW	131	reg_base = section->offset_within_address_space;
	132
	133	attr.group = KVM_DEV_MPIC_GRP_MISC;
	134	attr.attr = KVM_DEV_MPIC_BASE_ADDR;
	135	attr.addr = (uint64_t)(unsigned long)&reg_base;
	136
	137	ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr);
	138	if (ret < 0) {
	139	fprintf(stderr, "%s: %s %" PRIx64 "\n", __func__,
	140	strerror(errno), reg_base);
	141	}
	142	}
	143
	144	static void kvm_openpic_region_del(MemoryListener *listener,
	145	MemoryRegionSection *section)
	146	{
	147	KVMOpenPICState *opp = container_of(listener, KVMOpenPICState,
	148	mem_listener);
	149	struct kvm_device_attr attr;
	150	uint64_t reg_base = 0;
	151	int ret;
	152
87d8354d AG	153	/* Ignore events on regions that are not us */
	154	if (section->mr != &opp->mem) {
	155	return;
	156	}
	157
d85937e6 SW	158	attr.group = KVM_DEV_MPIC_GRP_MISC;
	159	attr.attr = KVM_DEV_MPIC_BASE_ADDR;
	160	attr.addr = (uint64_t)(unsigned long)&reg_base;
	161
	162	ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr);
	163	if (ret < 0) {
	164	fprintf(stderr, "%s: %s %" PRIx64 "\n", __func__,
	165	strerror(errno), reg_base);
	166	}
	167	}
	168
dd49c038 AF	169	static void kvm_openpic_init(Object *obj)
	170	{
	171	KVMOpenPICState *opp = KVM_OPENPIC(obj);
	172
1437c94b	173	memory_region_init_io(&opp->mem, OBJECT(opp), &kvm_openpic_mem_ops, opp,
dd49c038 AF	174	"kvm-openpic", 0x40000);
	175	}
	176
	177	static void kvm_openpic_realize(DeviceState dev, Error *errp)
d85937e6	178	{
dd49c038 AF	179	SysBusDevice *d = SYS_BUS_DEVICE(dev);
dd49c038 AF	180	KVMOpenPICState *opp = KVM_OPENPIC(dev);
d85937e6	181	KVMState *s = kvm_state;
d85937e6 SW	182	int kvm_openpic_model;
	183	struct kvm_create_device cd = {0};
	184	int ret, i;
	185
	186	if (!kvm_check_extension(s, KVM_CAP_DEVICE_CTRL)) {
dd49c038 AF	187	error_setg(errp, "Kernel is lacking Device Control API");
dd49c038 AF	188	return;
d85937e6 SW	189	}
	190
	191	switch (opp->model) {
	192	case OPENPIC_MODEL_FSL_MPIC_20:
	193	kvm_openpic_model = KVM_DEV_TYPE_FSL_MPIC_20;
	194	break;
	195
	196	case OPENPIC_MODEL_FSL_MPIC_42:
	197	kvm_openpic_model = KVM_DEV_TYPE_FSL_MPIC_42;
	198	break;
	199
	200	default:
dd49c038 AF	201	error_setg(errp, "Unsupported OpenPIC model %" PRIu32, opp->model);
dd49c038 AF	202	return;
d85937e6 SW	203	}
	204
	205	cd.type = kvm_openpic_model;
	206	ret = kvm_vm_ioctl(s, KVM_CREATE_DEVICE, &cd);
	207	if (ret < 0) {
dd49c038 AF	208	error_setg(errp, "Can't create device %d: %s",
	209	cd.type, strerror(errno));
	210	return;
d85937e6 SW	211	}
	212	opp->fd = cd.fd;
	213
dd49c038 AF	214	sysbus_init_mmio(d, &opp->mem);
dd49c038 AF	215	qdev_init_gpio_in(dev, kvm_openpic_set_irq, OPENPIC_MAX_IRQ);
d85937e6 SW	216
d85937e6 SW	217	opp->mem_listener.region_add = kvm_openpic_region_add;
6f1834a2	218	opp->mem_listener.region_del = kvm_openpic_region_del;
d85937e6 SW	219	memory_listener_register(&opp->mem_listener, &address_space_memory);
	220
	221	/* indicate pic capabilities */
	222	msi_supported = true;
	223	kvm_kernel_irqchip = true;
	224	kvm_async_interrupts_allowed = true;
	225
	226	/* set up irq routing */
	227	kvm_init_irq_routing(kvm_state);
	228	for (i = 0; i < 256; ++i) {
	229	kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
	230	}
	231
	232	kvm_irqfds_allowed = true;
	233	kvm_msi_via_irqfd_allowed = true;
	234	kvm_gsi_routing_allowed = true;
	235
	236	kvm_irqchip_commit_routes(s);
d85937e6 SW	237	}
	238
	239	int kvm_openpic_connect_vcpu(DeviceState d, CPUState cs)
	240	{
dd49c038	241	KVMOpenPICState *opp = KVM_OPENPIC(d);
d85937e6	242
48add816 CH	243	return kvm_vcpu_enable_cap(cs, KVM_CAP_IRQ_MPIC, 0, opp->fd,
48add816 CH	244	kvm_arch_vcpu_id(cs));
d85937e6 SW	245	}
	246
	247	static Property kvm_openpic_properties[] = {
	248	DEFINE_PROP_UINT32("model", KVMOpenPICState, model,
	249	OPENPIC_MODEL_FSL_MPIC_20),
	250	DEFINE_PROP_END_OF_LIST(),
	251	};
	252
dd49c038	253	static void kvm_openpic_class_init(ObjectClass oc, void data)
d85937e6	254	{
dd49c038	255	DeviceClass *dc = DEVICE_CLASS(oc);
d85937e6	256
dd49c038	257	dc->realize = kvm_openpic_realize;
d85937e6 SW	258	dc->props = kvm_openpic_properties;
	259	dc->reset = kvm_openpic_reset;
	260	}
	261
	262	static const TypeInfo kvm_openpic_info = {
dd49c038	263	.name = TYPE_KVM_OPENPIC,
d85937e6 SW	264	.parent = TYPE_SYS_BUS_DEVICE,
d85937e6 SW	265	.instance_size = sizeof(KVMOpenPICState),
dd49c038	266	.instance_init = kvm_openpic_init,
d85937e6 SW	267	.class_init = kvm_openpic_class_init,
	268	};
	269
	270	static void kvm_openpic_register_types(void)
	271	{
	272	type_register_static(&kvm_openpic_info);
	273	}
	274
	275	type_init(kvm_openpic_register_types)