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target-cris/translate.c: Remove t_gen_mov_TN_reg and t_gen_mov_reg_TN
[qemu.git] / target-cris / translate.c
CommitLineData
8170028d
TS		 1/*
2 * CRIS emulation for qemu: main translation routines.
3 *
05ba7d5f 4 * Copyright (c) 2008 AXIS Communications AB
8170028d
TS		 5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
8167ee88 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
8170028d
TS		 19 */
20
b41f7df0
EI		 21/*
22 * FIXME:
cf1d97f0 23 * The condition code translation is in need of attention.
b41f7df0
EI		 24 */
25
8170028d 26#include "cpu.h"
76cad711 27#include "disas/disas.h"
57fec1fe 28#include "tcg-op.h"
2ef6175a 29#include "exec/helper-proto.h"
52819664 30#include "mmu.h"
f08b6170 31#include "exec/cpu_ldst.h"
8170028d
TS		 32#include "crisv32-decode.h"
33
2ef6175a 34#include "exec/helper-gen.h"
a7812ae4 35
8170028d
TS		 36#define DISAS_CRIS 0
37#if DISAS_CRIS
93fcfe39 38# define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
8170028d 39#else
d12d51d5 40# define LOG_DIS(...) do { } while (0)
8170028d
TS		 41#endif
42
b41f7df0 43#define D(x)
8170028d
TS		 44#define BUG() (gen_BUG(dc, __FILE__, __LINE__))
45#define BUG_ON(x) ({if (x) BUG();})
46
4f400ab5
EI		 47#define DISAS_SWI 5
48
8170028d
TS		 49/* Used by the decoder. */
50#define EXTRACT_FIELD(src, start, end) \
51 (((src) >> start) & ((1 << (end - start + 1)) - 1))
52
53#define CC_MASK_NZ 0xc
54#define CC_MASK_NZV 0xe
55#define CC_MASK_NZVC 0xf
56#define CC_MASK_RNZV 0x10e
57
a7812ae4 58static TCGv_ptr cpu_env;
9b32fbf8
EI		 59static TCGv cpu_R[16];
60static TCGv cpu_PR[16];
61static TCGv cc_x;
62static TCGv cc_src;
63static TCGv cc_dest;
64static TCGv cc_result;
65static TCGv cc_op;
66static TCGv cc_size;
67static TCGv cc_mask;
68
69static TCGv env_btaken;
70static TCGv env_btarget;
71static TCGv env_pc;
b41f7df0 72
022c62cb 73#include "exec/gen-icount.h"
2e70f6ef 74
8170028d
TS		 75/* This is the state at translation time. */
76typedef struct DisasContext {
0dd106c5 77 CRISCPU *cpu;
7b5eff4d 78 target_ulong pc, ppc;
8170028d 79
7b5eff4d 80 /* Decoder. */
cf7e0c80 81 unsigned int (*decoder)(CPUCRISState *env, struct DisasContext *dc);
7b5eff4d
EV		 82 uint32_t ir;
83 uint32_t opcode;
84 unsigned int op1;
85 unsigned int op2;
86 unsigned int zsize, zzsize;
87 unsigned int mode;
88 unsigned int postinc;
89
90 unsigned int size;
91 unsigned int src;
92 unsigned int dst;
93 unsigned int cond;
94
95 int update_cc;
96 int cc_op;
97 int cc_size;
98 uint32_t cc_mask;
99
100 int cc_size_uptodate; /* -1 invalid or last written value. */
101
102 int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not uptodate. */
103 int flags_uptodate; /* Wether or not $ccs is uptodate. */
104 int flagx_known; /* Wether or not flags_x has the x flag known at
105 translation time. */
106 int flags_x;
107
108 int clear_x; /* Clear x after this insn? */
109 int clear_prefix; /* Clear prefix after this insn? */
110 int clear_locked_irq; /* Clear the irq lockout. */
111 int cpustate_changed;
112 unsigned int tb_flags; /* tb dependent flags. */
113 int is_jmp;
8170028d 114
5cabc5cc
EI		 115#define JMP_NOJMP 0
116#define JMP_DIRECT 1
117#define JMP_DIRECT_CC 2
118#define JMP_INDIRECT 3
7b5eff4d
EV		 119 int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
120 uint32_t jmp_pc;
2a44f7f1 121
7b5eff4d 122 int delayed_branch;
8170028d 123
7b5eff4d
EV		 124 struct TranslationBlock *tb;
125 int singlestep_enabled;
8170028d
TS		 126} DisasContext;
127
7ccfb2eb 128static void gen_BUG(DisasContext *dc, const char *file, int line)
8170028d 129{
7b5eff4d
EV		 130 printf("BUG: pc=%x %s %d\n", dc->pc, file, line);
131 qemu_log("BUG: pc=%x %s %d\n", dc->pc, file, line);
0dd106c5 132 cpu_abort(CPU(dc->cpu), "%s:%d\n", file, line);
8170028d
TS		 133}
134
9b32fbf8 135static const char *regnames[] =
a825e703 136{
7b5eff4d
EV		 137 "$r0", "$r1", "$r2", "$r3",
138 "$r4", "$r5", "$r6", "$r7",
139 "$r8", "$r9", "$r10", "$r11",
140 "$r12", "$r13", "$sp", "$acr",
a825e703 141};
9b32fbf8 142static const char *pregnames[] =
a825e703 143{
7b5eff4d
EV		 144 "$bz", "$vr", "$pid", "$srs",
145 "$wz", "$exs", "$eda", "$mof",
146 "$dz", "$ebp", "$erp", "$srp",
147 "$nrp", "$ccs", "$usp", "$spc",
a825e703
EI		 148};
149
05ba7d5f 150/* We need this table to handle preg-moves with implicit width. */
9b32fbf8 151static int preg_sizes[] = {
7b5eff4d
EV		 152 1, /* bz. */
153 1, /* vr. */
154 4, /* pid. */
155 1, /* srs. */
156 2, /* wz. */
157 4, 4, 4,
158 4, 4, 4, 4,
159 4, 4, 4, 4,
05ba7d5f
EI		 160};
161
162#define t_gen_mov_TN_env(tn, member) \
a1170bfd 163 _t_gen_mov_TN_env((tn), offsetof(CPUCRISState, member))
05ba7d5f 164#define t_gen_mov_env_TN(member, tn) \
a1170bfd 165 _t_gen_mov_env_TN(offsetof(CPUCRISState, member), (tn))
05ba7d5f 166
05ba7d5f
EI		 167static inline void _t_gen_mov_TN_env(TCGv tn, int offset)
168{
7b5eff4d
EV		 169 if (offset > sizeof(CPUCRISState)) {
170 fprintf(stderr, "wrong load from env from off=%d\n", offset);
171 }
172 tcg_gen_ld_tl(tn, cpu_env, offset);
05ba7d5f
EI		 173}
174static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
175{
7b5eff4d
EV		 176 if (offset > sizeof(CPUCRISState)) {
177 fprintf(stderr, "wrong store to env at off=%d\n", offset);
178 }
179 tcg_gen_st_tl(tn, cpu_env, offset);
05ba7d5f
EI		 180}
181
182static inline void t_gen_mov_TN_preg(TCGv tn, int r)
183{
7b5eff4d
EV		 184 if (r < 0 || r > 15) {
185 fprintf(stderr, "wrong register read $p%d\n", r);
186 }
187 if (r == PR_BZ || r == PR_WZ || r == PR_DZ) {
188 tcg_gen_mov_tl(tn, tcg_const_tl(0));
189 } else if (r == PR_VR) {
190 tcg_gen_mov_tl(tn, tcg_const_tl(32));
191 } else {
192 tcg_gen_mov_tl(tn, cpu_PR[r]);
193 }
05ba7d5f 194}
cf1d97f0 195static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
05ba7d5f 196{
7b5eff4d
EV		 197 if (r < 0 || r > 15) {
198 fprintf(stderr, "wrong register write $p%d\n", r);
199 }
200 if (r == PR_BZ || r == PR_WZ || r == PR_DZ) {
201 return;
202 } else if (r == PR_SRS) {
203 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
204 } else {
205 if (r == PR_PID) {
206 gen_helper_tlb_flush_pid(cpu_env, tn);
207 }
208 if (dc->tb_flags & S_FLAG && r == PR_SPC) {
209 gen_helper_spc_write(cpu_env, tn);
210 } else if (r == PR_CCS) {
211 dc->cpustate_changed = 1;
212 }
213 tcg_gen_mov_tl(cpu_PR[r], tn);
214 }
05ba7d5f
EI		 215}
216
1884533c
EI		 217/* Sign extend at translation time. */
218static int sign_extend(unsigned int val, unsigned int width)
219{
7b5eff4d 220 int sval;
1884533c 221
7b5eff4d
EV		 222 /* LSL. */
223 val <<= 31 - width;
224 sval = val;
225 /* ASR. */
226 sval >>= 31 - width;
227 return sval;
1884533c
EI		 228}
229
cf7e0c80 230static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr,
7b5eff4d
EV		 231 unsigned int size, unsigned int sign)
232{
233 int r;
234
235 switch (size) {
236 case 4:
237 {
238 r = cpu_ldl_code(env, addr);
239 break;
240 }
241 case 2:
242 {
243 if (sign) {
244 r = cpu_ldsw_code(env, addr);
245 } else {
246 r = cpu_lduw_code(env, addr);
247 }
248 break;
249 }
250 case 1:
251 {
252 if (sign) {
253 r = cpu_ldsb_code(env, addr);
254 } else {
255 r = cpu_ldub_code(env, addr);
256 }
257 break;
258 }
259 default:
0dd106c5 260 cpu_abort(CPU(dc->cpu), "Invalid fetch size %d\n", size);
7b5eff4d
EV		 261 break;
262 }
263 return r;
7de141cb
EI		 264}
265
40e9eddd
EI		 266static void cris_lock_irq(DisasContext *dc)
267{
7b5eff4d
EV		 268 dc->clear_locked_irq = 0;
269 t_gen_mov_env_TN(locked_irq, tcg_const_tl(1));
40e9eddd
EI		 270}
271
dceaf394 272static inline void t_gen_raise_exception(uint32_t index)
05ba7d5f 273{
a7812ae4 274 TCGv_i32 tmp = tcg_const_i32(index);
febc9920 275 gen_helper_raise_exception(cpu_env, tmp);
a7812ae4 276 tcg_temp_free_i32(tmp);
05ba7d5f
EI		 277}
278
279static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
280{
7b5eff4d 281 TCGv t0, t_31;
05ba7d5f 282
7b5eff4d
EV		 283 t0 = tcg_temp_new();
284 t_31 = tcg_const_tl(31);
285 tcg_gen_shl_tl(d, a, b);
7dcfb089 286
7b5eff4d
EV		 287 tcg_gen_sub_tl(t0, t_31, b);
288 tcg_gen_sar_tl(t0, t0, t_31);
289 tcg_gen_and_tl(t0, t0, d);
290 tcg_gen_xor_tl(d, d, t0);
291 tcg_temp_free(t0);
292 tcg_temp_free(t_31);
05ba7d5f
EI		 293}
294
295static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
296{
7b5eff4d 297 TCGv t0, t_31;
05ba7d5f 298
7b5eff4d
EV		 299 t0 = tcg_temp_new();
300 t_31 = tcg_temp_new();
301 tcg_gen_shr_tl(d, a, b);
7dcfb089 302
7b5eff4d
EV		 303 tcg_gen_movi_tl(t_31, 31);
304 tcg_gen_sub_tl(t0, t_31, b);
305 tcg_gen_sar_tl(t0, t0, t_31);
306 tcg_gen_and_tl(t0, t0, d);
307 tcg_gen_xor_tl(d, d, t0);
308 tcg_temp_free(t0);
309 tcg_temp_free(t_31);
05ba7d5f
EI		 310}
311
312static void t_gen_asr(TCGv d, TCGv a, TCGv b)
313{
7b5eff4d 314 TCGv t0, t_31;
05ba7d5f 315
7b5eff4d
EV		 316 t0 = tcg_temp_new();
317 t_31 = tcg_temp_new();
318 tcg_gen_sar_tl(d, a, b);
7dcfb089 319
7b5eff4d
EV		 320 tcg_gen_movi_tl(t_31, 31);
321 tcg_gen_sub_tl(t0, t_31, b);
322 tcg_gen_sar_tl(t0, t0, t_31);
323 tcg_gen_or_tl(d, d, t0);
324 tcg_temp_free(t0);
325 tcg_temp_free(t_31);
05ba7d5f
EI		 326}
327
30abcfc7 328static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
aae6b32a 329{
7b5eff4d 330 int l1;
aae6b32a 331
7b5eff4d 332 l1 = gen_new_label();
aae6b32a 333
7b5eff4d
EV		 334 /*
335 * d <<= 1
336 * if (d >= s)
337 * d -= s;
338 */
339 tcg_gen_shli_tl(d, a, 1);
340 tcg_gen_brcond_tl(TCG_COND_LTU, d, b, l1);
341 tcg_gen_sub_tl(d, d, b);
342 gen_set_label(l1);
aae6b32a
EI		 343}
344
40e9eddd
EI		 345static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv ccs)
346{
7b5eff4d 347 TCGv t;
40e9eddd 348
7b5eff4d
EV		 349 /*
350 * d <<= 1
351 * if (n)
352 * d += s;
353 */
354 t = tcg_temp_new();
355 tcg_gen_shli_tl(d, a, 1);
356 tcg_gen_shli_tl(t, ccs, 31 - 3);
357 tcg_gen_sari_tl(t, t, 31);
358 tcg_gen_and_tl(t, t, b);
359 tcg_gen_add_tl(d, d, t);
360 tcg_temp_free(t);
40e9eddd
EI		 361}
362
3157a0a9
EI		 363/* Extended arithmetics on CRIS. */
364static inline void t_gen_add_flag(TCGv d, int flag)
365{
7b5eff4d 366 TCGv c;
3157a0a9 367
7b5eff4d
EV		 368 c = tcg_temp_new();
369 t_gen_mov_TN_preg(c, PR_CCS);
370 /* Propagate carry into d. */
371 tcg_gen_andi_tl(c, c, 1 << flag);
372 if (flag) {
373 tcg_gen_shri_tl(c, c, flag);
374 }
375 tcg_gen_add_tl(d, d, c);
376 tcg_temp_free(c);
3157a0a9
EI		 377}
378
30abcfc7 379static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
3157a0a9 380{
7b5eff4d
EV		 381 if (dc->flagx_known) {
382 if (dc->flags_x) {
383 TCGv c;
30abcfc7 384
7b5eff4d
EV		 385 c = tcg_temp_new();
386 t_gen_mov_TN_preg(c, PR_CCS);
387 /* C flag is already at bit 0. */
388 tcg_gen_andi_tl(c, c, C_FLAG);
389 tcg_gen_add_tl(d, d, c);
390 tcg_temp_free(c);
391 }
392 } else {
393 TCGv x, c;
394
395 x = tcg_temp_new();
396 c = tcg_temp_new();
397 t_gen_mov_TN_preg(x, PR_CCS);
398 tcg_gen_mov_tl(c, x);
399
400 /* Propagate carry into d if X is set. Branch free. */
401 tcg_gen_andi_tl(c, c, C_FLAG);
402 tcg_gen_andi_tl(x, x, X_FLAG);
403 tcg_gen_shri_tl(x, x, 4);
404
405 tcg_gen_and_tl(x, x, c);
406 tcg_gen_add_tl(d, d, x);
407 tcg_temp_free(x);
408 tcg_temp_free(c);
409 }
3157a0a9
EI		 410}
411
a39f8f3a 412static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
3157a0a9 413{
7b5eff4d
EV		 414 if (dc->flagx_known) {
415 if (dc->flags_x) {
416 TCGv c;
30abcfc7 417
7b5eff4d
EV		 418 c = tcg_temp_new();
419 t_gen_mov_TN_preg(c, PR_CCS);
420 /* C flag is already at bit 0. */
421 tcg_gen_andi_tl(c, c, C_FLAG);
422 tcg_gen_sub_tl(d, d, c);
423 tcg_temp_free(c);
424 }
425 } else {
426 TCGv x, c;
427
428 x = tcg_temp_new();
429 c = tcg_temp_new();
430 t_gen_mov_TN_preg(x, PR_CCS);
431 tcg_gen_mov_tl(c, x);
432
433 /* Propagate carry into d if X is set. Branch free. */
434 tcg_gen_andi_tl(c, c, C_FLAG);
435 tcg_gen_andi_tl(x, x, X_FLAG);
436 tcg_gen_shri_tl(x, x, 4);
437
438 tcg_gen_and_tl(x, x, c);
439 tcg_gen_sub_tl(d, d, x);
440 tcg_temp_free(x);
441 tcg_temp_free(c);
442 }
3157a0a9
EI		 443}
444
445/* Swap the two bytes within each half word of the s operand.
446 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
447static inline void t_gen_swapb(TCGv d, TCGv s)
448{
7b5eff4d 449 TCGv t, org_s;
3157a0a9 450
7b5eff4d
EV		 451 t = tcg_temp_new();
452 org_s = tcg_temp_new();
3157a0a9 453
7b5eff4d
EV		 454 /* d and s may refer to the same object. */
455 tcg_gen_mov_tl(org_s, s);
456 tcg_gen_shli_tl(t, org_s, 8);
457 tcg_gen_andi_tl(d, t, 0xff00ff00);
458 tcg_gen_shri_tl(t, org_s, 8);
459 tcg_gen_andi_tl(t, t, 0x00ff00ff);
460 tcg_gen_or_tl(d, d, t);
461 tcg_temp_free(t);
462 tcg_temp_free(org_s);
3157a0a9
EI		 463}
464
465/* Swap the halfwords of the s operand. */
466static inline void t_gen_swapw(TCGv d, TCGv s)
467{
7b5eff4d
EV		 468 TCGv t;
469 /* d and s refer the same object. */
470 t = tcg_temp_new();
471 tcg_gen_mov_tl(t, s);
472 tcg_gen_shli_tl(d, t, 16);
473 tcg_gen_shri_tl(t, t, 16);
474 tcg_gen_or_tl(d, d, t);
475 tcg_temp_free(t);
3157a0a9
EI		 476}
477
478/* Reverse the within each byte.
479 T0 = (((T0 << 7) & 0x80808080) |
480 ((T0 << 5) & 0x40404040) |
481 ((T0 << 3) & 0x20202020) |
482 ((T0 << 1) & 0x10101010) |
483 ((T0 >> 1) & 0x08080808) |
484 ((T0 >> 3) & 0x04040404) |
485 ((T0 >> 5) & 0x02020202) |
486 ((T0 >> 7) & 0x01010101));
487 */
488static inline void t_gen_swapr(TCGv d, TCGv s)
489{
7b5eff4d
EV		 490 struct {
491 int shift; /* LSL when positive, LSR when negative. */
492 uint32_t mask;
493 } bitrev[] = {
494 {7, 0x80808080},
495 {5, 0x40404040},
496 {3, 0x20202020},
497 {1, 0x10101010},
498 {-1, 0x08080808},
499 {-3, 0x04040404},
500 {-5, 0x02020202},
501 {-7, 0x01010101}
502 };
503 int i;
504 TCGv t, org_s;
505
506 /* d and s refer the same object. */
507 t = tcg_temp_new();
508 org_s = tcg_temp_new();
509 tcg_gen_mov_tl(org_s, s);
510
511 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
512 tcg_gen_andi_tl(d, t, bitrev[0].mask);
513 for (i = 1; i < ARRAY_SIZE(bitrev); i++) {
514 if (bitrev[i].shift >= 0) {
515 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
516 } else {
517 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
518 }
519 tcg_gen_andi_tl(t, t, bitrev[i].mask);
520 tcg_gen_or_tl(d, d, t);
521 }
522 tcg_temp_free(t);
523 tcg_temp_free(org_s);
3157a0a9
EI		 524}
525
cf1d97f0 526static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
17ac9754 527{
7b5eff4d 528 int l1;
17ac9754 529
7b5eff4d 530 l1 = gen_new_label();
17ac9754 531
7b5eff4d
EV		 532 /* Conditional jmp. */
533 tcg_gen_mov_tl(env_pc, pc_false);
534 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
535 tcg_gen_mov_tl(env_pc, pc_true);
536 gen_set_label(l1);
17ac9754
EI		 537}
538
8170028d
TS		 539static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
540{
7b5eff4d
EV		 541 TranslationBlock *tb;
542 tb = dc->tb;
543 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
544 tcg_gen_goto_tb(n);
545 tcg_gen_movi_tl(env_pc, dest);
8cfd0495 546 tcg_gen_exit_tb((uintptr_t)tb + n);
7b5eff4d
EV		 547 } else {
548 tcg_gen_movi_tl(env_pc, dest);
549 tcg_gen_exit_tb(0);
550 }
8170028d
TS		 551}
552
05ba7d5f
EI		 553static inline void cris_clear_x_flag(DisasContext *dc)
554{
7b5eff4d
EV		 555 if (dc->flagx_known && dc->flags_x) {
556 dc->flags_uptodate = 0;
557 }
2a44f7f1 558
7b5eff4d
EV		 559 dc->flagx_known = 1;
560 dc->flags_x = 0;
05ba7d5f
EI		 561}
562
30abcfc7 563static void cris_flush_cc_state(DisasContext *dc)
8170028d 564{
7b5eff4d
EV		 565 if (dc->cc_size_uptodate != dc->cc_size) {
566 tcg_gen_movi_tl(cc_size, dc->cc_size);
567 dc->cc_size_uptodate = dc->cc_size;
568 }
569 tcg_gen_movi_tl(cc_op, dc->cc_op);
570 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
30abcfc7
EI		 571}
572
573static void cris_evaluate_flags(DisasContext *dc)
574{
7b5eff4d
EV		 575 if (dc->flags_uptodate) {
576 return;
577 }
578
579 cris_flush_cc_state(dc);
580
581 switch (dc->cc_op) {
582 case CC_OP_MCP:
583 gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], cpu_env,
584 cpu_PR[PR_CCS], cc_src,
585 cc_dest, cc_result);
586 break;
587 case CC_OP_MULS:
588 gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], cpu_env,
589 cpu_PR[PR_CCS], cc_result,
590 cpu_PR[PR_MOF]);
591 break;
592 case CC_OP_MULU:
593 gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], cpu_env,
594 cpu_PR[PR_CCS], cc_result,
595 cpu_PR[PR_MOF]);
596 break;
597 case CC_OP_MOVE:
598 case CC_OP_AND:
599 case CC_OP_OR:
600 case CC_OP_XOR:
601 case CC_OP_ASR:
602 case CC_OP_LSR:
603 case CC_OP_LSL:
604 switch (dc->cc_size) {
605 case 4:
606 gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
607 cpu_env, cpu_PR[PR_CCS], cc_result);
608 break;
609 case 2:
610 gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
611 cpu_env, cpu_PR[PR_CCS], cc_result);
612 break;
613 default:
614 gen_helper_evaluate_flags(cpu_env);
615 break;
616 }
617 break;
618 case CC_OP_FLAGS:
619 /* live. */
620 break;
621 case CC_OP_SUB:
622 case CC_OP_CMP:
623 if (dc->cc_size == 4) {
624 gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], cpu_env,
625 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
626 } else {
627 gen_helper_evaluate_flags(cpu_env);
628 }
629
630 break;
631 default:
632 switch (dc->cc_size) {
633 case 4:
634 gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], cpu_env,
635 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
636 break;
637 default:
638 gen_helper_evaluate_flags(cpu_env);
639 break;
6231868b 640 }
7b5eff4d
EV		 641 break;
642 }
643
644 if (dc->flagx_known) {
645 if (dc->flags_x) {
646 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], X_FLAG);
647 } else if (dc->cc_op == CC_OP_FLAGS) {
648 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG);
649 }
650 }
651 dc->flags_uptodate = 1;
8170028d
TS		 652}
653
654static void cris_cc_mask(DisasContext *dc, unsigned int mask)
655{
7b5eff4d 656 uint32_t ovl;
8170028d 657
7b5eff4d
EV		 658 if (!mask) {
659 dc->update_cc = 0;
660 return;
661 }
2a44f7f1 662
7b5eff4d
EV		 663 /* Check if we need to evaluate the condition codes due to
664 CC overlaying. */
665 ovl = (dc->cc_mask ^ mask) & ~mask;
666 if (ovl) {
667 /* TODO: optimize this case. It trigs all the time. */
668 cris_evaluate_flags(dc);
669 }
670 dc->cc_mask = mask;
671 dc->update_cc = 1;
8170028d
TS		 672}
673
b41f7df0 674static void cris_update_cc_op(DisasContext *dc, int op, int size)
8170028d 675{
7b5eff4d
EV		 676 dc->cc_op = op;
677 dc->cc_size = size;
678 dc->flags_uptodate = 0;
8170028d
TS		 679}
680
30abcfc7
EI		 681static inline void cris_update_cc_x(DisasContext *dc)
682{
7b5eff4d
EV		 683 /* Save the x flag state at the time of the cc snapshot. */
684 if (dc->flagx_known) {
685 if (dc->cc_x_uptodate == (2 | dc->flags_x)) {
686 return;
687 }
688 tcg_gen_movi_tl(cc_x, dc->flags_x);
689 dc->cc_x_uptodate = 2 | dc->flags_x;
690 } else {
691 tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);
692 dc->cc_x_uptodate = 1;
693 }
30abcfc7
EI		 694}
695
696/* Update cc prior to executing ALU op. Needs source operands untouched. */
697static void cris_pre_alu_update_cc(DisasContext *dc, int op,
7b5eff4d
EV		 698 TCGv dst, TCGv src, int size)
699{
700 if (dc->update_cc) {
701 cris_update_cc_op(dc, op, size);
702 tcg_gen_mov_tl(cc_src, src);
703
704 if (op != CC_OP_MOVE
705 && op != CC_OP_AND
706 && op != CC_OP_OR
707 && op != CC_OP_XOR
708 && op != CC_OP_ASR
709 && op != CC_OP_LSR
710 && op != CC_OP_LSL) {
711 tcg_gen_mov_tl(cc_dest, dst);
712 }
30abcfc7 713
7b5eff4d
EV		 714 cris_update_cc_x(dc);
715 }
30abcfc7 716}
3157a0a9 717
30abcfc7
EI		 718/* Update cc after executing ALU op. needs the result. */
719static inline void cris_update_result(DisasContext *dc, TCGv res)
720{
7b5eff4d
EV		 721 if (dc->update_cc) {
722 tcg_gen_mov_tl(cc_result, res);
723 }
30abcfc7 724}
8170028d 725
30abcfc7
EI		 726/* Returns one if the write back stage should execute. */
727static void cris_alu_op_exec(DisasContext *dc, int op,
7b5eff4d
EV		 728 TCGv dst, TCGv a, TCGv b, int size)
729{
730 /* Emit the ALU insns. */
731 switch (op) {
732 case CC_OP_ADD:
733 tcg_gen_add_tl(dst, a, b);
734 /* Extended arithmetics. */
735 t_gen_addx_carry(dc, dst);
736 break;
737 case CC_OP_ADDC:
738 tcg_gen_add_tl(dst, a, b);
739 t_gen_add_flag(dst, 0); /* C_FLAG. */
740 break;
741 case CC_OP_MCP:
742 tcg_gen_add_tl(dst, a, b);
743 t_gen_add_flag(dst, 8); /* R_FLAG. */
744 break;
745 case CC_OP_SUB:
746 tcg_gen_sub_tl(dst, a, b);
747 /* Extended arithmetics. */
748 t_gen_subx_carry(dc, dst);
749 break;
750 case CC_OP_MOVE:
751 tcg_gen_mov_tl(dst, b);
752 break;
753 case CC_OP_OR:
754 tcg_gen_or_tl(dst, a, b);
755 break;
756 case CC_OP_AND:
757 tcg_gen_and_tl(dst, a, b);
758 break;
759 case CC_OP_XOR:
760 tcg_gen_xor_tl(dst, a, b);
761 break;
762 case CC_OP_LSL:
763 t_gen_lsl(dst, a, b);
764 break;
765 case CC_OP_LSR:
766 t_gen_lsr(dst, a, b);
767 break;
768 case CC_OP_ASR:
769 t_gen_asr(dst, a, b);
770 break;
771 case CC_OP_NEG:
772 tcg_gen_neg_tl(dst, b);
773 /* Extended arithmetics. */
774 t_gen_subx_carry(dc, dst);
775 break;
776 case CC_OP_LZ:
777 gen_helper_lz(dst, b);
778 break;
779 case CC_OP_MULS:
bf45f971 780 tcg_gen_muls2_tl(dst, cpu_PR[PR_MOF], a, b);
7b5eff4d
EV		 781 break;
782 case CC_OP_MULU:
bf45f971 783 tcg_gen_mulu2_tl(dst, cpu_PR[PR_MOF], a, b);
7b5eff4d
EV		 784 break;
785 case CC_OP_DSTEP:
786 t_gen_cris_dstep(dst, a, b);
787 break;
788 case CC_OP_MSTEP:
789 t_gen_cris_mstep(dst, a, b, cpu_PR[PR_CCS]);
790 break;
791 case CC_OP_BOUND:
792 {
793 int l1;
794 l1 = gen_new_label();
795 tcg_gen_mov_tl(dst, a);
796 tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1);
797 tcg_gen_mov_tl(dst, b);
798 gen_set_label(l1);
799 }
800 break;
801 case CC_OP_CMP:
802 tcg_gen_sub_tl(dst, a, b);
803 /* Extended arithmetics. */
804 t_gen_subx_carry(dc, dst);
805 break;
806 default:
807 qemu_log("illegal ALU op.\n");
808 BUG();
809 break;
810 }
811
812 if (size == 1) {
813 tcg_gen_andi_tl(dst, dst, 0xff);
814 } else if (size == 2) {
815 tcg_gen_andi_tl(dst, dst, 0xffff);
816 }
30abcfc7
EI		 817}
818
819static void cris_alu(DisasContext *dc, int op,
7b5eff4d 820 TCGv d, TCGv op_a, TCGv op_b, int size)
30abcfc7 821{
7b5eff4d
EV		 822 TCGv tmp;
823 int writeback;
30abcfc7 824
7b5eff4d 825 writeback = 1;
31c18d87 826
7b5eff4d
EV		 827 if (op == CC_OP_CMP) {
828 tmp = tcg_temp_new();
829 writeback = 0;
830 } else if (size == 4) {
831 tmp = d;
832 writeback = 0;
833 } else {
834 tmp = tcg_temp_new();
835 }
44696296 836
30abcfc7 837
7b5eff4d
EV		 838 cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
839 cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
840 cris_update_result(dc, tmp);
05ba7d5f 841
7b5eff4d
EV		 842 /* Writeback. */
843 if (writeback) {
844 if (size == 1) {
845 tcg_gen_andi_tl(d, d, ~0xff);
846 } else {
847 tcg_gen_andi_tl(d, d, ~0xffff);
848 }
849 tcg_gen_or_tl(d, d, tmp);
850 }
851 if (!TCGV_EQUAL(tmp, d)) {
852 tcg_temp_free(tmp);
853 }
8170028d
TS		 854}
855
856static int arith_cc(DisasContext *dc)
857{
7b5eff4d
EV		 858 if (dc->update_cc) {
859 switch (dc->cc_op) {
860 case CC_OP_ADDC: return 1;
861 case CC_OP_ADD: return 1;
862 case CC_OP_SUB: return 1;
863 case CC_OP_DSTEP: return 1;
864 case CC_OP_LSL: return 1;
865 case CC_OP_LSR: return 1;
866 case CC_OP_ASR: return 1;
867 case CC_OP_CMP: return 1;
868 case CC_OP_NEG: return 1;
869 case CC_OP_OR: return 1;
870 case CC_OP_AND: return 1;
871 case CC_OP_XOR: return 1;
872 case CC_OP_MULU: return 1;
873 case CC_OP_MULS: return 1;
874 default:
875 return 0;
876 }
877 }
878 return 0;
8170028d
TS		 879}
880
c5631f48 881static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond)
8170028d 882{
7b5eff4d
EV		 883 int arith_opt, move_opt;
884
885 /* TODO: optimize more condition codes. */
886
887 /*
888 * If the flags are live, we've gotta look into the bits of CCS.
889 * Otherwise, if we just did an arithmetic operation we try to
890 * evaluate the condition code faster.
891 *
892 * When this function is done, T0 should be non-zero if the condition
893 * code is true.
894 */
895 arith_opt = arith_cc(dc) && !dc->flags_uptodate;
896 move_opt = (dc->cc_op == CC_OP_MOVE);
897 switch (cond) {
898 case CC_EQ:
899 if ((arith_opt || move_opt)
900 && dc->cc_x_uptodate != (2 | X_FLAG)) {
901 tcg_gen_setcond_tl(TCG_COND_EQ, cc,
902 cc_result, tcg_const_tl(0));
903 } else {
904 cris_evaluate_flags(dc);
905 tcg_gen_andi_tl(cc,
906 cpu_PR[PR_CCS], Z_FLAG);
907 }
908 break;
909 case CC_NE:
910 if ((arith_opt || move_opt)
911 && dc->cc_x_uptodate != (2 | X_FLAG)) {
912 tcg_gen_mov_tl(cc, cc_result);
913 } else {
914 cris_evaluate_flags(dc);
915 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
916 Z_FLAG);
917 tcg_gen_andi_tl(cc, cc, Z_FLAG);
918 }
919 break;
920 case CC_CS:
921 cris_evaluate_flags(dc);
922 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG);
923 break;
924 case CC_CC:
925 cris_evaluate_flags(dc);
926 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG);
927 tcg_gen_andi_tl(cc, cc, C_FLAG);
928 break;
929 case CC_VS:
930 cris_evaluate_flags(dc);
931 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG);
932 break;
933 case CC_VC:
934 cris_evaluate_flags(dc);
935 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
936 V_FLAG);
937 tcg_gen_andi_tl(cc, cc, V_FLAG);
938 break;
939 case CC_PL:
940 if (arith_opt || move_opt) {
941 int bits = 31;
942
943 if (dc->cc_size == 1) {
944 bits = 7;
945 } else if (dc->cc_size == 2) {
946 bits = 15;
947 }
948
949 tcg_gen_shri_tl(cc, cc_result, bits);
950 tcg_gen_xori_tl(cc, cc, 1);
951 } else {
952 cris_evaluate_flags(dc);
953 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
954 N_FLAG);
955 tcg_gen_andi_tl(cc, cc, N_FLAG);
956 }
957 break;
958 case CC_MI:
959 if (arith_opt || move_opt) {
960 int bits = 31;
961
962 if (dc->cc_size == 1) {
963 bits = 7;
964 } else if (dc->cc_size == 2) {
965 bits = 15;
966 }
967
968 tcg_gen_shri_tl(cc, cc_result, bits);
969 tcg_gen_andi_tl(cc, cc, 1);
970 } else {
971 cris_evaluate_flags(dc);
972 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
973 N_FLAG);
974 }
975 break;
976 case CC_LS:
977 cris_evaluate_flags(dc);
978 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
979 C_FLAG | Z_FLAG);
980 break;
981 case CC_HI:
982 cris_evaluate_flags(dc);
983 {
984 TCGv tmp;
985
986 tmp = tcg_temp_new();
987 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
988 C_FLAG | Z_FLAG);
989 /* Overlay the C flag on top of the Z. */
990 tcg_gen_shli_tl(cc, tmp, 2);
991 tcg_gen_and_tl(cc, tmp, cc);
992 tcg_gen_andi_tl(cc, cc, Z_FLAG);
993
994 tcg_temp_free(tmp);
995 }
996 break;
997 case CC_GE:
998 cris_evaluate_flags(dc);
999 /* Overlay the V flag on top of the N. */
1000 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
1001 tcg_gen_xor_tl(cc,
1002 cpu_PR[PR_CCS], cc);
1003 tcg_gen_andi_tl(cc, cc, N_FLAG);
1004 tcg_gen_xori_tl(cc, cc, N_FLAG);
1005 break;
1006 case CC_LT:
1007 cris_evaluate_flags(dc);
1008 /* Overlay the V flag on top of the N. */
1009 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
1010 tcg_gen_xor_tl(cc,
1011 cpu_PR[PR_CCS], cc);
1012 tcg_gen_andi_tl(cc, cc, N_FLAG);
1013 break;
1014 case CC_GT:
1015 cris_evaluate_flags(dc);
1016 {
1017 TCGv n, z;
1018
1019 n = tcg_temp_new();
1020 z = tcg_temp_new();
1021
1022 /* To avoid a shift we overlay everything on
1023 the V flag. */
1024 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1025 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1026 /* invert Z. */
1027 tcg_gen_xori_tl(z, z, 2);
1028
1029 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1030 tcg_gen_xori_tl(n, n, 2);
1031 tcg_gen_and_tl(cc, z, n);
1032 tcg_gen_andi_tl(cc, cc, 2);
1033
1034 tcg_temp_free(n);
1035 tcg_temp_free(z);
1036 }
1037 break;
1038 case CC_LE:
1039 cris_evaluate_flags(dc);
1040 {
1041 TCGv n, z;
1042
1043 n = tcg_temp_new();
1044 z = tcg_temp_new();
1045
1046 /* To avoid a shift we overlay everything on
1047 the V flag. */
1048 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1049 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1050
1051 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1052 tcg_gen_or_tl(cc, z, n);
1053 tcg_gen_andi_tl(cc, cc, 2);
1054
1055 tcg_temp_free(n);
1056 tcg_temp_free(z);
1057 }
1058 break;
1059 case CC_P:
1060 cris_evaluate_flags(dc);
1061 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG);
1062 break;
1063 case CC_A:
1064 tcg_gen_movi_tl(cc, 1);
1065 break;
1066 default:
1067 BUG();
1068 break;
1069 };
8170028d
TS		 1070}
1071
2a44f7f1
EI		 1072static void cris_store_direct_jmp(DisasContext *dc)
1073{
7b5eff4d
EV		 1074 /* Store the direct jmp state into the cpu-state. */
1075 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
1076 if (dc->jmp == JMP_DIRECT) {
1077 tcg_gen_movi_tl(env_btaken, 1);
1078 }
1079 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1080 dc->jmp = JMP_INDIRECT;
1081 }
2a44f7f1
EI		 1082}
1083
1084static void cris_prepare_cc_branch (DisasContext *dc,
7b5eff4d 1085 int offset, int cond)
8170028d 1086{
7b5eff4d
EV		 1087 /* This helps us re-schedule the micro-code to insns in delay-slots
1088 before the actual jump. */
1089 dc->delayed_branch = 2;
1090 dc->jmp = JMP_DIRECT_CC;
1091 dc->jmp_pc = dc->pc + offset;
2a44f7f1 1092
7b5eff4d
EV		 1093 gen_tst_cc(dc, env_btaken, cond);
1094 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
8170028d
TS		 1095}
1096
b41f7df0 1097
2a44f7f1
EI		 1098/* jumps, when the dest is in a live reg for example. Direct should be set
1099 when the dest addr is constant to allow tb chaining. */
1100static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
8170028d 1101{
7b5eff4d
EV		 1102 /* This helps us re-schedule the micro-code to insns in delay-slots
1103 before the actual jump. */
1104 dc->delayed_branch = 2;
1105 dc->jmp = type;
1106 if (type == JMP_INDIRECT) {
1107 tcg_gen_movi_tl(env_btaken, 1);
1108 }
8170028d
TS		 1109}
1110
a7812ae4
PB		 1111static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
1112{
0dd106c5 1113 int mem_index = cpu_mmu_index(&dc->cpu->env);
a7812ae4 1114
7b5eff4d
EV		 1115 /* If we get a fault on a delayslot we must keep the jmp state in
1116 the cpu-state to be able to re-execute the jmp. */
1117 if (dc->delayed_branch == 1) {
1118 cris_store_direct_jmp(dc);
1119 }
a7812ae4 1120
a1d22a36 1121 tcg_gen_qemu_ld_i64(dst, addr, mem_index, MO_TEQ);
a7812ae4
PB		 1122}
1123
9b32fbf8 1124static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
7b5eff4d
EV		 1125 unsigned int size, int sign)
1126{
0dd106c5 1127 int mem_index = cpu_mmu_index(&dc->cpu->env);
7b5eff4d
EV		 1128
1129 /* If we get a fault on a delayslot we must keep the jmp state in
1130 the cpu-state to be able to re-execute the jmp. */
1131 if (dc->delayed_branch == 1) {
1132 cris_store_direct_jmp(dc);
1133 }
1134
a1d22a36
RH		 1135 tcg_gen_qemu_ld_tl(dst, addr, mem_index,
1136 MO_TE + ctz32(size) + (sign ? MO_SIGN : 0));
8170028d
TS		 1137}
1138
9b32fbf8 1139static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
7b5eff4d 1140 unsigned int size)
8170028d 1141{
0dd106c5 1142 int mem_index = cpu_mmu_index(&dc->cpu->env);
b41f7df0 1143
7b5eff4d
EV		 1144 /* If we get a fault on a delayslot we must keep the jmp state in
1145 the cpu-state to be able to re-execute the jmp. */
1146 if (dc->delayed_branch == 1) {
1147 cris_store_direct_jmp(dc);
1148 }
2a44f7f1
EI		 1149
1150
7b5eff4d
EV		 1151 /* Conditional writes. We only support the kind were X and P are known
1152 at translation time. */
1153 if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) {
1154 dc->postinc = 0;
1155 cris_evaluate_flags(dc);
1156 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);
1157 return;
1158 }
2a44f7f1 1159
a1d22a36 1160 tcg_gen_qemu_st_tl(val, addr, mem_index, MO_TE + ctz32(size));
2a44f7f1 1161
7b5eff4d
EV		 1162 if (dc->flagx_known && dc->flags_x) {
1163 cris_evaluate_flags(dc);
1164 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);
1165 }
8170028d
TS		 1166}
1167
05ba7d5f 1168static inline void t_gen_sext(TCGv d, TCGv s, int size)
8170028d 1169{
7b5eff4d
EV		 1170 if (size == 1) {
1171 tcg_gen_ext8s_i32(d, s);
1172 } else if (size == 2) {
1173 tcg_gen_ext16s_i32(d, s);
1174 } else if (!TCGV_EQUAL(d, s)) {
1175 tcg_gen_mov_tl(d, s);
1176 }
8170028d
TS		 1177}
1178
05ba7d5f 1179static inline void t_gen_zext(TCGv d, TCGv s, int size)
8170028d 1180{
7b5eff4d
EV		 1181 if (size == 1) {
1182 tcg_gen_ext8u_i32(d, s);
1183 } else if (size == 2) {
1184 tcg_gen_ext16u_i32(d, s);
1185 } else if (!TCGV_EQUAL(d, s)) {
1186 tcg_gen_mov_tl(d, s);
1187 }
8170028d
TS		 1188}
1189
1190#if DISAS_CRIS
1191static char memsize_char(int size)
1192{
7b5eff4d
EV		 1193 switch (size) {
1194 case 1: return 'b'; break;
1195 case 2: return 'w'; break;
1196 case 4: return 'd'; break;
1197 default:
1198 return 'x';
1199 break;
1200 }
8170028d
TS		 1201}
1202#endif
1203
30abcfc7 1204static inline unsigned int memsize_z(DisasContext *dc)
8170028d 1205{
7b5eff4d 1206 return dc->zsize + 1;
8170028d
TS		 1207}
1208
30abcfc7 1209static inline unsigned int memsize_zz(DisasContext *dc)
8170028d 1210{
7b5eff4d
EV		 1211 switch (dc->zzsize) {
1212 case 0: return 1;
1213 case 1: return 2;
1214 default:
1215 return 4;
1216 }
8170028d
TS		 1217}
1218
c7d05695 1219static inline void do_postinc (DisasContext *dc, int size)
8170028d 1220{
7b5eff4d
EV		 1221 if (dc->postinc) {
1222 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1223 }
8170028d
TS		 1224}
1225
30abcfc7 1226static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
7b5eff4d 1227 int size, int s_ext, TCGv dst)
8170028d 1228{
7b5eff4d
EV		 1229 if (s_ext) {
1230 t_gen_sext(dst, cpu_R[rs], size);
1231 } else {
1232 t_gen_zext(dst, cpu_R[rs], size);
1233 }
8170028d
TS		 1234}
1235
1236/* Prepare T0 and T1 for a register alu operation.
1237 s_ext decides if the operand1 should be sign-extended or zero-extended when
1238 needed. */
1239static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
7b5eff4d 1240 int size, int s_ext, TCGv dst, TCGv src)
8170028d 1241{
7b5eff4d 1242 dec_prep_move_r(dc, rs, rd, size, s_ext, src);
8170028d 1243
7b5eff4d
EV		 1244 if (s_ext) {
1245 t_gen_sext(dst, cpu_R[rd], size);
1246 } else {
1247 t_gen_zext(dst, cpu_R[rd], size);
1248 }
8170028d
TS		 1249}
1250
cf7e0c80
AJ		 1251static int dec_prep_move_m(CPUCRISState *env, DisasContext *dc,
1252 int s_ext, int memsize, TCGv dst)
8170028d 1253{
7b5eff4d
EV		 1254 unsigned int rs;
1255 uint32_t imm;
1256 int is_imm;
1257 int insn_len = 2;
1258
1259 rs = dc->op1;
1260 is_imm = rs == 15 && dc->postinc;
1261
1262 /* Load [$rs] onto T1. */
1263 if (is_imm) {
1264 insn_len = 2 + memsize;
1265 if (memsize == 1) {
1266 insn_len++;
1267 }
1268
1269 imm = cris_fetch(env, dc, dc->pc + 2, memsize, s_ext);
1270 tcg_gen_movi_tl(dst, imm);
1271 dc->postinc = 0;
1272 } else {
1273 cris_flush_cc_state(dc);
1274 gen_load(dc, dst, cpu_R[rs], memsize, 0);
1275 if (s_ext) {
1276 t_gen_sext(dst, dst, memsize);
1277 } else {
1278 t_gen_zext(dst, dst, memsize);
1279 }
1280 }
1281 return insn_len;
cf1d97f0
EI		 1282}
1283
1284/* Prepare T0 and T1 for a memory + alu operation.
1285 s_ext decides if the operand1 should be sign-extended or zero-extended when
1286 needed. */
cf7e0c80
AJ		 1287static int dec_prep_alu_m(CPUCRISState *env, DisasContext *dc,
1288 int s_ext, int memsize, TCGv dst, TCGv src)
cf1d97f0 1289{
7b5eff4d 1290 int insn_len;
cf1d97f0 1291
7b5eff4d
EV		 1292 insn_len = dec_prep_move_m(env, dc, s_ext, memsize, src);
1293 tcg_gen_mov_tl(dst, cpu_R[dc->op2]);
1294 return insn_len;
8170028d
TS		 1295}
1296
1297#if DISAS_CRIS
1298static const char *cc_name(int cc)
1299{
7b5eff4d
EV		 1300 static const char *cc_names[16] = {
1301 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1302 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1303 };
1304 assert(cc < 16);
1305 return cc_names[cc];
8170028d
TS		 1306}
1307#endif
1308
b41f7df0
EI		 1309/* Start of insn decoders. */
1310
cf7e0c80 1311static int dec_bccq(CPUCRISState *env, DisasContext *dc)
8170028d 1312{
7b5eff4d
EV		 1313 int32_t offset;
1314 int sign;
1315 uint32_t cond = dc->op2;
8170028d 1316
7b5eff4d
EV		 1317 offset = EXTRACT_FIELD(dc->ir, 1, 7);
1318 sign = EXTRACT_FIELD(dc->ir, 0, 0);
8170028d 1319
7b5eff4d
EV		 1320 offset *= 2;
1321 offset |= sign << 8;
1322 offset = sign_extend(offset, 8);
8170028d 1323
7b5eff4d 1324 LOG_DIS("b%s %x\n", cc_name(cond), dc->pc + offset);
2a44f7f1 1325
7b5eff4d
EV		 1326 /* op2 holds the condition-code. */
1327 cris_cc_mask(dc, 0);
1328 cris_prepare_cc_branch(dc, offset, cond);
1329 return 2;
8170028d 1330}
cf7e0c80 1331static int dec_addoq(CPUCRISState *env, DisasContext *dc)
8170028d 1332{
7b5eff4d 1333 int32_t imm;
8170028d 1334
7b5eff4d
EV		 1335 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1336 imm = sign_extend(dc->op1, 7);
8170028d 1337
7b5eff4d
EV		 1338 LOG_DIS("addoq %d, $r%u\n", imm, dc->op2);
1339 cris_cc_mask(dc, 0);
1340 /* Fetch register operand, */
1341 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
fb48f71b 1342
7b5eff4d 1343 return 2;
8170028d 1344}
cf7e0c80 1345static int dec_addq(CPUCRISState *env, DisasContext *dc)
8170028d 1346{
7b5eff4d 1347 LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2);
8170028d 1348
7b5eff4d 1349 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
8170028d 1350
7b5eff4d 1351 cris_cc_mask(dc, CC_MASK_NZVC);
30abcfc7 1352
7b5eff4d
EV		 1353 cris_alu(dc, CC_OP_ADD,
1354 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1355 return 2;
8170028d 1356}
cf7e0c80 1357static int dec_moveq(CPUCRISState *env, DisasContext *dc)
8170028d 1358{
7b5eff4d 1359 uint32_t imm;
8170028d 1360
7b5eff4d
EV		 1361 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1362 imm = sign_extend(dc->op1, 5);
1363 LOG_DIS("moveq %d, $r%u\n", imm, dc->op2);
8170028d 1364
7b5eff4d
EV		 1365 tcg_gen_movi_tl(cpu_R[dc->op2], imm);
1366 return 2;
8170028d 1367}
cf7e0c80 1368static int dec_subq(CPUCRISState *env, DisasContext *dc)
8170028d 1369{
7b5eff4d 1370 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
8170028d 1371
7b5eff4d 1372 LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2);
8170028d 1373
7b5eff4d
EV		 1374 cris_cc_mask(dc, CC_MASK_NZVC);
1375 cris_alu(dc, CC_OP_SUB,
1376 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1377 return 2;
8170028d 1378}
cf7e0c80 1379static int dec_cmpq(CPUCRISState *env, DisasContext *dc)
8170028d 1380{
7b5eff4d
EV		 1381 uint32_t imm;
1382 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1383 imm = sign_extend(dc->op1, 5);
8170028d 1384
7b5eff4d
EV		 1385 LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2);
1386 cris_cc_mask(dc, CC_MASK_NZVC);
30abcfc7 1387
7b5eff4d
EV		 1388 cris_alu(dc, CC_OP_CMP,
1389 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1390 return 2;
8170028d 1391}
cf7e0c80 1392static int dec_andq(CPUCRISState *env, DisasContext *dc)
8170028d 1393{
7b5eff4d
EV		 1394 uint32_t imm;
1395 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1396 imm = sign_extend(dc->op1, 5);
8170028d 1397
7b5eff4d
EV		 1398 LOG_DIS("andq %d, $r%d\n", imm, dc->op2);
1399 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7 1400
7b5eff4d
EV		 1401 cris_alu(dc, CC_OP_AND,
1402 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1403 return 2;
8170028d 1404}
cf7e0c80 1405static int dec_orq(CPUCRISState *env, DisasContext *dc)
8170028d 1406{
7b5eff4d
EV		 1407 uint32_t imm;
1408 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1409 imm = sign_extend(dc->op1, 5);
1410 LOG_DIS("orq %d, $r%d\n", imm, dc->op2);
1411 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7 1412
7b5eff4d
EV		 1413 cris_alu(dc, CC_OP_OR,
1414 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1415 return 2;
8170028d 1416}
cf7e0c80 1417static int dec_btstq(CPUCRISState *env, DisasContext *dc)
8170028d 1418{
7b5eff4d
EV		 1419 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1420 LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);
17ac9754 1421
7b5eff4d
EV		 1422 cris_cc_mask(dc, CC_MASK_NZ);
1423 cris_evaluate_flags(dc);
febc9920 1424 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
7b5eff4d
EV		 1425 tcg_const_tl(dc->op1), cpu_PR[PR_CCS]);
1426 cris_alu(dc, CC_OP_MOVE,
1427 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1428 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1429 dc->flags_uptodate = 1;
1430 return 2;
8170028d 1431}
cf7e0c80 1432static int dec_asrq(CPUCRISState *env, DisasContext *dc)
8170028d 1433{
7b5eff4d
EV		 1434 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1435 LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2);
1436 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7 1437
7b5eff4d
EV		 1438 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1439 cris_alu(dc, CC_OP_MOVE,
1440 cpu_R[dc->op2],
1441 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1442 return 2;
8170028d 1443}
cf7e0c80 1444static int dec_lslq(CPUCRISState *env, DisasContext *dc)
8170028d 1445{
7b5eff4d
EV		 1446 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1447 LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2);
8170028d 1448
7b5eff4d 1449 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7 1450
7b5eff4d 1451 tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
2a44f7f1 1452
7b5eff4d
EV		 1453 cris_alu(dc, CC_OP_MOVE,
1454 cpu_R[dc->op2],
1455 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1456 return 2;
8170028d 1457}
cf7e0c80 1458static int dec_lsrq(CPUCRISState *env, DisasContext *dc)
8170028d 1459{
7b5eff4d
EV		 1460 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1461 LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2);
8170028d 1462
7b5eff4d 1463 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7 1464
7b5eff4d
EV		 1465 tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1466 cris_alu(dc, CC_OP_MOVE,
1467 cpu_R[dc->op2],
1468 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1469 return 2;
8170028d
TS		 1470}
1471
cf7e0c80 1472static int dec_move_r(CPUCRISState *env, DisasContext *dc)
8170028d 1473{
7b5eff4d
EV		 1474 int size = memsize_zz(dc);
1475
1476 LOG_DIS("move.%c $r%u, $r%u\n",
1477 memsize_char(size), dc->op1, dc->op2);
1478
1479 cris_cc_mask(dc, CC_MASK_NZ);
1480 if (size == 4) {
1481 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
1482 cris_cc_mask(dc, CC_MASK_NZ);
1483 cris_update_cc_op(dc, CC_OP_MOVE, 4);
1484 cris_update_cc_x(dc);
1485 cris_update_result(dc, cpu_R[dc->op2]);
1486 } else {
1487 TCGv t0;
1488
1489 t0 = tcg_temp_new();
1490 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1491 cris_alu(dc, CC_OP_MOVE,
1492 cpu_R[dc->op2],
1493 cpu_R[dc->op2], t0, size);
1494 tcg_temp_free(t0);
1495 }
1496 return 2;
8170028d
TS		 1497}
1498
cf7e0c80 1499static int dec_scc_r(CPUCRISState *env, DisasContext *dc)
8170028d 1500{
7b5eff4d 1501 int cond = dc->op2;
8170028d 1502
7b5eff4d
EV		 1503 LOG_DIS("s%s $r%u\n",
1504 cc_name(cond), dc->op1);
8170028d 1505
7b5eff4d
EV		 1506 if (cond != CC_A) {
1507 int l1;
dceaf394 1508
7b5eff4d
EV		 1509 gen_tst_cc(dc, cpu_R[dc->op1], cond);
1510 l1 = gen_new_label();
1511 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[dc->op1], 0, l1);
1512 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1513 gen_set_label(l1);
1514 } else {
1515 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1516 }
8170028d 1517
7b5eff4d
EV		 1518 cris_cc_mask(dc, 0);
1519 return 2;
8170028d
TS		 1520}
1521
fb48f71b
EI		 1522static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t)
1523{
7b5eff4d
EV		 1524 if (size == 4) {
1525 t[0] = cpu_R[dc->op2];
1526 t[1] = cpu_R[dc->op1];
1527 } else {
1528 t[0] = tcg_temp_new();
1529 t[1] = tcg_temp_new();
1530 }
fb48f71b
EI		 1531}
1532
1533static inline void cris_alu_free_temps(DisasContext *dc, int size, TCGv *t)
1534{
7b5eff4d
EV		 1535 if (size != 4) {
1536 tcg_temp_free(t[0]);
1537 tcg_temp_free(t[1]);
1538 }
fb48f71b
EI		 1539}
1540
cf7e0c80 1541static int dec_and_r(CPUCRISState *env, DisasContext *dc)
8170028d 1542{
7b5eff4d
EV		 1543 TCGv t[2];
1544 int size = memsize_zz(dc);
8170028d 1545
7b5eff4d
EV		 1546 LOG_DIS("and.%c $r%u, $r%u\n",
1547 memsize_char(size), dc->op1, dc->op2);
fb48f71b 1548
7b5eff4d 1549 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7 1550
7b5eff4d
EV		 1551 cris_alu_alloc_temps(dc, size, t);
1552 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1553 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size);
1554 cris_alu_free_temps(dc, size, t);
1555 return 2;
8170028d
TS		 1556}
1557
cf7e0c80 1558static int dec_lz_r(CPUCRISState *env, DisasContext *dc)
8170028d 1559{
7b5eff4d
EV		 1560 TCGv t0;
1561 LOG_DIS("lz $r%u, $r%u\n",
1562 dc->op1, dc->op2);
1563 cris_cc_mask(dc, CC_MASK_NZ);
1564 t0 = tcg_temp_new();
1565 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0);
1566 cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1567 tcg_temp_free(t0);
1568 return 2;
8170028d
TS		 1569}
1570
cf7e0c80 1571static int dec_lsl_r(CPUCRISState *env, DisasContext *dc)
8170028d 1572{
7b5eff4d
EV		 1573 TCGv t[2];
1574 int size = memsize_zz(dc);
8170028d 1575
7b5eff4d
EV		 1576 LOG_DIS("lsl.%c $r%u, $r%u\n",
1577 memsize_char(size), dc->op1, dc->op2);
30abcfc7 1578
7b5eff4d
EV		 1579 cris_cc_mask(dc, CC_MASK_NZ);
1580 cris_alu_alloc_temps(dc, size, t);
1581 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1582 tcg_gen_andi_tl(t[1], t[1], 63);
1583 cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size);
1584 cris_alu_alloc_temps(dc, size, t);
1585 return 2;
8170028d
TS		 1586}
1587
cf7e0c80 1588static int dec_lsr_r(CPUCRISState *env, DisasContext *dc)
8170028d 1589{
7b5eff4d
EV		 1590 TCGv t[2];
1591 int size = memsize_zz(dc);
8170028d 1592
7b5eff4d
EV		 1593 LOG_DIS("lsr.%c $r%u, $r%u\n",
1594 memsize_char(size), dc->op1, dc->op2);
30abcfc7 1595
7b5eff4d
EV		 1596 cris_cc_mask(dc, CC_MASK_NZ);
1597 cris_alu_alloc_temps(dc, size, t);
1598 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1599 tcg_gen_andi_tl(t[1], t[1], 63);
1600 cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size);
1601 cris_alu_free_temps(dc, size, t);
1602 return 2;
8170028d
TS		 1603}
1604
cf7e0c80 1605static int dec_asr_r(CPUCRISState *env, DisasContext *dc)
8170028d 1606{
7b5eff4d
EV		 1607 TCGv t[2];
1608 int size = memsize_zz(dc);
8170028d 1609
7b5eff4d
EV		 1610 LOG_DIS("asr.%c $r%u, $r%u\n",
1611 memsize_char(size), dc->op1, dc->op2);
30abcfc7 1612
7b5eff4d
EV		 1613 cris_cc_mask(dc, CC_MASK_NZ);
1614 cris_alu_alloc_temps(dc, size, t);
1615 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1616 tcg_gen_andi_tl(t[1], t[1], 63);
1617 cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size);
1618 cris_alu_free_temps(dc, size, t);
1619 return 2;
8170028d
TS		 1620}
1621
cf7e0c80 1622static int dec_muls_r(CPUCRISState *env, DisasContext *dc)
8170028d 1623{
7b5eff4d
EV		 1624 TCGv t[2];
1625 int size = memsize_zz(dc);
8170028d 1626
7b5eff4d
EV		 1627 LOG_DIS("muls.%c $r%u, $r%u\n",
1628 memsize_char(size), dc->op1, dc->op2);
1629 cris_cc_mask(dc, CC_MASK_NZV);
1630 cris_alu_alloc_temps(dc, size, t);
1631 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
30abcfc7 1632
7b5eff4d
EV		 1633 cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4);
1634 cris_alu_free_temps(dc, size, t);
1635 return 2;
8170028d
TS		 1636}
1637
cf7e0c80 1638static int dec_mulu_r(CPUCRISState *env, DisasContext *dc)
8170028d 1639{
7b5eff4d
EV		 1640 TCGv t[2];
1641 int size = memsize_zz(dc);
8170028d 1642
7b5eff4d
EV		 1643 LOG_DIS("mulu.%c $r%u, $r%u\n",
1644 memsize_char(size), dc->op1, dc->op2);
1645 cris_cc_mask(dc, CC_MASK_NZV);
1646 cris_alu_alloc_temps(dc, size, t);
1647 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
30abcfc7 1648
7b5eff4d
EV		 1649 cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4);
1650 cris_alu_alloc_temps(dc, size, t);
1651 return 2;
8170028d
TS		 1652}
1653
1654
cf7e0c80 1655static int dec_dstep_r(CPUCRISState *env, DisasContext *dc)
8170028d 1656{
7b5eff4d
EV		 1657 LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2);
1658 cris_cc_mask(dc, CC_MASK_NZ);
1659 cris_alu(dc, CC_OP_DSTEP,
1660 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1661 return 2;
8170028d
TS		 1662}
1663
cf7e0c80 1664static int dec_xor_r(CPUCRISState *env, DisasContext *dc)
8170028d 1665{
7b5eff4d
EV		 1666 TCGv t[2];
1667 int size = memsize_zz(dc);
1668 LOG_DIS("xor.%c $r%u, $r%u\n",
1669 memsize_char(size), dc->op1, dc->op2);
1670 BUG_ON(size != 4); /* xor is dword. */
1671 cris_cc_mask(dc, CC_MASK_NZ);
1672 cris_alu_alloc_temps(dc, size, t);
1673 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
30abcfc7 1674
7b5eff4d
EV		 1675 cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4);
1676 cris_alu_free_temps(dc, size, t);
1677 return 2;
8170028d
TS		 1678}
1679
cf7e0c80 1680static int dec_bound_r(CPUCRISState *env, DisasContext *dc)
8170028d 1681{
7b5eff4d
EV		 1682 TCGv l0;
1683 int size = memsize_zz(dc);
1684 LOG_DIS("bound.%c $r%u, $r%u\n",
1685 memsize_char(size), dc->op1, dc->op2);
1686 cris_cc_mask(dc, CC_MASK_NZ);
1687 l0 = tcg_temp_local_new();
1688 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0);
1689 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4);
1690 tcg_temp_free(l0);
1691 return 2;
8170028d
TS		 1692}
1693
cf7e0c80 1694static int dec_cmp_r(CPUCRISState *env, DisasContext *dc)
8170028d 1695{
7b5eff4d
EV		 1696 TCGv t[2];
1697 int size = memsize_zz(dc);
1698 LOG_DIS("cmp.%c $r%u, $r%u\n",
1699 memsize_char(size), dc->op1, dc->op2);
1700 cris_cc_mask(dc, CC_MASK_NZVC);
1701 cris_alu_alloc_temps(dc, size, t);
1702 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
30abcfc7 1703
7b5eff4d
EV		 1704 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size);
1705 cris_alu_free_temps(dc, size, t);
1706 return 2;
8170028d
TS		 1707}
1708
cf7e0c80 1709static int dec_abs_r(CPUCRISState *env, DisasContext *dc)
8170028d 1710{
7b5eff4d 1711 TCGv t0;
3157a0a9 1712
7b5eff4d
EV		 1713 LOG_DIS("abs $r%u, $r%u\n",
1714 dc->op1, dc->op2);
1715 cris_cc_mask(dc, CC_MASK_NZ);
3157a0a9 1716
7b5eff4d
EV		 1717 t0 = tcg_temp_new();
1718 tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31);
1719 tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0);
1720 tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0);
1721 tcg_temp_free(t0);
7dcfb089 1722
7b5eff4d
EV		 1723 cris_alu(dc, CC_OP_MOVE,
1724 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1725 return 2;
8170028d
TS		 1726}
1727
cf7e0c80 1728static int dec_add_r(CPUCRISState *env, DisasContext *dc)
8170028d 1729{
7b5eff4d
EV		 1730 TCGv t[2];
1731 int size = memsize_zz(dc);
1732 LOG_DIS("add.%c $r%u, $r%u\n",
1733 memsize_char(size), dc->op1, dc->op2);
1734 cris_cc_mask(dc, CC_MASK_NZVC);
1735 cris_alu_alloc_temps(dc, size, t);
1736 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
30abcfc7 1737
7b5eff4d
EV		 1738 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size);
1739 cris_alu_free_temps(dc, size, t);
1740 return 2;
8170028d
TS		 1741}
1742
cf7e0c80 1743static int dec_addc_r(CPUCRISState *env, DisasContext *dc)
8170028d 1744{
7b5eff4d
EV		 1745 LOG_DIS("addc $r%u, $r%u\n",
1746 dc->op1, dc->op2);
1747 cris_evaluate_flags(dc);
1748 /* Set for this insn. */
1749 dc->flagx_known = 1;
1750 dc->flags_x = X_FLAG;
a8cf66bb 1751
7b5eff4d
EV		 1752 cris_cc_mask(dc, CC_MASK_NZVC);
1753 cris_alu(dc, CC_OP_ADDC,
1754 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1755 return 2;
8170028d
TS		 1756}
1757
cf7e0c80 1758static int dec_mcp_r(CPUCRISState *env, DisasContext *dc)
8170028d 1759{
7b5eff4d
EV		 1760 LOG_DIS("mcp $p%u, $r%u\n",
1761 dc->op2, dc->op1);
1762 cris_evaluate_flags(dc);
1763 cris_cc_mask(dc, CC_MASK_RNZV);
1764 cris_alu(dc, CC_OP_MCP,
1765 cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
1766 return 2;
8170028d
TS		 1767}
1768
1769#if DISAS_CRIS
1770static char * swapmode_name(int mode, char *modename) {
7b5eff4d
EV		 1771 int i = 0;
1772 if (mode & 8) {
1773 modename[i++] = 'n';
1774 }
1775 if (mode & 4) {
1776 modename[i++] = 'w';
1777 }
1778 if (mode & 2) {
1779 modename[i++] = 'b';
1780 }
1781 if (mode & 1) {
1782 modename[i++] = 'r';
1783 }
1784 modename[i++] = 0;
1785 return modename;
8170028d
TS		 1786}
1787#endif
1788
cf7e0c80 1789static int dec_swap_r(CPUCRISState *env, DisasContext *dc)
8170028d 1790{
7b5eff4d 1791 TCGv t0;
cf1d97f0 1792#if DISAS_CRIS
7b5eff4d 1793 char modename[4];
cf1d97f0 1794#endif
7b5eff4d
EV		 1795 LOG_DIS("swap%s $r%u\n",
1796 swapmode_name(dc->op2, modename), dc->op1);
1797
1798 cris_cc_mask(dc, CC_MASK_NZ);
1799 t0 = tcg_temp_new();
08397c4b 1800 tcg_gen_mov_tl(t0, cpu_R[dc->op1]);
7b5eff4d
EV		 1801 if (dc->op2 & 8) {
1802 tcg_gen_not_tl(t0, t0);
1803 }
1804 if (dc->op2 & 4) {
1805 t_gen_swapw(t0, t0);
1806 }
1807 if (dc->op2 & 2) {
1808 t_gen_swapb(t0, t0);
1809 }
1810 if (dc->op2 & 1) {
1811 t_gen_swapr(t0, t0);
1812 }
1813 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op1], cpu_R[dc->op1], t0, 4);
1814 tcg_temp_free(t0);
1815 return 2;
8170028d
TS		 1816}
1817
cf7e0c80 1818static int dec_or_r(CPUCRISState *env, DisasContext *dc)
8170028d 1819{
7b5eff4d
EV		 1820 TCGv t[2];
1821 int size = memsize_zz(dc);
1822 LOG_DIS("or.%c $r%u, $r%u\n",
1823 memsize_char(size), dc->op1, dc->op2);
1824 cris_cc_mask(dc, CC_MASK_NZ);
1825 cris_alu_alloc_temps(dc, size, t);
1826 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1827 cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size);
1828 cris_alu_free_temps(dc, size, t);
1829 return 2;
8170028d
TS		 1830}
1831
cf7e0c80 1832static int dec_addi_r(CPUCRISState *env, DisasContext *dc)
8170028d 1833{
7b5eff4d
EV		 1834 TCGv t0;
1835 LOG_DIS("addi.%c $r%u, $r%u\n",
1836 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1837 cris_cc_mask(dc, 0);
1838 t0 = tcg_temp_new();
1839 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1840 tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0);
1841 tcg_temp_free(t0);
1842 return 2;
8170028d
TS		 1843}
1844
cf7e0c80 1845static int dec_addi_acr(CPUCRISState *env, DisasContext *dc)
8170028d 1846{
7b5eff4d
EV		 1847 TCGv t0;
1848 LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
1849 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1850 cris_cc_mask(dc, 0);
1851 t0 = tcg_temp_new();
1852 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1853 tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0);
1854 tcg_temp_free(t0);
1855 return 2;
8170028d
TS		 1856}
1857
cf7e0c80 1858static int dec_neg_r(CPUCRISState *env, DisasContext *dc)
8170028d 1859{
7b5eff4d
EV		 1860 TCGv t[2];
1861 int size = memsize_zz(dc);
1862 LOG_DIS("neg.%c $r%u, $r%u\n",
1863 memsize_char(size), dc->op1, dc->op2);
1864 cris_cc_mask(dc, CC_MASK_NZVC);
1865 cris_alu_alloc_temps(dc, size, t);
1866 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
30abcfc7 1867
7b5eff4d
EV		 1868 cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size);
1869 cris_alu_free_temps(dc, size, t);
1870 return 2;
8170028d
TS		 1871}
1872
cf7e0c80 1873static int dec_btst_r(CPUCRISState *env, DisasContext *dc)
8170028d 1874{
7b5eff4d
EV		 1875 LOG_DIS("btst $r%u, $r%u\n",
1876 dc->op1, dc->op2);
1877 cris_cc_mask(dc, CC_MASK_NZ);
1878 cris_evaluate_flags(dc);
febc9920 1879 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
7b5eff4d
EV		 1880 cpu_R[dc->op1], cpu_PR[PR_CCS]);
1881 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
1882 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1883 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1884 dc->flags_uptodate = 1;
1885 return 2;
8170028d
TS		 1886}
1887
cf7e0c80 1888static int dec_sub_r(CPUCRISState *env, DisasContext *dc)
8170028d 1889{
7b5eff4d
EV		 1890 TCGv t[2];
1891 int size = memsize_zz(dc);
1892 LOG_DIS("sub.%c $r%u, $r%u\n",
1893 memsize_char(size), dc->op1, dc->op2);
1894 cris_cc_mask(dc, CC_MASK_NZVC);
1895 cris_alu_alloc_temps(dc, size, t);
1896 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1897 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size);
1898 cris_alu_free_temps(dc, size, t);
1899 return 2;
8170028d
TS		 1900}
1901
1902/* Zero extension. From size to dword. */
cf7e0c80 1903static int dec_movu_r(CPUCRISState *env, DisasContext *dc)
8170028d 1904{
7b5eff4d
EV		 1905 TCGv t0;
1906 int size = memsize_z(dc);
1907 LOG_DIS("movu.%c $r%u, $r%u\n",
1908 memsize_char(size),
1909 dc->op1, dc->op2);
8170028d 1910
7b5eff4d
EV		 1911 cris_cc_mask(dc, CC_MASK_NZ);
1912 t0 = tcg_temp_new();
1913 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1914 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1915 tcg_temp_free(t0);
1916 return 2;
8170028d
TS		 1917}
1918
1919/* Sign extension. From size to dword. */
cf7e0c80 1920static int dec_movs_r(CPUCRISState *env, DisasContext *dc)
8170028d 1921{
7b5eff4d
EV		 1922 TCGv t0;
1923 int size = memsize_z(dc);
1924 LOG_DIS("movs.%c $r%u, $r%u\n",
1925 memsize_char(size),
1926 dc->op1, dc->op2);
8170028d 1927
7b5eff4d
EV		 1928 cris_cc_mask(dc, CC_MASK_NZ);
1929 t0 = tcg_temp_new();
1930 /* Size can only be qi or hi. */
1931 t_gen_sext(t0, cpu_R[dc->op1], size);
1932 cris_alu(dc, CC_OP_MOVE,
1933 cpu_R[dc->op2], cpu_R[dc->op1], t0, 4);
1934 tcg_temp_free(t0);
1935 return 2;
8170028d
TS		 1936}
1937
1938/* zero extension. From size to dword. */
cf7e0c80 1939static int dec_addu_r(CPUCRISState *env, DisasContext *dc)
8170028d 1940{
7b5eff4d
EV		 1941 TCGv t0;
1942 int size = memsize_z(dc);
1943 LOG_DIS("addu.%c $r%u, $r%u\n",
1944 memsize_char(size),
1945 dc->op1, dc->op2);
8170028d 1946
7b5eff4d
EV		 1947 cris_cc_mask(dc, CC_MASK_NZVC);
1948 t0 = tcg_temp_new();
1949 /* Size can only be qi or hi. */
1950 t_gen_zext(t0, cpu_R[dc->op1], size);
1951 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1952 tcg_temp_free(t0);
1953 return 2;
8170028d 1954}
05ba7d5f 1955
8170028d 1956/* Sign extension. From size to dword. */
cf7e0c80 1957static int dec_adds_r(CPUCRISState *env, DisasContext *dc)
8170028d 1958{
7b5eff4d
EV		 1959 TCGv t0;
1960 int size = memsize_z(dc);
1961 LOG_DIS("adds.%c $r%u, $r%u\n",
1962 memsize_char(size),
1963 dc->op1, dc->op2);
8170028d 1964
7b5eff4d
EV		 1965 cris_cc_mask(dc, CC_MASK_NZVC);
1966 t0 = tcg_temp_new();
1967 /* Size can only be qi or hi. */
1968 t_gen_sext(t0, cpu_R[dc->op1], size);
1969 cris_alu(dc, CC_OP_ADD,
1970 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1971 tcg_temp_free(t0);
1972 return 2;
8170028d
TS		 1973}
1974
1975/* Zero extension. From size to dword. */
cf7e0c80 1976static int dec_subu_r(CPUCRISState *env, DisasContext *dc)
8170028d 1977{
7b5eff4d
EV		 1978 TCGv t0;
1979 int size = memsize_z(dc);
1980 LOG_DIS("subu.%c $r%u, $r%u\n",
1981 memsize_char(size),
1982 dc->op1, dc->op2);
8170028d 1983
7b5eff4d
EV		 1984 cris_cc_mask(dc, CC_MASK_NZVC);
1985 t0 = tcg_temp_new();
1986 /* Size can only be qi or hi. */
1987 t_gen_zext(t0, cpu_R[dc->op1], size);
1988 cris_alu(dc, CC_OP_SUB,
1989 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1990 tcg_temp_free(t0);
1991 return 2;
8170028d
TS		 1992}
1993
1994/* Sign extension. From size to dword. */
cf7e0c80 1995static int dec_subs_r(CPUCRISState *env, DisasContext *dc)
8170028d 1996{
7b5eff4d
EV		 1997 TCGv t0;
1998 int size = memsize_z(dc);
1999 LOG_DIS("subs.%c $r%u, $r%u\n",
2000 memsize_char(size),
2001 dc->op1, dc->op2);
8170028d 2002
7b5eff4d
EV		 2003 cris_cc_mask(dc, CC_MASK_NZVC);
2004 t0 = tcg_temp_new();
2005 /* Size can only be qi or hi. */
2006 t_gen_sext(t0, cpu_R[dc->op1], size);
2007 cris_alu(dc, CC_OP_SUB,
2008 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2009 tcg_temp_free(t0);
2010 return 2;
8170028d
TS		 2011}
2012
cf7e0c80 2013static int dec_setclrf(CPUCRISState *env, DisasContext *dc)
8170028d 2014{
7b5eff4d
EV		 2015 uint32_t flags;
2016 int set = (~dc->opcode >> 2) & 1;
2017
2018
2019 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
2020 | EXTRACT_FIELD(dc->ir, 0, 3);
2021 if (set && flags == 0) {
2022 LOG_DIS("nop\n");
2023 return 2;
2024 } else if (!set && (flags & 0x20)) {
2025 LOG_DIS("di\n");
2026 } else {
2027 LOG_DIS("%sf %x\n", set ? "set" : "clr", flags);
2028 }
2029
2030 /* User space is not allowed to touch these. Silently ignore. */
2031 if (dc->tb_flags & U_FLAG) {
2032 flags &= ~(S_FLAG | I_FLAG | U_FLAG);
2033 }
2034
2035 if (flags & X_FLAG) {
2036 dc->flagx_known = 1;
2037 if (set) {
2038 dc->flags_x = X_FLAG;
2039 } else {
2040 dc->flags_x = 0;
2041 }
2042 }
2043
2044 /* Break the TB if any of the SPI flag changes. */
2045 if (flags & (P_FLAG | S_FLAG)) {
2046 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2047 dc->is_jmp = DISAS_UPDATE;
2048 dc->cpustate_changed = 1;
2049 }
2050
2051 /* For the I flag, only act on posedge. */
2052 if ((flags & I_FLAG)) {
2053 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2054 dc->is_jmp = DISAS_UPDATE;
2055 dc->cpustate_changed = 1;
2056 }
2057
2058
2059 /* Simply decode the flags. */
2060 cris_evaluate_flags(dc);
2061 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2062 cris_update_cc_x(dc);
2063 tcg_gen_movi_tl(cc_op, dc->cc_op);
2064
2065 if (set) {
2066 if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) {
2067 /* Enter user mode. */
2068 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
2069 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
2070 dc->cpustate_changed = 1;
2071 }
2072 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
2073 } else {
2074 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
2075 }
2076
2077 dc->flags_uptodate = 1;
2078 dc->clear_x = 0;
2079 return 2;
8170028d
TS		 2080}
2081
cf7e0c80 2082static int dec_move_rs(CPUCRISState *env, DisasContext *dc)
8170028d 2083{
7b5eff4d
EV		 2084 LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
2085 cris_cc_mask(dc, 0);
febc9920
AJ		 2086 gen_helper_movl_sreg_reg(cpu_env, tcg_const_tl(dc->op2),
2087 tcg_const_tl(dc->op1));
7b5eff4d 2088 return 2;
8170028d 2089}
cf7e0c80 2090static int dec_move_sr(CPUCRISState *env, DisasContext *dc)
8170028d 2091{
7b5eff4d
EV		 2092 LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
2093 cris_cc_mask(dc, 0);
febc9920
AJ		 2094 gen_helper_movl_reg_sreg(cpu_env, tcg_const_tl(dc->op1),
2095 tcg_const_tl(dc->op2));
7b5eff4d 2096 return 2;
8170028d 2097}
dceaf394 2098
cf7e0c80 2099static int dec_move_rp(CPUCRISState *env, DisasContext *dc)
8170028d 2100{
7b5eff4d
EV		 2101 TCGv t[2];
2102 LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2);
2103 cris_cc_mask(dc, 0);
2104
2105 t[0] = tcg_temp_new();
2106 if (dc->op2 == PR_CCS) {
2107 cris_evaluate_flags(dc);
08397c4b 2108 tcg_gen_mov_tl(t[0], cpu_R[dc->op1]);
7b5eff4d
EV		 2109 if (dc->tb_flags & U_FLAG) {
2110 t[1] = tcg_temp_new();
2111 /* User space is not allowed to touch all flags. */
2112 tcg_gen_andi_tl(t[0], t[0], 0x39f);
2113 tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f);
2114 tcg_gen_or_tl(t[0], t[1], t[0]);
2115 tcg_temp_free(t[1]);
2116 }
2117 } else {
08397c4b 2118 tcg_gen_mov_tl(t[0], cpu_R[dc->op1]);
7b5eff4d
EV		 2119 }
2120
2121 t_gen_mov_preg_TN(dc, dc->op2, t[0]);
2122 if (dc->op2 == PR_CCS) {
2123 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2124 dc->flags_uptodate = 1;
2125 }
2126 tcg_temp_free(t[0]);
2127 return 2;
8170028d 2128}
cf7e0c80 2129static int dec_move_pr(CPUCRISState *env, DisasContext *dc)
8170028d 2130{
7b5eff4d
EV		 2131 TCGv t0;
2132 LOG_DIS("move $p%u, $r%u\n", dc->op2, dc->op1);
2133 cris_cc_mask(dc, 0);
2a44f7f1 2134
7b5eff4d
EV		 2135 if (dc->op2 == PR_CCS) {
2136 cris_evaluate_flags(dc);
2137 }
2a44f7f1 2138
7b5eff4d
EV		 2139 if (dc->op2 == PR_DZ) {
2140 tcg_gen_movi_tl(cpu_R[dc->op1], 0);
2141 } else {
2142 t0 = tcg_temp_new();
2143 t_gen_mov_TN_preg(t0, dc->op2);
2144 cris_alu(dc, CC_OP_MOVE,
2145 cpu_R[dc->op1], cpu_R[dc->op1], t0,
2146 preg_sizes[dc->op2]);
2147 tcg_temp_free(t0);
2148 }
2149 return 2;
8170028d
TS		 2150}
2151
cf7e0c80 2152static int dec_move_mr(CPUCRISState *env, DisasContext *dc)
8170028d 2153{
7b5eff4d
EV		 2154 int memsize = memsize_zz(dc);
2155 int insn_len;
2156 LOG_DIS("move.%c [$r%u%s, $r%u\n",
2157 memsize_char(memsize),
2158 dc->op1, dc->postinc ? "+]" : "]",
2159 dc->op2);
2160
2161 if (memsize == 4) {
2162 insn_len = dec_prep_move_m(env, dc, 0, 4, cpu_R[dc->op2]);
2163 cris_cc_mask(dc, CC_MASK_NZ);
2164 cris_update_cc_op(dc, CC_OP_MOVE, 4);
2165 cris_update_cc_x(dc);
2166 cris_update_result(dc, cpu_R[dc->op2]);
2167 } else {
2168 TCGv t0;
2169
2170 t0 = tcg_temp_new();
2171 insn_len = dec_prep_move_m(env, dc, 0, memsize, t0);
2172 cris_cc_mask(dc, CC_MASK_NZ);
2173 cris_alu(dc, CC_OP_MOVE,
2174 cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize);
2175 tcg_temp_free(t0);
2176 }
2177 do_postinc(dc, memsize);
2178 return insn_len;
8170028d
TS		 2179}
2180
31c18d87
EI		 2181static inline void cris_alu_m_alloc_temps(TCGv *t)
2182{
7b5eff4d
EV		 2183 t[0] = tcg_temp_new();
2184 t[1] = tcg_temp_new();
31c18d87
EI		 2185}
2186
2187static inline void cris_alu_m_free_temps(TCGv *t)
2188{
7b5eff4d
EV		 2189 tcg_temp_free(t[0]);
2190 tcg_temp_free(t[1]);
31c18d87
EI		 2191}
2192
cf7e0c80 2193static int dec_movs_m(CPUCRISState *env, DisasContext *dc)
8170028d 2194{
7b5eff4d
EV		 2195 TCGv t[2];
2196 int memsize = memsize_z(dc);
2197 int insn_len;
2198 LOG_DIS("movs.%c [$r%u%s, $r%u\n",
2199 memsize_char(memsize),
2200 dc->op1, dc->postinc ? "+]" : "]",
2201 dc->op2);
8170028d 2202
7b5eff4d
EV		 2203 cris_alu_m_alloc_temps(t);
2204 /* sign extend. */
cf7e0c80 2205 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
7b5eff4d
EV		 2206 cris_cc_mask(dc, CC_MASK_NZ);
2207 cris_alu(dc, CC_OP_MOVE,
2208 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2209 do_postinc(dc, memsize);
2210 cris_alu_m_free_temps(t);
2211 return insn_len;
8170028d
TS		 2212}
2213
cf7e0c80 2214static int dec_addu_m(CPUCRISState *env, DisasContext *dc)
8170028d 2215{
7b5eff4d
EV		 2216 TCGv t[2];
2217 int memsize = memsize_z(dc);
2218 int insn_len;
2219 LOG_DIS("addu.%c [$r%u%s, $r%u\n",
2220 memsize_char(memsize),
2221 dc->op1, dc->postinc ? "+]" : "]",
2222 dc->op2);
8170028d 2223
7b5eff4d
EV		 2224 cris_alu_m_alloc_temps(t);
2225 /* sign extend. */
cf7e0c80 2226 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2227 cris_cc_mask(dc, CC_MASK_NZVC);
2228 cris_alu(dc, CC_OP_ADD,
2229 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2230 do_postinc(dc, memsize);
2231 cris_alu_m_free_temps(t);
2232 return insn_len;
8170028d
TS		 2233}
2234
cf7e0c80 2235static int dec_adds_m(CPUCRISState *env, DisasContext *dc)
8170028d 2236{
7b5eff4d
EV		 2237 TCGv t[2];
2238 int memsize = memsize_z(dc);
2239 int insn_len;
2240 LOG_DIS("adds.%c [$r%u%s, $r%u\n",
2241 memsize_char(memsize),
2242 dc->op1, dc->postinc ? "+]" : "]",
2243 dc->op2);
8170028d 2244
7b5eff4d
EV		 2245 cris_alu_m_alloc_temps(t);
2246 /* sign extend. */
cf7e0c80 2247 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
7b5eff4d
EV		 2248 cris_cc_mask(dc, CC_MASK_NZVC);
2249 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2250 do_postinc(dc, memsize);
2251 cris_alu_m_free_temps(t);
2252 return insn_len;
8170028d
TS		 2253}
2254
cf7e0c80 2255static int dec_subu_m(CPUCRISState *env, DisasContext *dc)
8170028d 2256{
7b5eff4d
EV		 2257 TCGv t[2];
2258 int memsize = memsize_z(dc);
2259 int insn_len;
2260 LOG_DIS("subu.%c [$r%u%s, $r%u\n",
2261 memsize_char(memsize),
2262 dc->op1, dc->postinc ? "+]" : "]",
2263 dc->op2);
8170028d 2264
7b5eff4d
EV		 2265 cris_alu_m_alloc_temps(t);
2266 /* sign extend. */
cf7e0c80 2267 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2268 cris_cc_mask(dc, CC_MASK_NZVC);
2269 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2270 do_postinc(dc, memsize);
2271 cris_alu_m_free_temps(t);
2272 return insn_len;
8170028d
TS		 2273}
2274
cf7e0c80 2275static int dec_subs_m(CPUCRISState *env, DisasContext *dc)
8170028d 2276{
7b5eff4d
EV		 2277 TCGv t[2];
2278 int memsize = memsize_z(dc);
2279 int insn_len;
2280 LOG_DIS("subs.%c [$r%u%s, $r%u\n",
2281 memsize_char(memsize),
2282 dc->op1, dc->postinc ? "+]" : "]",
2283 dc->op2);
8170028d 2284
7b5eff4d
EV		 2285 cris_alu_m_alloc_temps(t);
2286 /* sign extend. */
cf7e0c80 2287 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
7b5eff4d
EV		 2288 cris_cc_mask(dc, CC_MASK_NZVC);
2289 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2290 do_postinc(dc, memsize);
2291 cris_alu_m_free_temps(t);
2292 return insn_len;
8170028d
TS		 2293}
2294
cf7e0c80 2295static int dec_movu_m(CPUCRISState *env, DisasContext *dc)
8170028d 2296{
7b5eff4d
EV		 2297 TCGv t[2];
2298 int memsize = memsize_z(dc);
2299 int insn_len;
8170028d 2300
7b5eff4d
EV		 2301 LOG_DIS("movu.%c [$r%u%s, $r%u\n",
2302 memsize_char(memsize),
2303 dc->op1, dc->postinc ? "+]" : "]",
2304 dc->op2);
8170028d 2305
7b5eff4d 2306 cris_alu_m_alloc_temps(t);
cf7e0c80 2307 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2308 cris_cc_mask(dc, CC_MASK_NZ);
2309 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2310 do_postinc(dc, memsize);
2311 cris_alu_m_free_temps(t);
2312 return insn_len;
8170028d
TS		 2313}
2314
cf7e0c80 2315static int dec_cmpu_m(CPUCRISState *env, DisasContext *dc)
8170028d 2316{
7b5eff4d
EV		 2317 TCGv t[2];
2318 int memsize = memsize_z(dc);
2319 int insn_len;
2320 LOG_DIS("cmpu.%c [$r%u%s, $r%u\n",
2321 memsize_char(memsize),
2322 dc->op1, dc->postinc ? "+]" : "]",
2323 dc->op2);
8170028d 2324
7b5eff4d 2325 cris_alu_m_alloc_temps(t);
cf7e0c80 2326 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2327 cris_cc_mask(dc, CC_MASK_NZVC);
2328 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2329 do_postinc(dc, memsize);
2330 cris_alu_m_free_temps(t);
2331 return insn_len;
8170028d
TS		 2332}
2333
cf7e0c80 2334static int dec_cmps_m(CPUCRISState *env, DisasContext *dc)
8170028d 2335{
7b5eff4d
EV		 2336 TCGv t[2];
2337 int memsize = memsize_z(dc);
2338 int insn_len;
2339 LOG_DIS("cmps.%c [$r%u%s, $r%u\n",
2340 memsize_char(memsize),
2341 dc->op1, dc->postinc ? "+]" : "]",
2342 dc->op2);
8170028d 2343
7b5eff4d 2344 cris_alu_m_alloc_temps(t);
cf7e0c80 2345 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
7b5eff4d
EV		 2346 cris_cc_mask(dc, CC_MASK_NZVC);
2347 cris_alu(dc, CC_OP_CMP,
2348 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2349 memsize_zz(dc));
2350 do_postinc(dc, memsize);
2351 cris_alu_m_free_temps(t);
2352 return insn_len;
8170028d
TS		 2353}
2354
cf7e0c80 2355static int dec_cmp_m(CPUCRISState *env, DisasContext *dc)
8170028d 2356{
7b5eff4d
EV		 2357 TCGv t[2];
2358 int memsize = memsize_zz(dc);
2359 int insn_len;
2360 LOG_DIS("cmp.%c [$r%u%s, $r%u\n",
2361 memsize_char(memsize),
2362 dc->op1, dc->postinc ? "+]" : "]",
2363 dc->op2);
8170028d 2364
7b5eff4d 2365 cris_alu_m_alloc_temps(t);
cf7e0c80 2366 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2367 cris_cc_mask(dc, CC_MASK_NZVC);
2368 cris_alu(dc, CC_OP_CMP,
2369 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2370 memsize_zz(dc));
2371 do_postinc(dc, memsize);
2372 cris_alu_m_free_temps(t);
2373 return insn_len;
8170028d
TS		 2374}
2375
cf7e0c80 2376static int dec_test_m(CPUCRISState *env, DisasContext *dc)
8170028d 2377{
7b5eff4d
EV		 2378 TCGv t[2];
2379 int memsize = memsize_zz(dc);
2380 int insn_len;
2381 LOG_DIS("test.%c [$r%u%s] op2=%x\n",
2382 memsize_char(memsize),
2383 dc->op1, dc->postinc ? "+]" : "]",
2384 dc->op2);
8170028d 2385
7b5eff4d 2386 cris_evaluate_flags(dc);
dceaf394 2387
7b5eff4d 2388 cris_alu_m_alloc_temps(t);
cf7e0c80 2389 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2390 cris_cc_mask(dc, CC_MASK_NZ);
2391 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
b41f7df0 2392
7b5eff4d
EV		 2393 cris_alu(dc, CC_OP_CMP,
2394 cpu_R[dc->op2], t[1], tcg_const_tl(0), memsize_zz(dc));
2395 do_postinc(dc, memsize);
2396 cris_alu_m_free_temps(t);
2397 return insn_len;
8170028d
TS		 2398}
2399
cf7e0c80 2400static int dec_and_m(CPUCRISState *env, DisasContext *dc)
8170028d 2401{
7b5eff4d
EV		 2402 TCGv t[2];
2403 int memsize = memsize_zz(dc);
2404 int insn_len;
2405 LOG_DIS("and.%c [$r%u%s, $r%u\n",
2406 memsize_char(memsize),
2407 dc->op1, dc->postinc ? "+]" : "]",
2408 dc->op2);
8170028d 2409
7b5eff4d 2410 cris_alu_m_alloc_temps(t);
cf7e0c80 2411 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2412 cris_cc_mask(dc, CC_MASK_NZ);
2413 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2414 do_postinc(dc, memsize);
2415 cris_alu_m_free_temps(t);
2416 return insn_len;
8170028d
TS		 2417}
2418
cf7e0c80 2419static int dec_add_m(CPUCRISState *env, DisasContext *dc)
8170028d 2420{
7b5eff4d
EV		 2421 TCGv t[2];
2422 int memsize = memsize_zz(dc);
2423 int insn_len;
2424 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2425 memsize_char(memsize),
2426 dc->op1, dc->postinc ? "+]" : "]",
2427 dc->op2);
8170028d 2428
7b5eff4d 2429 cris_alu_m_alloc_temps(t);
cf7e0c80 2430 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2431 cris_cc_mask(dc, CC_MASK_NZVC);
2432 cris_alu(dc, CC_OP_ADD,
2433 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2434 do_postinc(dc, memsize);
2435 cris_alu_m_free_temps(t);
2436 return insn_len;
8170028d
TS		 2437}
2438
cf7e0c80 2439static int dec_addo_m(CPUCRISState *env, DisasContext *dc)
8170028d 2440{
7b5eff4d
EV		 2441 TCGv t[2];
2442 int memsize = memsize_zz(dc);
2443 int insn_len;
2444 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2445 memsize_char(memsize),
2446 dc->op1, dc->postinc ? "+]" : "]",
2447 dc->op2);
8170028d 2448
7b5eff4d 2449 cris_alu_m_alloc_temps(t);
cf7e0c80 2450 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
7b5eff4d
EV		 2451 cris_cc_mask(dc, 0);
2452 cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4);
2453 do_postinc(dc, memsize);
2454 cris_alu_m_free_temps(t);
2455 return insn_len;
8170028d
TS		 2456}
2457
cf7e0c80 2458static int dec_bound_m(CPUCRISState *env, DisasContext *dc)
8170028d 2459{
7b5eff4d
EV		 2460 TCGv l[2];
2461 int memsize = memsize_zz(dc);
2462 int insn_len;
2463 LOG_DIS("bound.%c [$r%u%s, $r%u\n",
2464 memsize_char(memsize),
2465 dc->op1, dc->postinc ? "+]" : "]",
2466 dc->op2);
8170028d 2467
7b5eff4d
EV		 2468 l[0] = tcg_temp_local_new();
2469 l[1] = tcg_temp_local_new();
cf7e0c80 2470 insn_len = dec_prep_alu_m(env, dc, 0, memsize, l[0], l[1]);
7b5eff4d
EV		 2471 cris_cc_mask(dc, CC_MASK_NZ);
2472 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4);
2473 do_postinc(dc, memsize);
2474 tcg_temp_free(l[0]);
2475 tcg_temp_free(l[1]);
2476 return insn_len;
8170028d
TS		 2477}
2478
cf7e0c80 2479static int dec_addc_mr(CPUCRISState *env, DisasContext *dc)
8170028d 2480{
7b5eff4d
EV		 2481 TCGv t[2];
2482 int insn_len = 2;
2483 LOG_DIS("addc [$r%u%s, $r%u\n",
2484 dc->op1, dc->postinc ? "+]" : "]",
2485 dc->op2);
8170028d 2486
7b5eff4d 2487 cris_evaluate_flags(dc);
a8cf66bb 2488
7b5eff4d
EV		 2489 /* Set for this insn. */
2490 dc->flagx_known = 1;
2491 dc->flags_x = X_FLAG;
a8cf66bb 2492
7b5eff4d 2493 cris_alu_m_alloc_temps(t);
cf7e0c80 2494 insn_len = dec_prep_alu_m(env, dc, 0, 4, t[0], t[1]);
7b5eff4d
EV		 2495 cris_cc_mask(dc, CC_MASK_NZVC);
2496 cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4);
2497 do_postinc(dc, 4);
2498 cris_alu_m_free_temps(t);
2499 return insn_len;
8170028d
TS		 2500}
2501
cf7e0c80 2502static int dec_sub_m(CPUCRISState *env, DisasContext *dc)
8170028d 2503{
7b5eff4d
EV		 2504 TCGv t[2];
2505 int memsize = memsize_zz(dc);
2506 int insn_len;
2507 LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2508 memsize_char(memsize),
2509 dc->op1, dc->postinc ? "+]" : "]",
2510 dc->op2, dc->ir, dc->zzsize);
8170028d 2511
7b5eff4d 2512 cris_alu_m_alloc_temps(t);
cf7e0c80 2513 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2514 cris_cc_mask(dc, CC_MASK_NZVC);
2515 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize);
2516 do_postinc(dc, memsize);
2517 cris_alu_m_free_temps(t);
2518 return insn_len;
8170028d
TS		 2519}
2520
cf7e0c80 2521static int dec_or_m(CPUCRISState *env, DisasContext *dc)
8170028d 2522{
7b5eff4d
EV		 2523 TCGv t[2];
2524 int memsize = memsize_zz(dc);
2525 int insn_len;
2526 LOG_DIS("or.%c [$r%u%s, $r%u pc=%x\n",
2527 memsize_char(memsize),
2528 dc->op1, dc->postinc ? "+]" : "]",
2529 dc->op2, dc->pc);
8170028d 2530
7b5eff4d 2531 cris_alu_m_alloc_temps(t);
cf7e0c80 2532 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2533 cris_cc_mask(dc, CC_MASK_NZ);
2534 cris_alu(dc, CC_OP_OR,
2535 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2536 do_postinc(dc, memsize);
2537 cris_alu_m_free_temps(t);
2538 return insn_len;
8170028d
TS		 2539}
2540
cf7e0c80 2541static int dec_move_mp(CPUCRISState *env, DisasContext *dc)
8170028d 2542{
7b5eff4d
EV		 2543 TCGv t[2];
2544 int memsize = memsize_zz(dc);
2545 int insn_len = 2;
8170028d 2546
7b5eff4d
EV		 2547 LOG_DIS("move.%c [$r%u%s, $p%u\n",
2548 memsize_char(memsize),
2549 dc->op1,
2550 dc->postinc ? "+]" : "]",
2551 dc->op2);
8170028d 2552
7b5eff4d 2553 cris_alu_m_alloc_temps(t);
cf7e0c80 2554 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2555 cris_cc_mask(dc, 0);
2556 if (dc->op2 == PR_CCS) {
2557 cris_evaluate_flags(dc);
2558 if (dc->tb_flags & U_FLAG) {
2559 /* User space is not allowed to touch all flags. */
2560 tcg_gen_andi_tl(t[1], t[1], 0x39f);
2561 tcg_gen_andi_tl(t[0], cpu_PR[PR_CCS], ~0x39f);
2562 tcg_gen_or_tl(t[1], t[0], t[1]);
2563 }
2564 }
b41f7df0 2565
7b5eff4d 2566 t_gen_mov_preg_TN(dc, dc->op2, t[1]);
8170028d 2567
7b5eff4d
EV		 2568 do_postinc(dc, memsize);
2569 cris_alu_m_free_temps(t);
2570 return insn_len;
8170028d
TS		 2571}
2572
cf7e0c80 2573static int dec_move_pm(CPUCRISState *env, DisasContext *dc)
8170028d 2574{
7b5eff4d
EV		 2575 TCGv t0;
2576 int memsize;
8170028d 2577
7b5eff4d 2578 memsize = preg_sizes[dc->op2];
8170028d 2579
7b5eff4d
EV		 2580 LOG_DIS("move.%c $p%u, [$r%u%s\n",
2581 memsize_char(memsize),
2582 dc->op2, dc->op1, dc->postinc ? "+]" : "]");
8170028d 2583
7b5eff4d
EV		 2584 /* prepare store. Address in T0, value in T1. */
2585 if (dc->op2 == PR_CCS) {
2586 cris_evaluate_flags(dc);
2587 }
2588 t0 = tcg_temp_new();
2589 t_gen_mov_TN_preg(t0, dc->op2);
2590 cris_flush_cc_state(dc);
2591 gen_store(dc, cpu_R[dc->op1], t0, memsize);
2592 tcg_temp_free(t0);
2593
2594 cris_cc_mask(dc, 0);
2595 if (dc->postinc) {
2596 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2597 }
2598 return 2;
8170028d
TS		 2599}
2600
cf7e0c80 2601static int dec_movem_mr(CPUCRISState *env, DisasContext *dc)
8170028d 2602{
7b5eff4d
EV		 2603 TCGv_i64 tmp[16];
2604 TCGv tmp32;
2605 TCGv addr;
2606 int i;
2607 int nr = dc->op2 + 1;
2608
2609 LOG_DIS("movem [$r%u%s, $r%u\n", dc->op1,
2610 dc->postinc ? "+]" : "]", dc->op2);
2611
2612 addr = tcg_temp_new();
2613 /* There are probably better ways of doing this. */
2614 cris_flush_cc_state(dc);
2615 for (i = 0; i < (nr >> 1); i++) {
2616 tmp[i] = tcg_temp_new_i64();
2617 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2618 gen_load64(dc, tmp[i], addr);
2619 }
2620 if (nr & 1) {
2621 tmp32 = tcg_temp_new_i32();
2622 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2623 gen_load(dc, tmp32, addr, 4, 0);
2624 } else {
2625 TCGV_UNUSED(tmp32);
2626 }
2627 tcg_temp_free(addr);
2628
2629 for (i = 0; i < (nr >> 1); i++) {
2630 tcg_gen_trunc_i64_i32(cpu_R[i * 2], tmp[i]);
2631 tcg_gen_shri_i64(tmp[i], tmp[i], 32);
2632 tcg_gen_trunc_i64_i32(cpu_R[i * 2 + 1], tmp[i]);
2633 tcg_temp_free_i64(tmp[i]);
2634 }
2635 if (nr & 1) {
2636 tcg_gen_mov_tl(cpu_R[dc->op2], tmp32);
2637 tcg_temp_free(tmp32);
2638 }
2639
2640 /* writeback the updated pointer value. */
2641 if (dc->postinc) {
2642 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4);
2643 }
2644
2645 /* gen_load might want to evaluate the previous insns flags. */
2646 cris_cc_mask(dc, 0);
2647 return 2;
8170028d
TS		 2648}
2649
cf7e0c80 2650static int dec_movem_rm(CPUCRISState *env, DisasContext *dc)
8170028d 2651{
7b5eff4d
EV		 2652 TCGv tmp;
2653 TCGv addr;
2654 int i;
2655
2656 LOG_DIS("movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2657 dc->postinc ? "+]" : "]");
2658
2659 cris_flush_cc_state(dc);
2660
2661 tmp = tcg_temp_new();
2662 addr = tcg_temp_new();
2663 tcg_gen_movi_tl(tmp, 4);
2664 tcg_gen_mov_tl(addr, cpu_R[dc->op1]);
2665 for (i = 0; i <= dc->op2; i++) {
2666 /* Displace addr. */
2667 /* Perform the store. */
2668 gen_store(dc, addr, cpu_R[i], 4);
2669 tcg_gen_add_tl(addr, addr, tmp);
2670 }
2671 if (dc->postinc) {
2672 tcg_gen_mov_tl(cpu_R[dc->op1], addr);
2673 }
2674 cris_cc_mask(dc, 0);
2675 tcg_temp_free(tmp);
2676 tcg_temp_free(addr);
2677 return 2;
8170028d
TS		 2678}
2679
cf7e0c80 2680static int dec_move_rm(CPUCRISState *env, DisasContext *dc)
8170028d 2681{
7b5eff4d 2682 int memsize;
8170028d 2683
7b5eff4d 2684 memsize = memsize_zz(dc);
8170028d 2685
7b5eff4d
EV		 2686 LOG_DIS("move.%c $r%u, [$r%u]\n",
2687 memsize_char(memsize), dc->op2, dc->op1);
8170028d 2688
7b5eff4d
EV		 2689 /* prepare store. */
2690 cris_flush_cc_state(dc);
2691 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
17ac9754 2692
7b5eff4d
EV		 2693 if (dc->postinc) {
2694 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2695 }
2696 cris_cc_mask(dc, 0);
2697 return 2;
8170028d
TS		 2698}
2699
cf7e0c80 2700static int dec_lapcq(CPUCRISState *env, DisasContext *dc)
8170028d 2701{
7b5eff4d
EV		 2702 LOG_DIS("lapcq %x, $r%u\n",
2703 dc->pc + dc->op1*2, dc->op2);
2704 cris_cc_mask(dc, 0);
2705 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
2706 return 2;
8170028d
TS		 2707}
2708
cf7e0c80 2709static int dec_lapc_im(CPUCRISState *env, DisasContext *dc)
8170028d 2710{
7b5eff4d
EV		 2711 unsigned int rd;
2712 int32_t imm;
2713 int32_t pc;
8170028d 2714
7b5eff4d 2715 rd = dc->op2;
8170028d 2716
7b5eff4d
EV		 2717 cris_cc_mask(dc, 0);
2718 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2719 LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2);
b41f7df0 2720
7b5eff4d
EV		 2721 pc = dc->pc;
2722 pc += imm;
2723 tcg_gen_movi_tl(cpu_R[rd], pc);
2724 return 6;
8170028d
TS		 2725}
2726
2727/* Jump to special reg. */
cf7e0c80 2728static int dec_jump_p(CPUCRISState *env, DisasContext *dc)
8170028d 2729{
7b5eff4d 2730 LOG_DIS("jump $p%u\n", dc->op2);
b41f7df0 2731
7b5eff4d
EV		 2732 if (dc->op2 == PR_CCS) {
2733 cris_evaluate_flags(dc);
2734 }
2735 t_gen_mov_TN_preg(env_btarget, dc->op2);
2736 /* rete will often have low bit set to indicate delayslot. */
2737 tcg_gen_andi_tl(env_btarget, env_btarget, ~1);
2738 cris_cc_mask(dc, 0);
2739 cris_prepare_jmp(dc, JMP_INDIRECT);
2740 return 2;
8170028d
TS		 2741}
2742
2743/* Jump and save. */
cf7e0c80 2744static int dec_jas_r(CPUCRISState *env, DisasContext *dc)
8170028d 2745{
7b5eff4d
EV		 2746 LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2);
2747 cris_cc_mask(dc, 0);
2748 /* Store the return address in Pd. */
2749 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2750 if (dc->op2 > 15) {
2751 abort();
2752 }
2753 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4));
b41f7df0 2754
7b5eff4d
EV		 2755 cris_prepare_jmp(dc, JMP_INDIRECT);
2756 return 2;
8170028d
TS		 2757}
2758
cf7e0c80 2759static int dec_jas_im(CPUCRISState *env, DisasContext *dc)
8170028d 2760{
7b5eff4d 2761 uint32_t imm;
8170028d 2762
7b5eff4d 2763 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
8170028d 2764
7b5eff4d
EV		 2765 LOG_DIS("jas 0x%x\n", imm);
2766 cris_cc_mask(dc, 0);
2767 /* Store the return address in Pd. */
2768 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2a44f7f1 2769
7b5eff4d
EV		 2770 dc->jmp_pc = imm;
2771 cris_prepare_jmp(dc, JMP_DIRECT);
2772 return 6;
8170028d
TS		 2773}
2774
cf7e0c80 2775static int dec_jasc_im(CPUCRISState *env, DisasContext *dc)
8170028d 2776{
7b5eff4d 2777 uint32_t imm;
8170028d 2778
7b5eff4d 2779 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
8170028d 2780
7b5eff4d
EV		 2781 LOG_DIS("jasc 0x%x\n", imm);
2782 cris_cc_mask(dc, 0);
2783 /* Store the return address in Pd. */
2784 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
2a44f7f1 2785
7b5eff4d
EV		 2786 dc->jmp_pc = imm;
2787 cris_prepare_jmp(dc, JMP_DIRECT);
2788 return 6;
8170028d
TS		 2789}
2790
cf7e0c80 2791static int dec_jasc_r(CPUCRISState *env, DisasContext *dc)
8170028d 2792{
7b5eff4d
EV		 2793 LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2);
2794 cris_cc_mask(dc, 0);
2795 /* Store the return address in Pd. */
2796 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2797 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4));
2798 cris_prepare_jmp(dc, JMP_INDIRECT);
2799 return 2;
8170028d
TS		 2800}
2801
cf7e0c80 2802static int dec_bcc_im(CPUCRISState *env, DisasContext *dc)
8170028d 2803{
7b5eff4d
EV		 2804 int32_t offset;
2805 uint32_t cond = dc->op2;
8170028d 2806
7b5eff4d 2807 offset = cris_fetch(env, dc, dc->pc + 2, 2, 1);
8170028d 2808
7b5eff4d
EV		 2809 LOG_DIS("b%s %d pc=%x dst=%x\n",
2810 cc_name(cond), offset,
2811 dc->pc, dc->pc + offset);
8170028d 2812
7b5eff4d
EV		 2813 cris_cc_mask(dc, 0);
2814 /* op2 holds the condition-code. */
2815 cris_prepare_cc_branch(dc, offset, cond);
2816 return 4;
8170028d
TS		 2817}
2818
cf7e0c80 2819static int dec_bas_im(CPUCRISState *env, DisasContext *dc)
8170028d 2820{
7b5eff4d 2821 int32_t simm;
8170028d 2822
7b5eff4d 2823 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
8170028d 2824
7b5eff4d
EV		 2825 LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2826 cris_cc_mask(dc, 0);
2827 /* Store the return address in Pd. */
2828 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
8170028d 2829
7b5eff4d
EV		 2830 dc->jmp_pc = dc->pc + simm;
2831 cris_prepare_jmp(dc, JMP_DIRECT);
2832 return 6;
8170028d
TS		 2833}
2834
cf7e0c80 2835static int dec_basc_im(CPUCRISState *env, DisasContext *dc)
8170028d 2836{
7b5eff4d
EV		 2837 int32_t simm;
2838 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
8170028d 2839
7b5eff4d
EV		 2840 LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2841 cris_cc_mask(dc, 0);
2842 /* Store the return address in Pd. */
2843 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
2a44f7f1 2844
7b5eff4d
EV		 2845 dc->jmp_pc = dc->pc + simm;
2846 cris_prepare_jmp(dc, JMP_DIRECT);
2847 return 6;
8170028d
TS		 2848}
2849
cf7e0c80 2850static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc)
8170028d 2851{
7b5eff4d
EV		 2852 cris_cc_mask(dc, 0);
2853
2854 if (dc->op2 == 15) {
259186a7
AF		 2855 tcg_gen_st_i32(tcg_const_i32(1), cpu_env,
2856 -offsetof(CRISCPU, env) + offsetof(CPUState, halted));
7b5eff4d
EV		 2857 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2858 t_gen_raise_exception(EXCP_HLT);
2859 return 2;
2860 }
2861
2862 switch (dc->op2 & 7) {
2863 case 2:
2864 /* rfe. */
2865 LOG_DIS("rfe\n");
2866 cris_evaluate_flags(dc);
2867 gen_helper_rfe(cpu_env);
2868 dc->is_jmp = DISAS_UPDATE;
2869 break;
2870 case 5:
2871 /* rfn. */
2872 LOG_DIS("rfn\n");
2873 cris_evaluate_flags(dc);
2874 gen_helper_rfn(cpu_env);
2875 dc->is_jmp = DISAS_UPDATE;
2876 break;
2877 case 6:
2878 LOG_DIS("break %d\n", dc->op1);
2879 cris_evaluate_flags(dc);
2880 /* break. */
2881 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2882
2883 /* Breaks start at 16 in the exception vector. */
2884 t_gen_mov_env_TN(trap_vector,
2885 tcg_const_tl(dc->op1 + 16));
2886 t_gen_raise_exception(EXCP_BREAK);
2887 dc->is_jmp = DISAS_UPDATE;
2888 break;
2889 default:
2890 printf("op2=%x\n", dc->op2);
2891 BUG();
2892 break;
2893
2894 }
2895 return 2;
8170028d
TS		 2896}
2897
cf7e0c80 2898static int dec_ftag_fidx_d_m(CPUCRISState *env, DisasContext *dc)
5d4a534d 2899{
7b5eff4d 2900 return 2;
5d4a534d
EI		 2901}
2902
cf7e0c80 2903static int dec_ftag_fidx_i_m(CPUCRISState *env, DisasContext *dc)
5d4a534d 2904{
7b5eff4d 2905 return 2;
5d4a534d
EI		 2906}
2907
cf7e0c80 2908static int dec_null(CPUCRISState *env, DisasContext *dc)
8170028d 2909{
7b5eff4d
EV		 2910 printf("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2911 dc->pc, dc->opcode, dc->op1, dc->op2);
2912 fflush(NULL);
2913 BUG();
2914 return 2;
8170028d
TS		 2915}
2916
9b32fbf8 2917static struct decoder_info {
7b5eff4d
EV		 2918 struct {
2919 uint32_t bits;
2920 uint32_t mask;
2921 };
2922 int (*dec)(CPUCRISState *env, DisasContext *dc);
8170028d 2923} decinfo[] = {
7b5eff4d
EV		 2924 /* Order matters here. */
2925 {DEC_MOVEQ, dec_moveq},
2926 {DEC_BTSTQ, dec_btstq},
2927 {DEC_CMPQ, dec_cmpq},
2928 {DEC_ADDOQ, dec_addoq},
2929 {DEC_ADDQ, dec_addq},
2930 {DEC_SUBQ, dec_subq},
2931 {DEC_ANDQ, dec_andq},
2932 {DEC_ORQ, dec_orq},
2933 {DEC_ASRQ, dec_asrq},
2934 {DEC_LSLQ, dec_lslq},
2935 {DEC_LSRQ, dec_lsrq},
2936 {DEC_BCCQ, dec_bccq},
2937
2938 {DEC_BCC_IM, dec_bcc_im},
2939 {DEC_JAS_IM, dec_jas_im},
2940 {DEC_JAS_R, dec_jas_r},
2941 {DEC_JASC_IM, dec_jasc_im},
2942 {DEC_JASC_R, dec_jasc_r},
2943 {DEC_BAS_IM, dec_bas_im},
2944 {DEC_BASC_IM, dec_basc_im},
2945 {DEC_JUMP_P, dec_jump_p},
2946 {DEC_LAPC_IM, dec_lapc_im},
2947 {DEC_LAPCQ, dec_lapcq},
2948
2949 {DEC_RFE_ETC, dec_rfe_etc},
2950 {DEC_ADDC_MR, dec_addc_mr},
2951
2952 {DEC_MOVE_MP, dec_move_mp},
2953 {DEC_MOVE_PM, dec_move_pm},
2954 {DEC_MOVEM_MR, dec_movem_mr},
2955 {DEC_MOVEM_RM, dec_movem_rm},
2956 {DEC_MOVE_PR, dec_move_pr},
2957 {DEC_SCC_R, dec_scc_r},
2958 {DEC_SETF, dec_setclrf},
2959 {DEC_CLEARF, dec_setclrf},
2960
2961 {DEC_MOVE_SR, dec_move_sr},
2962 {DEC_MOVE_RP, dec_move_rp},
2963 {DEC_SWAP_R, dec_swap_r},
2964 {DEC_ABS_R, dec_abs_r},
2965 {DEC_LZ_R, dec_lz_r},
2966 {DEC_MOVE_RS, dec_move_rs},
2967 {DEC_BTST_R, dec_btst_r},
2968 {DEC_ADDC_R, dec_addc_r},
2969
2970 {DEC_DSTEP_R, dec_dstep_r},
2971 {DEC_XOR_R, dec_xor_r},
2972 {DEC_MCP_R, dec_mcp_r},
2973 {DEC_CMP_R, dec_cmp_r},
2974
2975 {DEC_ADDI_R, dec_addi_r},
2976 {DEC_ADDI_ACR, dec_addi_acr},
2977
2978 {DEC_ADD_R, dec_add_r},
2979 {DEC_SUB_R, dec_sub_r},
2980
2981 {DEC_ADDU_R, dec_addu_r},
2982 {DEC_ADDS_R, dec_adds_r},
2983 {DEC_SUBU_R, dec_subu_r},
2984 {DEC_SUBS_R, dec_subs_r},
2985 {DEC_LSL_R, dec_lsl_r},
2986
2987 {DEC_AND_R, dec_and_r},
2988 {DEC_OR_R, dec_or_r},
2989 {DEC_BOUND_R, dec_bound_r},
2990 {DEC_ASR_R, dec_asr_r},
2991 {DEC_LSR_R, dec_lsr_r},
2992
2993 {DEC_MOVU_R, dec_movu_r},
2994 {DEC_MOVS_R, dec_movs_r},
2995 {DEC_NEG_R, dec_neg_r},
2996 {DEC_MOVE_R, dec_move_r},
2997
2998 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
2999 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
3000
3001 {DEC_MULS_R, dec_muls_r},
3002 {DEC_MULU_R, dec_mulu_r},
3003
3004 {DEC_ADDU_M, dec_addu_m},
3005 {DEC_ADDS_M, dec_adds_m},
3006 {DEC_SUBU_M, dec_subu_m},
3007 {DEC_SUBS_M, dec_subs_m},
3008
3009 {DEC_CMPU_M, dec_cmpu_m},
3010 {DEC_CMPS_M, dec_cmps_m},
3011 {DEC_MOVU_M, dec_movu_m},
3012 {DEC_MOVS_M, dec_movs_m},
3013
3014 {DEC_CMP_M, dec_cmp_m},
3015 {DEC_ADDO_M, dec_addo_m},
3016 {DEC_BOUND_M, dec_bound_m},
3017 {DEC_ADD_M, dec_add_m},
3018 {DEC_SUB_M, dec_sub_m},
3019 {DEC_AND_M, dec_and_m},
3020 {DEC_OR_M, dec_or_m},
3021 {DEC_MOVE_RM, dec_move_rm},
3022 {DEC_TEST_M, dec_test_m},
3023 {DEC_MOVE_MR, dec_move_mr},
3024
3025 {{0, 0}, dec_null}
8170028d
TS		 3026};
3027
cf7e0c80 3028static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
8170028d 3029{
7b5eff4d
EV		 3030 int insn_len = 2;
3031 int i;
8170028d 3032
7b5eff4d
EV		 3033 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
3034 tcg_gen_debug_insn_start(dc->pc);
fdefe51c 3035 }
28de16da 3036
7b5eff4d 3037 /* Load a halfword onto the instruction register. */
cf7e0c80 3038 dc->ir = cris_fetch(env, dc, dc->pc, 2, 0);
8170028d 3039
7b5eff4d
EV		 3040 /* Now decode it. */
3041 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
3042 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
3043 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
3044 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
3045 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
3046 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
3047
3048 /* Large switch for all insns. */
3049 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
3050 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
3051 insn_len = decinfo[i].dec(env, dc);
3052 break;
3053 }
3054 }
8170028d 3055
dd20fcd0 3056#if !defined(CONFIG_USER_ONLY)
7b5eff4d
EV		 3057 /* Single-stepping ? */
3058 if (dc->tb_flags & S_FLAG) {
3059 int l1;
3060
3061 l1 = gen_new_label();
3062 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1);
3063 /* We treat SPC as a break with an odd trap vector. */
3064 cris_evaluate_flags(dc);
3065 t_gen_mov_env_TN(trap_vector, tcg_const_tl(3));
3066 tcg_gen_movi_tl(env_pc, dc->pc + insn_len);
3067 tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len);
3068 t_gen_raise_exception(EXCP_BREAK);
3069 gen_set_label(l1);
3070 }
a1aebcb8 3071#endif
7b5eff4d 3072 return insn_len;
8170028d
TS		 3073}
3074
a1170bfd 3075static void check_breakpoint(CPUCRISState *env, DisasContext *dc)
8170028d 3076{
f0c3c505 3077 CPUState *cs = CPU(cris_env_get_cpu(env));
7b5eff4d 3078 CPUBreakpoint *bp;
a1d1bb31 3079
f0c3c505
AF		 3080 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
3081 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
7b5eff4d
EV		 3082 if (bp->pc == dc->pc) {
3083 cris_evaluate_flags(dc);
3084 tcg_gen_movi_tl(env_pc, dc->pc);
3085 t_gen_raise_exception(EXCP_DEBUG);
3086 dc->is_jmp = DISAS_UPDATE;
3087 }
3088 }
3089 }
8170028d
TS		 3090}
3091
40e9eddd 3092#include "translate_v10.c"
cf1d97f0
EI		 3093
3094/*
3095 * Delay slots on QEMU/CRIS.
3096 *
3097 * If an exception hits on a delayslot, the core will let ERP (the Exception
3098 * Return Pointer) point to the branch (the previous) insn and set the lsb to
3099 * to give SW a hint that the exception actually hit on the dslot.
3100 *
3101 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
3102 * the core and any jmp to an odd addresses will mask off that lsb. It is
3103 * simply there to let sw know there was an exception on a dslot.
3104 *
3105 * When the software returns from an exception, the branch will re-execute.
3106 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3107 * and the branch and delayslot dont share pages.
3108 *
3109 * The TB contaning the branch insn will set up env->btarget and evaluate
3110 * env->btaken. When the translation loop exits we will note that the branch
3111 * sequence is broken and let env->dslot be the size of the branch insn (those
3112 * vary in length).
3113 *
3114 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3115 * set). It will also expect to have env->dslot setup with the size of the
3116 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3117 * will execute the dslot and take the branch, either to btarget or just one
3118 * insn ahead.
3119 *
3120 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3121 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3122 * branch and set lsb). Then env->dslot gets cleared so that the exception
3123 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3124 * masked off and we will reexecute the branch insn.
3125 *
3126 */
3127
8170028d 3128/* generate intermediate code for basic block 'tb'. */
6f47ec50 3129static inline void
7fd2592d
AF		 3130gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,
3131 bool search_pc)
8170028d 3132{
ed2803da 3133 CPUState *cs = CPU(cpu);
7fd2592d 3134 CPUCRISState *env = &cpu->env;
7b5eff4d
EV		 3135 uint16_t *gen_opc_end;
3136 uint32_t pc_start;
3137 unsigned int insn_len;
3138 int j, lj;
3139 struct DisasContext ctx;
3140 struct DisasContext *dc = &ctx;
3141 uint32_t next_page_start;
3142 target_ulong npc;
3143 int num_insns;
3144 int max_insns;
3145
7b5eff4d
EV		 3146 if (env->pregs[PR_VR] == 32) {
3147 dc->decoder = crisv32_decoder;
3148 dc->clear_locked_irq = 0;
3149 } else {
3150 dc->decoder = crisv10_decoder;
3151 dc->clear_locked_irq = 1;
3152 }
3153
3154 /* Odd PC indicates that branch is rexecuting due to exception in the
3155 * delayslot, like in real hw.
3156 */
3157 pc_start = tb->pc & ~1;
0dd106c5 3158 dc->cpu = cpu;
7b5eff4d
EV		 3159 dc->tb = tb;
3160
92414b31 3161 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
7b5eff4d
EV		 3162
3163 dc->is_jmp = DISAS_NEXT;
3164 dc->ppc = pc_start;
3165 dc->pc = pc_start;
ed2803da 3166 dc->singlestep_enabled = cs->singlestep_enabled;
7b5eff4d
EV		 3167 dc->flags_uptodate = 1;
3168 dc->flagx_known = 1;
3169 dc->flags_x = tb->flags & X_FLAG;
3170 dc->cc_x_uptodate = 0;
3171 dc->cc_mask = 0;
3172 dc->update_cc = 0;
3173 dc->clear_prefix = 0;
3174
3175 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
3176 dc->cc_size_uptodate = -1;
3177
3178 /* Decode TB flags. */
3179 dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG \
3180 | X_FLAG | PFIX_FLAG);
3181 dc->delayed_branch = !!(tb->flags & 7);
3182 if (dc->delayed_branch) {
3183 dc->jmp = JMP_INDIRECT;
3184 } else {
3185 dc->jmp = JMP_NOJMP;
3186 }
3187
3188 dc->cpustate_changed = 0;
3189
3190 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3191 qemu_log(
3192 "srch=%d pc=%x %x flg=%" PRIx64 " bt=%x ds=%u ccs=%x\n"
3193 "pid=%x usp=%x\n"
3194 "%x.%x.%x.%x\n"
3195 "%x.%x.%x.%x\n"
3196 "%x.%x.%x.%x\n"
3197 "%x.%x.%x.%x\n",
3198 search_pc, dc->pc, dc->ppc,
3199 (uint64_t)tb->flags,
3200 env->btarget, (unsigned)tb->flags & 7,
3201 env->pregs[PR_CCS],
3202 env->pregs[PR_PID], env->pregs[PR_USP],
3203 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
3204 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
3205 env->regs[8], env->regs[9],
3206 env->regs[10], env->regs[11],
3207 env->regs[12], env->regs[13],
3208 env->regs[14], env->regs[15]);
3209 qemu_log("--------------\n");
3210 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3211 }
3212
3213 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3214 lj = -1;
3215 num_insns = 0;
3216 max_insns = tb->cflags & CF_COUNT_MASK;
3217 if (max_insns == 0) {
3218 max_insns = CF_COUNT_MASK;
3219 }
3220
806f352d 3221 gen_tb_start();
7b5eff4d
EV		 3222 do {
3223 check_breakpoint(env, dc);
3224
3225 if (search_pc) {
92414b31 3226 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
7b5eff4d
EV		 3227 if (lj < j) {
3228 lj++;
3229 while (lj < j) {
ab1103de 3230 tcg_ctx.gen_opc_instr_start[lj++] = 0;
7b5eff4d
EV		 3231 }
3232 }
3233 if (dc->delayed_branch == 1) {
25983cad 3234 tcg_ctx.gen_opc_pc[lj] = dc->ppc | 1;
7b5eff4d 3235 } else {
25983cad 3236 tcg_ctx.gen_opc_pc[lj] = dc->pc;
7b5eff4d 3237 }
ab1103de 3238 tcg_ctx.gen_opc_instr_start[lj] = 1;
c9c99c22 3239 tcg_ctx.gen_opc_icount[lj] = num_insns;
7b5eff4d
EV		 3240 }
3241
3242 /* Pretty disas. */
3243 LOG_DIS("%8.8x:\t", dc->pc);
3244
3245 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
3246 gen_io_start();
3247 }
3248 dc->clear_x = 1;
3249
3250 insn_len = dc->decoder(env, dc);
3251 dc->ppc = dc->pc;
3252 dc->pc += insn_len;
3253 if (dc->clear_x) {
3254 cris_clear_x_flag(dc);
3255 }
3256
3257 num_insns++;
3258 /* Check for delayed branches here. If we do it before
3259 actually generating any host code, the simulator will just
3260 loop doing nothing for on this program location. */
3261 if (dc->delayed_branch) {
3262 dc->delayed_branch--;
3263 if (dc->delayed_branch == 0) {
3264 if (tb->flags & 7) {
3265 t_gen_mov_env_TN(dslot, tcg_const_tl(0));
3266 }
3267 if (dc->cpustate_changed || !dc->flagx_known
3268 || (dc->flags_x != (tb->flags & X_FLAG))) {
3269 cris_store_direct_jmp(dc);
3270 }
3271
3272 if (dc->clear_locked_irq) {
3273 dc->clear_locked_irq = 0;
3274 t_gen_mov_env_TN(locked_irq, tcg_const_tl(0));
3275 }
3276
3277 if (dc->jmp == JMP_DIRECT_CC) {
3278 int l1;
3279
3280 l1 = gen_new_label();
3281 cris_evaluate_flags(dc);
3282
3283 /* Conditional jmp. */
3284 tcg_gen_brcondi_tl(TCG_COND_EQ,
3285 env_btaken, 0, l1);
3286 gen_goto_tb(dc, 1, dc->jmp_pc);
3287 gen_set_label(l1);
3288 gen_goto_tb(dc, 0, dc->pc);
3289 dc->is_jmp = DISAS_TB_JUMP;
3290 dc->jmp = JMP_NOJMP;
3291 } else if (dc->jmp == JMP_DIRECT) {
3292 cris_evaluate_flags(dc);
3293 gen_goto_tb(dc, 0, dc->jmp_pc);
3294 dc->is_jmp = DISAS_TB_JUMP;
3295 dc->jmp = JMP_NOJMP;
3296 } else {
3297 t_gen_cc_jmp(env_btarget, tcg_const_tl(dc->pc));
3298 dc->is_jmp = DISAS_JUMP;
3299 }
3300 break;
3301 }
3302 }
3303
3304 /* If we are rexecuting a branch due to exceptions on
3305 delay slots dont break. */
ed2803da 3306 if (!(tb->pc & 1) && cs->singlestep_enabled) {
7b5eff4d
EV		 3307 break;
3308 }
3309 } while (!dc->is_jmp && !dc->cpustate_changed
efd7f486 3310 && tcg_ctx.gen_opc_ptr < gen_opc_end
7b5eff4d
EV		 3311 && !singlestep
3312 && (dc->pc < next_page_start)
3313 && num_insns < max_insns);
3314
3315 if (dc->clear_locked_irq) {
3316 t_gen_mov_env_TN(locked_irq, tcg_const_tl(0));
3317 }
3318
3319 npc = dc->pc;
2a44f7f1 3320
2e70f6ef
PB		 3321 if (tb->cflags & CF_LAST_IO)
3322 gen_io_end();
7b5eff4d
EV		 3323 /* Force an update if the per-tb cpu state has changed. */
3324 if (dc->is_jmp == DISAS_NEXT
3325 && (dc->cpustate_changed || !dc->flagx_known
3326 || (dc->flags_x != (tb->flags & X_FLAG)))) {
3327 dc->is_jmp = DISAS_UPDATE;
3328 tcg_gen_movi_tl(env_pc, npc);
3329 }
3330 /* Broken branch+delayslot sequence. */
3331 if (dc->delayed_branch == 1) {
3332 /* Set env->dslot to the size of the branch insn. */
3333 t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
3334 cris_store_direct_jmp(dc);
3335 }
3336
3337 cris_evaluate_flags(dc);
3338
ed2803da 3339 if (unlikely(cs->singlestep_enabled)) {
7b5eff4d
EV		 3340 if (dc->is_jmp == DISAS_NEXT) {
3341 tcg_gen_movi_tl(env_pc, npc);
3342 }
3343 t_gen_raise_exception(EXCP_DEBUG);
3344 } else {
3345 switch (dc->is_jmp) {
3346 case DISAS_NEXT:
3347 gen_goto_tb(dc, 1, npc);
3348 break;
3349 default:
3350 case DISAS_JUMP:
3351 case DISAS_UPDATE:
3352 /* indicate that the hash table must be used
3353 to find the next TB */
3354 tcg_gen_exit_tb(0);
3355 break;
3356 case DISAS_SWI:
3357 case DISAS_TB_JUMP:
3358 /* nothing more to generate */
3359 break;
3360 }
3361 }
806f352d 3362 gen_tb_end(tb, num_insns);
efd7f486 3363 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
7b5eff4d 3364 if (search_pc) {
92414b31 3365 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
7b5eff4d
EV		 3366 lj++;
3367 while (lj <= j) {
ab1103de 3368 tcg_ctx.gen_opc_instr_start[lj++] = 0;
7b5eff4d
EV		 3369 }
3370 } else {
3371 tb->size = dc->pc - pc_start;
3372 tb->icount = num_insns;
3373 }
8170028d
TS		 3374
3375#ifdef DEBUG_DISAS
a1aebcb8 3376#if !DISAS_CRIS
7b5eff4d
EV		 3377 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3378 log_target_disas(env, pc_start, dc->pc - pc_start,
0dd106c5 3379 env->pregs[PR_VR]);
7b5eff4d 3380 qemu_log("\nisize=%d osize=%td\n",
92414b31 3381 dc->pc - pc_start, tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf);
7b5eff4d 3382 }
8170028d 3383#endif
a1aebcb8 3384#endif
8170028d
TS		 3385}
3386
a1170bfd 3387void gen_intermediate_code (CPUCRISState *env, struct TranslationBlock *tb)
8170028d 3388{
7fd2592d 3389 gen_intermediate_code_internal(cris_env_get_cpu(env), tb, false);
8170028d
TS		 3390}
3391
a1170bfd 3392void gen_intermediate_code_pc (CPUCRISState *env, struct TranslationBlock *tb)
8170028d 3393{
7fd2592d 3394 gen_intermediate_code_internal(cris_env_get_cpu(env), tb, true);
8170028d
TS		 3395}
3396
878096ee
AF		 3397void cris_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
3398 int flags)
8170028d 3399{
878096ee
AF		 3400 CRISCPU *cpu = CRIS_CPU(cs);
3401 CPUCRISState *env = &cpu->env;
7b5eff4d
EV		 3402 int i;
3403 uint32_t srs;
3404
3405 if (!env || !f) {
3406 return;
3407 }
3408
3409 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3410 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3411 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
3412 env->cc_op,
3413 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
3414
3415
3416 for (i = 0; i < 16; i++) {
3417 cpu_fprintf(f, "%s=%8.8x ", regnames[i], env->regs[i]);
3418 if ((i + 1) % 4 == 0) {
3419 cpu_fprintf(f, "\n");
3420 }
3421 }
3422 cpu_fprintf(f, "\nspecial regs:\n");
3423 for (i = 0; i < 16; i++) {
3424 cpu_fprintf(f, "%s=%8.8x ", pregnames[i], env->pregs[i]);
3425 if ((i + 1) % 4 == 0) {
3426 cpu_fprintf(f, "\n");
3427 }
3428 }
3429 srs = env->pregs[PR_SRS];
3430 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
3431 if (srs < ARRAY_SIZE(env->sregs)) {
3432 for (i = 0; i < 16; i++) {
3433 cpu_fprintf(f, "s%2.2d=%8.8x ",
3434 i, env->sregs[srs][i]);
3435 if ((i + 1) % 4 == 0) {
3436 cpu_fprintf(f, "\n");
3437 }
3438 }
3439 }
3440 cpu_fprintf(f, "\n\n");
8170028d
TS		 3441
3442}
3443
d1a94fec
AF		 3444void cris_initialize_tcg(void)
3445{
3446 int i;
05ba7d5f 3447
dd10ce6d
AF		 3448 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
3449 cc_x = tcg_global_mem_new(TCG_AREG0,
3450 offsetof(CPUCRISState, cc_x), "cc_x");
3451 cc_src = tcg_global_mem_new(TCG_AREG0,
3452 offsetof(CPUCRISState, cc_src), "cc_src");
3453 cc_dest = tcg_global_mem_new(TCG_AREG0,
3454 offsetof(CPUCRISState, cc_dest),
3455 "cc_dest");
3456 cc_result = tcg_global_mem_new(TCG_AREG0,
3457 offsetof(CPUCRISState, cc_result),
3458 "cc_result");
3459 cc_op = tcg_global_mem_new(TCG_AREG0,
3460 offsetof(CPUCRISState, cc_op), "cc_op");
3461 cc_size = tcg_global_mem_new(TCG_AREG0,
3462 offsetof(CPUCRISState, cc_size),
3463 "cc_size");
3464 cc_mask = tcg_global_mem_new(TCG_AREG0,
3465 offsetof(CPUCRISState, cc_mask),
3466 "cc_mask");
3467
3468 env_pc = tcg_global_mem_new(TCG_AREG0,
3469 offsetof(CPUCRISState, pc),
3470 "pc");
3471 env_btarget = tcg_global_mem_new(TCG_AREG0,
3472 offsetof(CPUCRISState, btarget),
3473 "btarget");
3474 env_btaken = tcg_global_mem_new(TCG_AREG0,
3475 offsetof(CPUCRISState, btaken),
3476 "btaken");
3477 for (i = 0; i < 16; i++) {
3478 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
3479 offsetof(CPUCRISState, regs[i]),
3480 regnames[i]);
3481 }
3482 for (i = 0; i < 16; i++) {
3483 cpu_PR[i] = tcg_global_mem_new(TCG_AREG0,
3484 offsetof(CPUCRISState, pregs[i]),
3485 pregnames[i]);
3486 }
8170028d
TS		 3487}
3488
a1170bfd 3489void restore_state_to_opc(CPUCRISState *env, TranslationBlock *tb, int pc_pos)
d2856f1a 3490{
25983cad 3491 env->pc = tcg_ctx.gen_opc_pc[pc_pos];
d2856f1a 3492}
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