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ab93bbe2 FB |
1 | /* |
2 | * common defines for all CPUs | |
5fafdf24 | 3 | * |
ab93bbe2 FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | #ifndef CPU_DEFS_H | |
21 | #define CPU_DEFS_H | |
22 | ||
87ecb68b PB |
23 | #ifndef NEED_CPU_H |
24 | #error cpu.h included from common code | |
25 | #endif | |
26 | ||
ab93bbe2 FB |
27 | #include "config.h" |
28 | #include <setjmp.h> | |
ed1c0bcb FB |
29 | #include <inttypes.h> |
30 | #include "osdep.h" | |
ab93bbe2 | 31 | |
35b66fc4 FB |
32 | #ifndef TARGET_LONG_BITS |
33 | #error TARGET_LONG_BITS must be defined before including this header | |
34 | #endif | |
35 | ||
5fafdf24 | 36 | #ifndef TARGET_PHYS_ADDR_BITS |
4f2ac237 | 37 | #if TARGET_LONG_BITS >= HOST_LONG_BITS |
ab6d960f | 38 | #define TARGET_PHYS_ADDR_BITS TARGET_LONG_BITS |
4f2ac237 FB |
39 | #else |
40 | #define TARGET_PHYS_ADDR_BITS HOST_LONG_BITS | |
41 | #endif | |
ab6d960f FB |
42 | #endif |
43 | ||
35b66fc4 FB |
44 | #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) |
45 | ||
ab6d960f | 46 | /* target_ulong is the type of a virtual address */ |
35b66fc4 FB |
47 | #if TARGET_LONG_SIZE == 4 |
48 | typedef int32_t target_long; | |
49 | typedef uint32_t target_ulong; | |
c27004ec | 50 | #define TARGET_FMT_lx "%08x" |
b62b461b | 51 | #define TARGET_FMT_ld "%d" |
71c8b8fd | 52 | #define TARGET_FMT_lu "%u" |
35b66fc4 FB |
53 | #elif TARGET_LONG_SIZE == 8 |
54 | typedef int64_t target_long; | |
55 | typedef uint64_t target_ulong; | |
26a76461 | 56 | #define TARGET_FMT_lx "%016" PRIx64 |
b62b461b | 57 | #define TARGET_FMT_ld "%" PRId64 |
71c8b8fd | 58 | #define TARGET_FMT_lu "%" PRIu64 |
35b66fc4 FB |
59 | #else |
60 | #error TARGET_LONG_SIZE undefined | |
61 | #endif | |
62 | ||
ab6d960f | 63 | /* target_phys_addr_t is the type of a physical address (its size can |
4f2ac237 FB |
64 | be different from 'target_ulong'). We have sizeof(target_phys_addr) |
65 | = max(sizeof(unsigned long), | |
66 | sizeof(size_of_target_physical_address)) because we must pass a | |
67 | host pointer to memory operations in some cases */ | |
68 | ||
ab6d960f FB |
69 | #if TARGET_PHYS_ADDR_BITS == 32 |
70 | typedef uint32_t target_phys_addr_t; | |
ba13c432 | 71 | #define TARGET_FMT_plx "%08x" |
ab6d960f FB |
72 | #elif TARGET_PHYS_ADDR_BITS == 64 |
73 | typedef uint64_t target_phys_addr_t; | |
ba13c432 | 74 | #define TARGET_FMT_plx "%016" PRIx64 |
ab6d960f FB |
75 | #else |
76 | #error TARGET_PHYS_ADDR_BITS undefined | |
77 | #endif | |
78 | ||
ff7b8f5b FB |
79 | /* address in the RAM (different from a physical address) */ |
80 | typedef unsigned long ram_addr_t; | |
81 | ||
f193c797 FB |
82 | #define HOST_LONG_SIZE (HOST_LONG_BITS / 8) |
83 | ||
2be0071f FB |
84 | #define EXCP_INTERRUPT 0x10000 /* async interruption */ |
85 | #define EXCP_HLT 0x10001 /* hlt instruction reached */ | |
86 | #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ | |
5a1e3cfc | 87 | #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ |
ab93bbe2 | 88 | #define MAX_BREAKPOINTS 32 |
6658ffb8 | 89 | #define MAX_WATCHPOINTS 32 |
ab93bbe2 | 90 | |
a316d335 FB |
91 | #define TB_JMP_CACHE_BITS 12 |
92 | #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) | |
93 | ||
b362e5e0 PB |
94 | /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for |
95 | addresses on the same page. The top bits are the same. This allows | |
96 | TLB invalidation to quickly clear a subset of the hash table. */ | |
97 | #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2) | |
98 | #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS) | |
99 | #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1) | |
100 | #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE) | |
101 | ||
84b7b8e7 FB |
102 | #define CPU_TLB_BITS 8 |
103 | #define CPU_TLB_SIZE (1 << CPU_TLB_BITS) | |
ab93bbe2 FB |
104 | |
105 | typedef struct CPUTLBEntry { | |
5fafdf24 | 106 | /* bit 31 to TARGET_PAGE_BITS : virtual address |
db8d7466 FB |
107 | bit TARGET_PAGE_BITS-1..IO_MEM_SHIFT : if non zero, memory io |
108 | zone number | |
109 | bit 3 : indicates that the entry is invalid | |
110 | bit 2..0 : zero | |
111 | */ | |
5fafdf24 TS |
112 | target_ulong addr_read; |
113 | target_ulong addr_write; | |
114 | target_ulong addr_code; | |
db8d7466 | 115 | /* addend to virtual address to get physical address */ |
5fafdf24 | 116 | target_phys_addr_t addend; |
ab93bbe2 FB |
117 | } CPUTLBEntry; |
118 | ||
a316d335 FB |
119 | #define CPU_COMMON \ |
120 | struct TranslationBlock *current_tb; /* currently executing TB */ \ | |
121 | /* soft mmu support */ \ | |
122 | /* in order to avoid passing too many arguments to the memory \ | |
123 | write helpers, we store some rarely used information in the CPU \ | |
124 | context) */ \ | |
125 | unsigned long mem_write_pc; /* host pc at which the memory was \ | |
126 | written */ \ | |
127 | target_ulong mem_write_vaddr; /* target virtual addr at which the \ | |
128 | memory was written */ \ | |
623a930e | 129 | /* The meaning of the MMU modes is defined in the target code. */ \ |
6fa4cea9 | 130 | CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ |
a316d335 FB |
131 | struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ |
132 | \ | |
133 | /* from this point: preserved by CPU reset */ \ | |
134 | /* ice debug support */ \ | |
135 | target_ulong breakpoints[MAX_BREAKPOINTS]; \ | |
136 | int nb_breakpoints; \ | |
137 | int singlestep_enabled; \ | |
138 | \ | |
6658ffb8 PB |
139 | struct { \ |
140 | target_ulong vaddr; \ | |
d79acba4 | 141 | target_phys_addr_t addend; \ |
6658ffb8 PB |
142 | } watchpoint[MAX_WATCHPOINTS]; \ |
143 | int nb_watchpoints; \ | |
144 | int watchpoint_hit; \ | |
145 | \ | |
6a00d601 FB |
146 | void *next_cpu; /* next CPU sharing TB cache */ \ |
147 | int cpu_index; /* CPU index (informative) */ \ | |
a316d335 FB |
148 | /* user data */ \ |
149 | void *opaque; | |
150 | ||
ab93bbe2 | 151 | #endif |