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tcg-sparc: fix build
[qemu.git] / cpu-exec.c
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7d13299d 1/*
e965fc38 2 * emulator main execution loop
5fafdf24 3 *
66321a11 4 * Copyright (c) 2003-2005 Fabrice Bellard
7d13299d 5 *
3ef693a0
FB		 6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB		 11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0 16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
7d13299d 18 */
e4533c7a 19#include "config.h"
cea5f9a2 20#include "cpu.h"
76cad711 21#include "disas/disas.h"
7cb69cae 22#include "tcg.h"
1de7afc9 23#include "qemu/atomic.h"
9c17d615 24#include "sysemu/qtest.h"
7d13299d 25
f0667e66 26//#define CONFIG_DEBUG_EXEC
7d13299d 27
3993c6bd 28bool qemu_cpu_has_work(CPUState *cpu)
6a4955a8 29{
3993c6bd 30 return cpu_has_work(cpu);
6a4955a8
AL		 31}
32
9349b4f9 33void cpu_loop_exit(CPUArchState *env)
e4533c7a 34{
d77953b9
AF		 35 CPUState *cpu = ENV_GET_CPU(env);
36
37 cpu->current_tb = NULL;
6ab7e546 38 siglongjmp(env->jmp_env, 1);
e4533c7a 39}
bfed01fc 40
fbf9eeb3
FB		 41/* exit the current TB from a signal handler. The host registers are
42 restored in a state compatible with the CPU emulator
43 */
9eff14f3 44#if defined(CONFIG_SOFTMMU)
9349b4f9 45void cpu_resume_from_signal(CPUArchState *env, void *puc)
9eff14f3 46{
9eff14f3
BS		 47 /* XXX: restore cpu registers saved in host registers */
48
49 env->exception_index = -1;
6ab7e546 50 siglongjmp(env->jmp_env, 1);
9eff14f3 51}
9eff14f3 52#endif
fbf9eeb3 53
2e70f6ef
PB		 54/* Execute the code without caching the generated code. An interpreter
55 could be used if available. */
9349b4f9 56static void cpu_exec_nocache(CPUArchState *env, int max_cycles,
cea5f9a2 57 TranslationBlock *orig_tb)
2e70f6ef 58{
d77953b9 59 CPUState *cpu = ENV_GET_CPU(env);
69784eae 60 tcg_target_ulong next_tb;
2e70f6ef
PB		 61 TranslationBlock *tb;
62
63 /* Should never happen.
64 We only end up here when an existing TB is too long. */
65 if (max_cycles > CF_COUNT_MASK)
66 max_cycles = CF_COUNT_MASK;
67
68 tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
69 max_cycles);
d77953b9 70 cpu->current_tb = tb;
2e70f6ef 71 /* execute the generated code */
cea5f9a2 72 next_tb = tcg_qemu_tb_exec(env, tb->tc_ptr);
d77953b9 73 cpu->current_tb = NULL;
2e70f6ef
PB		 74
75 if ((next_tb & 3) == 2) {
76 /* Restore PC. This may happen if async event occurs before
77 the TB starts executing. */
622ed360 78 cpu_pc_from_tb(env, tb);
2e70f6ef
PB		 79 }
80 tb_phys_invalidate(tb, -1);
81 tb_free(tb);
82}
83
9349b4f9 84static TranslationBlock *tb_find_slow(CPUArchState *env,
cea5f9a2 85 target_ulong pc,
8a40a180 86 target_ulong cs_base,
c068688b 87 uint64_t flags)
8a40a180
FB		 88{
89 TranslationBlock *tb, **ptb1;
8a40a180 90 unsigned int h;
337fc758 91 tb_page_addr_t phys_pc, phys_page1;
41c1b1c9 92 target_ulong virt_page2;
3b46e624 93
5e5f07e0 94 tcg_ctx.tb_ctx.tb_invalidated_flag = 0;
3b46e624 95
8a40a180 96 /* find translated block using physical mappings */
41c1b1c9 97 phys_pc = get_page_addr_code(env, pc);
8a40a180 98 phys_page1 = phys_pc & TARGET_PAGE_MASK;
8a40a180 99 h = tb_phys_hash_func(phys_pc);
5e5f07e0 100 ptb1 = &tcg_ctx.tb_ctx.tb_phys_hash[h];
8a40a180
FB		 101 for(;;) {
102 tb = *ptb1;
103 if (!tb)
104 goto not_found;
5fafdf24 105 if (tb->pc == pc &&
8a40a180 106 tb->page_addr[0] == phys_page1 &&
5fafdf24 107 tb->cs_base == cs_base &&
8a40a180
FB		 108 tb->flags == flags) {
109 /* check next page if needed */
110 if (tb->page_addr[1] != -1) {
337fc758
BS		 111 tb_page_addr_t phys_page2;
112
5fafdf24 113 virt_page2 = (pc & TARGET_PAGE_MASK) +
8a40a180 114 TARGET_PAGE_SIZE;
41c1b1c9 115 phys_page2 = get_page_addr_code(env, virt_page2);
8a40a180
FB		 116 if (tb->page_addr[1] == phys_page2)
117 goto found;
118 } else {
119 goto found;
120 }
121 }
122 ptb1 = &tb->phys_hash_next;
123 }
124 not_found:
2e70f6ef
PB		 125 /* if no translated code available, then translate it now */
126 tb = tb_gen_code(env, pc, cs_base, flags, 0);
3b46e624 127
8a40a180 128 found:
2c90fe2b
KB		 129 /* Move the last found TB to the head of the list */
130 if (likely(*ptb1)) {
131 *ptb1 = tb->phys_hash_next;
5e5f07e0
EV		 132 tb->phys_hash_next = tcg_ctx.tb_ctx.tb_phys_hash[h];
133 tcg_ctx.tb_ctx.tb_phys_hash[h] = tb;
2c90fe2b 134 }
8a40a180
FB		 135 /* we add the TB in the virtual pc hash table */
136 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
8a40a180
FB		 137 return tb;
138}
139
9349b4f9 140static inline TranslationBlock *tb_find_fast(CPUArchState *env)
8a40a180
FB		 141{
142 TranslationBlock *tb;
143 target_ulong cs_base, pc;
6b917547 144 int flags;
8a40a180
FB		 145
146 /* we record a subset of the CPU state. It will
147 always be the same before a given translated block
148 is executed. */
6b917547 149 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
bce61846 150 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
551bd27f
TS		 151 if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
152 tb->flags != flags)) {
cea5f9a2 153 tb = tb_find_slow(env, pc, cs_base, flags);
8a40a180
FB		 154 }
155 return tb;
156}
157
1009d2ed
JK		 158static CPUDebugExcpHandler *debug_excp_handler;
159
84e3b602 160void cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
1009d2ed 161{
1009d2ed 162 debug_excp_handler = handler;
1009d2ed
JK		 163}
164
9349b4f9 165static void cpu_handle_debug_exception(CPUArchState *env)
1009d2ed
JK		 166{
167 CPUWatchpoint *wp;
168
169 if (!env->watchpoint_hit) {
170 QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
171 wp->flags &= ~BP_WATCHPOINT_HIT;
172 }
173 }
174 if (debug_excp_handler) {
175 debug_excp_handler(env);
176 }
177}
178
7d13299d
FB		 179/* main execution loop */
180
1a28cac3
MT		 181volatile sig_atomic_t exit_request;
182
9349b4f9 183int cpu_exec(CPUArchState *env)
7d13299d 184{
c356a1bc 185 CPUState *cpu = ENV_GET_CPU(env);
8a40a180 186 int ret, interrupt_request;
8a40a180 187 TranslationBlock *tb;
c27004ec 188 uint8_t *tc_ptr;
69784eae 189 tcg_target_ulong next_tb;
8c6939c0 190
cea5f9a2 191 if (env->halted) {
3993c6bd 192 if (!cpu_has_work(cpu)) {
eda48c34
PB		 193 return EXCP_HALTED;
194 }
195
cea5f9a2 196 env->halted = 0;
eda48c34 197 }
5a1e3cfc 198
cea5f9a2 199 cpu_single_env = env;
e4533c7a 200
c629a4bc 201 if (unlikely(exit_request)) {
fcd7d003 202 cpu->exit_request = 1;
1a28cac3
MT		 203 }
204
ecb644f4 205#if defined(TARGET_I386)
6792a57b
JK		 206 /* put eflags in CPU temporary format */
207 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
208 DF = 1 - (2 * ((env->eflags >> 10) & 1));
209 CC_OP = CC_OP_EFLAGS;
210 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
93ac68bc 211#elif defined(TARGET_SPARC)
e6e5906b
PB		 212#elif defined(TARGET_M68K)
213 env->cc_op = CC_OP_FLAGS;
214 env->cc_dest = env->sr & 0xf;
215 env->cc_x = (env->sr >> 4) & 1;
ecb644f4
TS		 216#elif defined(TARGET_ALPHA)
217#elif defined(TARGET_ARM)
d2fbca94 218#elif defined(TARGET_UNICORE32)
ecb644f4 219#elif defined(TARGET_PPC)
4e85f82c 220 env->reserve_addr = -1;
81ea0e13 221#elif defined(TARGET_LM32)
b779e29e 222#elif defined(TARGET_MICROBLAZE)
6af0bf9c 223#elif defined(TARGET_MIPS)
e67db06e 224#elif defined(TARGET_OPENRISC)
fdf9b3e8 225#elif defined(TARGET_SH4)
f1ccf904 226#elif defined(TARGET_CRIS)
10ec5117 227#elif defined(TARGET_S390X)
2328826b 228#elif defined(TARGET_XTENSA)
fdf9b3e8 229 /* XXXXX */
e4533c7a
FB		 230#else
231#error unsupported target CPU
232#endif
3fb2ded1 233 env->exception_index = -1;
9d27abd9 234
7d13299d 235 /* prepare setjmp context for exception handling */
3fb2ded1 236 for(;;) {
6ab7e546 237 if (sigsetjmp(env->jmp_env, 0) == 0) {
3fb2ded1
FB		 238 /* if an exception is pending, we execute it here */
239 if (env->exception_index >= 0) {
240 if (env->exception_index >= EXCP_INTERRUPT) {
241 /* exit request from the cpu execution loop */
242 ret = env->exception_index;
1009d2ed
JK		 243 if (ret == EXCP_DEBUG) {
244 cpu_handle_debug_exception(env);
245 }
3fb2ded1 246 break;
72d239ed
AJ		 247 } else {
248#if defined(CONFIG_USER_ONLY)
3fb2ded1 249 /* if user mode only, we simulate a fake exception
9f083493 250 which will be handled outside the cpu execution
3fb2ded1 251 loop */
83479e77 252#if defined(TARGET_I386)
e694d4e2 253 do_interrupt(env);
83479e77 254#endif
3fb2ded1
FB		 255 ret = env->exception_index;
256 break;
72d239ed 257#else
b5ff1b31 258 do_interrupt(env);
301d2908 259 env->exception_index = -1;
83479e77 260#endif
3fb2ded1 261 }
5fafdf24 262 }
9df217a3 263
b5fc09ae 264 next_tb = 0; /* force lookup of first TB */
3fb2ded1 265 for(;;) {
68a79315 266 interrupt_request = env->interrupt_request;
e1638bd8 267 if (unlikely(interrupt_request)) {
268 if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
269 /* Mask out external interrupts for this step. */
3125f763 270 interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
e1638bd8 271 }
6658ffb8
PB		 272 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
273 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
274 env->exception_index = EXCP_DEBUG;
1162c041 275 cpu_loop_exit(env);
6658ffb8 276 }
a90b7318 277#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
b779e29e 278 defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
d2fbca94 279 defined(TARGET_MICROBLAZE) || defined(TARGET_LM32) || defined(TARGET_UNICORE32)
a90b7318
AZ		 280 if (interrupt_request & CPU_INTERRUPT_HALT) {
281 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
282 env->halted = 1;
283 env->exception_index = EXCP_HLT;
1162c041 284 cpu_loop_exit(env);
a90b7318
AZ		 285 }
286#endif
68a79315 287#if defined(TARGET_I386)
5d62c43a
JK		 288#if !defined(CONFIG_USER_ONLY)
289 if (interrupt_request & CPU_INTERRUPT_POLL) {
290 env->interrupt_request &= ~CPU_INTERRUPT_POLL;
291 apic_poll_irq(env->apic_state);
292 }
293#endif
b09ea7d5 294 if (interrupt_request & CPU_INTERRUPT_INIT) {
77b2bc2c
BS		 295 cpu_svm_check_intercept_param(env, SVM_EXIT_INIT,
296 0);
232fc23b 297 do_cpu_init(x86_env_get_cpu(env));
b09ea7d5 298 env->exception_index = EXCP_HALTED;
1162c041 299 cpu_loop_exit(env);
b09ea7d5 300 } else if (interrupt_request & CPU_INTERRUPT_SIPI) {
232fc23b 301 do_cpu_sipi(x86_env_get_cpu(env));
b09ea7d5 302 } else if (env->hflags2 & HF2_GIF_MASK) {
db620f46
FB		 303 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
304 !(env->hflags & HF_SMM_MASK)) {
77b2bc2c
BS		 305 cpu_svm_check_intercept_param(env, SVM_EXIT_SMI,
306 0);
db620f46 307 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
e694d4e2 308 do_smm_enter(env);
db620f46
FB		 309 next_tb = 0;
310 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
311 !(env->hflags2 & HF2_NMI_MASK)) {
312 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
313 env->hflags2 |= HF2_NMI_MASK;
e694d4e2 314 do_interrupt_x86_hardirq(env, EXCP02_NMI, 1);
db620f46 315 next_tb = 0;
e965fc38 316 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
79c4f6b0 317 env->interrupt_request &= ~CPU_INTERRUPT_MCE;
e694d4e2 318 do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0);
79c4f6b0 319 next_tb = 0;
db620f46
FB		 320 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
321 (((env->hflags2 & HF2_VINTR_MASK) &&
322 (env->hflags2 & HF2_HIF_MASK)) ||
323 (!(env->hflags2 & HF2_VINTR_MASK) &&
324 (env->eflags & IF_MASK &&
325 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
326 int intno;
77b2bc2c
BS		 327 cpu_svm_check_intercept_param(env, SVM_EXIT_INTR,
328 0);
db620f46
FB		 329 env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
330 intno = cpu_get_pic_interrupt(env);
4f213879 331 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
332 do_interrupt_x86_hardirq(env, intno, 1);
333 /* ensure that no TB jump will be modified as
334 the program flow was changed */
335 next_tb = 0;
0573fbfc 336#if !defined(CONFIG_USER_ONLY)
db620f46
FB		 337 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
338 (env->eflags & IF_MASK) &&
339 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
340 int intno;
341 /* FIXME: this should respect TPR */
77b2bc2c
BS		 342 cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR,
343 0);
db620f46 344 intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
93fcfe39 345 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
e694d4e2 346 do_interrupt_x86_hardirq(env, intno, 1);
d40c54d6 347 env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
db620f46 348 next_tb = 0;
907a5b26 349#endif
db620f46 350 }
68a79315 351 }
ce09776b 352#elif defined(TARGET_PPC)
9fddaa0c 353 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
c356a1bc 354 cpu_reset(cpu);
9fddaa0c 355 }
47103572 356 if (interrupt_request & CPU_INTERRUPT_HARD) {
e9df014c
JM		 357 ppc_hw_interrupt(env);
358 if (env->pending_interrupts == 0)
359 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
b5fc09ae 360 next_tb = 0;
ce09776b 361 }
81ea0e13
MW		 362#elif defined(TARGET_LM32)
363 if ((interrupt_request & CPU_INTERRUPT_HARD)
364 && (env->ie & IE_IE)) {
365 env->exception_index = EXCP_IRQ;
366 do_interrupt(env);
367 next_tb = 0;
368 }
b779e29e
EI		 369#elif defined(TARGET_MICROBLAZE)
370 if ((interrupt_request & CPU_INTERRUPT_HARD)
371 && (env->sregs[SR_MSR] & MSR_IE)
372 && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
373 && !(env->iflags & (D_FLAG | IMM_FLAG))) {
374 env->exception_index = EXCP_IRQ;
375 do_interrupt(env);
376 next_tb = 0;
377 }
6af0bf9c
FB		 378#elif defined(TARGET_MIPS)
379 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
4cdc1cd1 380 cpu_mips_hw_interrupts_pending(env)) {
6af0bf9c
FB		 381 /* Raise it */
382 env->exception_index = EXCP_EXT_INTERRUPT;
383 env->error_code = 0;
384 do_interrupt(env);
b5fc09ae 385 next_tb = 0;
6af0bf9c 386 }
b6a71ef7
JL		 387#elif defined(TARGET_OPENRISC)
388 {
389 int idx = -1;
390 if ((interrupt_request & CPU_INTERRUPT_HARD)
391 && (env->sr & SR_IEE)) {
392 idx = EXCP_INT;
393 }
394 if ((interrupt_request & CPU_INTERRUPT_TIMER)
395 && (env->sr & SR_TEE)) {
396 idx = EXCP_TICK;
397 }
398 if (idx >= 0) {
399 env->exception_index = idx;
400 do_interrupt(env);
401 next_tb = 0;
402 }
403 }
e95c8d51 404#elif defined(TARGET_SPARC)
d532b26c
IK		 405 if (interrupt_request & CPU_INTERRUPT_HARD) {
406 if (cpu_interrupts_enabled(env) &&
407 env->interrupt_index > 0) {
408 int pil = env->interrupt_index & 0xf;
409 int type = env->interrupt_index & 0xf0;
410
411 if (((type == TT_EXTINT) &&
412 cpu_pil_allowed(env, pil)) ||
413 type != TT_EXTINT) {
414 env->exception_index = env->interrupt_index;
415 do_interrupt(env);
416 next_tb = 0;
417 }
418 }
e965fc38 419 }
b5ff1b31
FB		 420#elif defined(TARGET_ARM)
421 if (interrupt_request & CPU_INTERRUPT_FIQ
422 && !(env->uncached_cpsr & CPSR_F)) {
423 env->exception_index = EXCP_FIQ;
424 do_interrupt(env);
b5fc09ae 425 next_tb = 0;
b5ff1b31 426 }
9ee6e8bb
PB		 427 /* ARMv7-M interrupt return works by loading a magic value
428 into the PC. On real hardware the load causes the
429 return to occur. The qemu implementation performs the
430 jump normally, then does the exception return when the
431 CPU tries to execute code at the magic address.
432 This will cause the magic PC value to be pushed to
a1c7273b 433 the stack if an interrupt occurred at the wrong time.
9ee6e8bb
PB		 434 We avoid this by disabling interrupts when
435 pc contains a magic address. */
b5ff1b31 436 if (interrupt_request & CPU_INTERRUPT_HARD
9ee6e8bb
PB		 437 && ((IS_M(env) && env->regs[15] < 0xfffffff0)
438 || !(env->uncached_cpsr & CPSR_I))) {
b5ff1b31
FB		 439 env->exception_index = EXCP_IRQ;
440 do_interrupt(env);
b5fc09ae 441 next_tb = 0;
b5ff1b31 442 }
d2fbca94
GX		 443#elif defined(TARGET_UNICORE32)
444 if (interrupt_request & CPU_INTERRUPT_HARD
445 && !(env->uncached_asr & ASR_I)) {
d48813dd 446 env->exception_index = UC32_EXCP_INTR;
d2fbca94
GX		 447 do_interrupt(env);
448 next_tb = 0;
449 }
fdf9b3e8 450#elif defined(TARGET_SH4)
e96e2044
TS		 451 if (interrupt_request & CPU_INTERRUPT_HARD) {
452 do_interrupt(env);
b5fc09ae 453 next_tb = 0;
e96e2044 454 }
eddf68a6 455#elif defined(TARGET_ALPHA)
6a80e088
RH		 456 {
457 int idx = -1;
458 /* ??? This hard-codes the OSF/1 interrupt levels. */
e965fc38 459 switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) {
6a80e088
RH		 460 case 0 ... 3:
461 if (interrupt_request & CPU_INTERRUPT_HARD) {
462 idx = EXCP_DEV_INTERRUPT;
463 }
464 /* FALLTHRU */
465 case 4:
466 if (interrupt_request & CPU_INTERRUPT_TIMER) {
467 idx = EXCP_CLK_INTERRUPT;
468 }
469 /* FALLTHRU */
470 case 5:
471 if (interrupt_request & CPU_INTERRUPT_SMP) {
472 idx = EXCP_SMP_INTERRUPT;
473 }
474 /* FALLTHRU */
475 case 6:
476 if (interrupt_request & CPU_INTERRUPT_MCHK) {
477 idx = EXCP_MCHK;
478 }
479 }
480 if (idx >= 0) {
481 env->exception_index = idx;
482 env->error_code = 0;
483 do_interrupt(env);
484 next_tb = 0;
485 }
eddf68a6 486 }
f1ccf904 487#elif defined(TARGET_CRIS)
1b1a38b0 488 if (interrupt_request & CPU_INTERRUPT_HARD
fb9fb692
EI		 489 && (env->pregs[PR_CCS] & I_FLAG)
490 && !env->locked_irq) {
1b1a38b0
EI		 491 env->exception_index = EXCP_IRQ;
492 do_interrupt(env);
493 next_tb = 0;
494 }
8219314b
LP		 495 if (interrupt_request & CPU_INTERRUPT_NMI) {
496 unsigned int m_flag_archval;
497 if (env->pregs[PR_VR] < 32) {
498 m_flag_archval = M_FLAG_V10;
499 } else {
500 m_flag_archval = M_FLAG_V32;
501 }
502 if ((env->pregs[PR_CCS] & m_flag_archval)) {
503 env->exception_index = EXCP_NMI;
504 do_interrupt(env);
505 next_tb = 0;
506 }
f1ccf904 507 }
0633879f
PB		 508#elif defined(TARGET_M68K)
509 if (interrupt_request & CPU_INTERRUPT_HARD
510 && ((env->sr & SR_I) >> SR_I_SHIFT)
511 < env->pending_level) {
512 /* Real hardware gets the interrupt vector via an
513 IACK cycle at this point. Current emulated
514 hardware doesn't rely on this, so we
515 provide/save the vector when the interrupt is
516 first signalled. */
517 env->exception_index = env->pending_vector;
3c688828 518 do_interrupt_m68k_hardirq(env);
b5fc09ae 519 next_tb = 0;
0633879f 520 }
3110e292
AG		 521#elif defined(TARGET_S390X) && !defined(CONFIG_USER_ONLY)
522 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
523 (env->psw.mask & PSW_MASK_EXT)) {
524 do_interrupt(env);
525 next_tb = 0;
526 }
40643d7c
MF		 527#elif defined(TARGET_XTENSA)
528 if (interrupt_request & CPU_INTERRUPT_HARD) {
529 env->exception_index = EXC_IRQ;
530 do_interrupt(env);
531 next_tb = 0;
532 }
68a79315 533#endif
ff2712ba 534 /* Don't use the cached interrupt_request value,
9d05095e 535 do_interrupt may have updated the EXITTB flag. */
b5ff1b31 536 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
bf3e8bf1
FB		 537 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
538 /* ensure that no TB jump will be modified as
539 the program flow was changed */
b5fc09ae 540 next_tb = 0;
bf3e8bf1 541 }
be214e6c 542 }
fcd7d003
AF		 543 if (unlikely(cpu->exit_request)) {
544 cpu->exit_request = 0;
be214e6c 545 env->exception_index = EXCP_INTERRUPT;
1162c041 546 cpu_loop_exit(env);
3fb2ded1 547 }
a73b1fd9 548#if defined(DEBUG_DISAS) || defined(CONFIG_DEBUG_EXEC)
8fec2b8c 549 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
3fb2ded1 550 /* restore flags in standard format */
ecb644f4 551#if defined(TARGET_I386)
e694d4e2
BS		 552 env->eflags = env->eflags | cpu_cc_compute_all(env, CC_OP)
553 | (DF & DF_MASK);
6fd2a026 554 log_cpu_state(env, CPU_DUMP_CCOP);
3fb2ded1 555 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e6e5906b
PB		 556#elif defined(TARGET_M68K)
557 cpu_m68k_flush_flags(env, env->cc_op);
558 env->cc_op = CC_OP_FLAGS;
559 env->sr = (env->sr & 0xffe0)
560 | env->cc_dest | (env->cc_x << 4);
93fcfe39 561 log_cpu_state(env, 0);
e4533c7a 562#else
a73b1fd9 563 log_cpu_state(env, 0);
e4533c7a 564#endif
3fb2ded1 565 }
a73b1fd9 566#endif /* DEBUG_DISAS || CONFIG_DEBUG_EXEC */
5e5f07e0 567 spin_lock(&tcg_ctx.tb_ctx.tb_lock);
cea5f9a2 568 tb = tb_find_fast(env);
d5975363
PB		 569 /* Note: we do it here to avoid a gcc bug on Mac OS X when
570 doing it in tb_find_slow */
5e5f07e0 571 if (tcg_ctx.tb_ctx.tb_invalidated_flag) {
d5975363
PB		 572 /* as some TB could have been invalidated because
573 of memory exceptions while generating the code, we
574 must recompute the hash index here */
575 next_tb = 0;
5e5f07e0 576 tcg_ctx.tb_ctx.tb_invalidated_flag = 0;
d5975363 577 }
f0667e66 578#ifdef CONFIG_DEBUG_EXEC
3ba19255
SW		 579 qemu_log_mask(CPU_LOG_EXEC, "Trace %p [" TARGET_FMT_lx "] %s\n",
580 tb->tc_ptr, tb->pc,
93fcfe39 581 lookup_symbol(tb->pc));
9d27abd9 582#endif
8a40a180
FB		 583 /* see if we can patch the calling TB. When the TB
584 spans two pages, we cannot safely do a direct
585 jump. */
040f2fb2 586 if (next_tb != 0 && tb->page_addr[1] == -1) {
b5fc09ae 587 tb_add_jump((TranslationBlock *)(next_tb & ~3), next_tb & 3, tb);
3fb2ded1 588 }
5e5f07e0 589 spin_unlock(&tcg_ctx.tb_ctx.tb_lock);
55e8b85e 590
591 /* cpu_interrupt might be called while translating the
592 TB, but before it is linked into a potentially
593 infinite loop and becomes env->current_tb. Avoid
594 starting execution if there is a pending interrupt. */
d77953b9 595 cpu->current_tb = tb;
b0052d15 596 barrier();
fcd7d003 597 if (likely(!cpu->exit_request)) {
2e70f6ef 598 tc_ptr = tb->tc_ptr;
e965fc38 599 /* execute the generated code */
cea5f9a2 600 next_tb = tcg_qemu_tb_exec(env, tc_ptr);
2e70f6ef 601 if ((next_tb & 3) == 2) {
bf20dc07 602 /* Instruction counter expired. */
2e70f6ef 603 int insns_left;
69784eae 604 tb = (TranslationBlock *)(next_tb & ~3);
2e70f6ef 605 /* Restore PC. */
622ed360 606 cpu_pc_from_tb(env, tb);
2e70f6ef
PB		 607 insns_left = env->icount_decr.u32;
608 if (env->icount_extra && insns_left >= 0) {
609 /* Refill decrementer and continue execution. */
610 env->icount_extra += insns_left;
611 if (env->icount_extra > 0xffff) {
612 insns_left = 0xffff;
613 } else {
614 insns_left = env->icount_extra;
615 }
616 env->icount_extra -= insns_left;
617 env->icount_decr.u16.low = insns_left;
618 } else {
619 if (insns_left > 0) {
620 /* Execute remaining instructions. */
cea5f9a2 621 cpu_exec_nocache(env, insns_left, tb);
2e70f6ef
PB		 622 }
623 env->exception_index = EXCP_INTERRUPT;
624 next_tb = 0;
1162c041 625 cpu_loop_exit(env);
2e70f6ef
PB		 626 }
627 }
628 }
d77953b9 629 cpu->current_tb = NULL;
4cbf74b6
FB		 630 /* reset soft MMU for next block (it can currently
631 only be set by a memory fault) */
50a518e3 632 } /* for(;;) */
0d101938
JK		 633 } else {
634 /* Reload env after longjmp - the compiler may have smashed all
635 * local variables as longjmp is marked 'noreturn'. */
636 env = cpu_single_env;
7d13299d 637 }
3fb2ded1
FB		 638 } /* for(;;) */
639
7d13299d 640
e4533c7a 641#if defined(TARGET_I386)
9de5e440 642 /* restore flags in standard format */
e694d4e2
BS		 643 env->eflags = env->eflags | cpu_cc_compute_all(env, CC_OP)
644 | (DF & DF_MASK);
e4533c7a 645#elif defined(TARGET_ARM)
b7bcbe95 646 /* XXX: Save/restore host fpu exception state?. */
d2fbca94 647#elif defined(TARGET_UNICORE32)
93ac68bc 648#elif defined(TARGET_SPARC)
67867308 649#elif defined(TARGET_PPC)
81ea0e13 650#elif defined(TARGET_LM32)
e6e5906b
PB		 651#elif defined(TARGET_M68K)
652 cpu_m68k_flush_flags(env, env->cc_op);
653 env->cc_op = CC_OP_FLAGS;
654 env->sr = (env->sr & 0xffe0)
655 | env->cc_dest | (env->cc_x << 4);
b779e29e 656#elif defined(TARGET_MICROBLAZE)
6af0bf9c 657#elif defined(TARGET_MIPS)
e67db06e 658#elif defined(TARGET_OPENRISC)
fdf9b3e8 659#elif defined(TARGET_SH4)
eddf68a6 660#elif defined(TARGET_ALPHA)
f1ccf904 661#elif defined(TARGET_CRIS)
10ec5117 662#elif defined(TARGET_S390X)
2328826b 663#elif defined(TARGET_XTENSA)
fdf9b3e8 664 /* XXXXX */
e4533c7a
FB		 665#else
666#error unsupported target CPU
667#endif
1057eaa7 668
6a00d601 669 /* fail safe : never use cpu_single_env outside cpu_exec() */
5fafdf24 670 cpu_single_env = NULL;
7d13299d
FB		 671 return ret;
672}
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